DE19963689A1 - Circuit arrangement of an integrated semiconductor memory for storing addresses of defective memory cells - Google Patents

Abstract

A circuit arrangement of an integrated semiconductor memory which can be subjected to a memory cell test to determine functional and defective memory cells has addressable normal memory cells (MC) and redundant memory cells (RMC) in each case to replace one of the normal memory cells (MC). A memory unit (2) for storing addresses (ADR) of defective normal memory cells (MC) serves as a buffer. A preprocessing device (3) has a memory device (4, 5) for storing a fixed number of addresses (ADR) of defective normal memory cells (MC). It is used to compare the stored addresses (ADR) and to output an output signal (S31) depending on the comparison result. This serves to control the storage process of the storage unit (2). By means of a suitable comparison between the addresses (ADR), error information can be filtered out for a later redundancy analysis, whereby the size of the memory unit (2) can be kept comparatively small.

Description

The present invention relates to a circuit arrangement an integrated semiconductor memory that a memory Cell test can be subjected to the determination of functional and faulty memory cells, with a memory unit for storing addresses of faulty memory cells len.

Integrated semiconductor memories generally point to the right faulty memory cells redundant memory cells on, mostly to redundant row lines or redundant th column lines are summarized, the regular Lei Replace the addresses with defective memory cells can. The integrated memory, for example with an external test facility or a self-test stone direction checked and then using a so-called Redundancy analysis a programming of the redundant elements performed. A redundancy circuit then has programming bare elements z. B. in the form of programmable fuses, those for storing the address of a line to be replaced serve.

A semiconductor memory device is for example after the Manufacturing process tested and then repaired. Here to become the addresses of those memory cells tested, wel che were detected as defective in a so-called Error address memory stored in a subsequent Step based on the stored addresses this memory cell len to be replaced by error-free redundant memory cells. The memory chip is generally several tests subjected. Only those memory cells that test all exist, are considered functional or error-free. If a memory cell does not pass one or more tests, then  it is considered to be faulty and must be done by faultless speech dante memory cell to be replaced. For semiconductor memories with a matrix-shaped memory cell array, the redundant Have row lines or redundant column lines, is usually egg instead of a single memory cell ne whole row or column line by appropriate red undante row or column lines replaced.

Since memory cells are subjected to several tests, Failing a test before saving the address of one faulty memory cell, the so-called error address check whether the error address has already occurred in a previous one test has been saved. If this is the case, then the Error address cannot be saved a second time Save space. The storage of the error addresses can be checked on the in a separate memory cell array done the chip. This additional memory cell array is then part of, for example, a self-test facility of the Memory chips.

The check to be carried out whether a memory cell be Once saved, the speed at which the memory test is carried out does not affect sen. A parallel comparison can be used, for example all already stored error addresses with the current one Error address and, if applicable, the subsequent spoke of the new address take place together in one clock cycle. However, this generally results in a significant scarf effort for the error address memory to be provided. On serial comparison of the stored error addresses with the current error address is only possible if ensured can be that the time from recognizing a faulty Memory cell until the next faulty one is recognized Memory cell reaches a certain length. This time must be dimensioned such that before a faulty one is recognized Memory cell all comparisons of the mistake already saved Read addresses with the address of a previous faulty one  Memory cell and the possibly required storage of the Address of the previous faulty memory cell ended are. Because in a memory cell test in particular along row lines or column lines are often faulty Memory cells occur in quick succession, the be written period of time is usually not adhered to.

If the number of defective memory cells is small in Ver equal to the memory size, a memory unit can be used as an intermediate memory are provided to test the memory cell field and the storage of the error addresses couple. This buffer must be large enough to ensure that the addresses of as erroneous knew memory cells in the buffer at any time can be written. The maximum size of the provision the cache can be based on the size of the device under test Memory and the existing number of redundant series and column lines can be estimated. For example, who the all memory cells along a column line and tested as many column lines until it is certain that no redundant column line to repair feh Learning memory cells along a column line for Available. The result is a relatively high amount of food of the buffer to be provided. For storage Building blocks with a built-in self-test unit is one such a solution is usually too expensive.

The object of the present invention is a scarf arrangement of a semiconductor memory, the memory cell test is subject to, with a Spei described Memory unit for storing addresses of faulty storage Specify cher cells in which the memory requirements of the memory unit is as low as possible.

The object is achieved by a circuit arrangement integrated semiconductor memory according to the characteristics of Pa  Tent claims 1. Are advantageous training and further education Subject of dependent claims.

The circuit arrangement of the integrated semiconductor memory has addressable in addition to addressable normal memory cells bare redundant memory cells to replace one of the norma len memory cells. Furthermore, the circuit arrangement a storage unit for storing addresses of errors normal memory cells, with a control unit gear to control the storage process of the storage unit and an output for outputting the memory content. A before processing device has a storage device to store a fixed number of addresses learnable normal memory cells. It serves for comparison between the saved addresses and to output a Output signal depending on the comparison result. The preprocessing device also has an output to output the output signal on with the control gang of the storage unit is connected. With such a Circuit arrangement in which Feh lerinformation temporarily stored in the storage unit the size of the storage unit can be kept small the.

The size of the storage unit is kept small by be is already in the intermediate storage in the storage unit Error information, which for the subsequent to the test Repair phase are irrelevant through preprocessing device filtered out and no longer saved the. The comparison carried out for this purpose in the Preprocessing device stored error addresses suitably follows which of the nor paint memory cells through which of the redundant memories cells have to be replaced. So there is a kind of preprocessing Processing the error information, which is missing in the form of addresses lerlicher memory cells is present, with regard to the following redundancy analysis.  

The addresses of memory cells, which are in a matrix gene array are arranged and addressable Units of column lines and row lines together are summarized, or have a first address part on the the respective column line is accessed, and one second address section, via which to the respective row line is accessed. The memory device accordingly device of the preprocessing device, for example, Regi ster units for storing one of the address parts le connected together in the form of a shift register are.

According to one embodiment of the invention are for comparison between the contents of the register units, the outputs of the Register units with corresponding inputs of a ver equal device connected. An output of comparison direction is with the output of the preprocessing device connected and thus to the control input for controlling the Storage process of the storage unit.

As described at the beginning, the (permanent) spoke takes place Error addresses from several tests to be carried out for example in a fault address memory, which is in egg nem separate memory cell array on the half to be tested conductor chip is located. Accordingly, the circuit design order another storage unit for storing addresses of faulty normal memory cells that are connected to the Output of the storage unit is connected to take over of the addresses stored in the storage unit.

Due to the circuit arrangement according to the invention, a fil Error information is already stored in the buffer tion possible in the storage unit, so that a relatively ge rings number of error addresses in the error address memory must be saved. This can save a significant amount of time in the subsequent redundancy analysis, for example in egg  ner self-test unit because a comparatively ge rings number of error addresses from the error address memory must be processed.

The invention is described below with reference to the drawing illustrated figures explained in more detail. Show it:

Fig. 1 is a schematic representation of a matrix-shaped memory cell array of a semiconductor memory,

Fig. 2 shows an embodiment of a circuit arrangement of a semiconductor memory according to the invention.

Fig. 1 is set out, for example, a DRAM, a matrix-like organized memory cell array 1, regular Rei Hen- or word lines WL, column or bit lines BL, redundant word lines RWL and redundancy bit lines RBL has, in their crossing points memory cells MC and redundant memory cells RMC are arranged. The memory cells MC and RMC of the memory shown each contain a selection transistor and a storage capacitor. Control inputs of the selection transistors are connected to one of the word lines WL or redundant word lines RWL, while a main current path of the selection transistors is arranged between the storage capacitor of the respective memory cell MC or RMC and one of the bit lines BL and RBL.

Test systems which have a so-called Fail Address Memory (FAM) use, save the addresses as described above Learning memory cells MC of the module to be tested. The maximum size of the buffer to be provided can be hand the size of the memory cell array to be tested and the existing number of redundant bit lines and redundant th word lines can be estimated. Has a test the memory cell array, for example via r word line WL and cr redundant bit lines RBL, then at one  Memory test, which first up or the word lines WL counts down before the bit line address increments or decremented up to r.cr error addresses before it is certain that the component cannot be repaired can. Conversely, in the case of a memory cell array with c Bit lines BL and rr redundant word lines RWL and ei nem test, the bit lines BL up or down first counts before the word line address increments or is decremented until c.rr error addresses occur, be before it is certain that the block cannot be repaired. The cache must therefore be the maximum number W = c.rr or W = r.cr can record error addresses. For exemplary numerical values r = 2048, rr = 24, c = 512, cr = 8 and an address depth of 24 bits results in a size of 48 KB. For memory chips with a built-in self such a solution is usually too complex.

Fig. 2 shows an embodiment of a circuit arrangement according to the invention. This has a memory unit 2 for storing addresses of faulty normal memory cells with a control input 21 for controlling the memory operation of the memory unit 2 and an output 22 for outputting the memory content. The circuit arrangement also has a preprocessing device 3 , which is connected via the output 31 to the control input 21 of the memory unit 2 for outputting the output signal 531 . The memory unit 2 and the preprocessing device 3 are each supplied with addresses ADR of defective memory cells MC via an address bus. The addresses include a first address part ADR1, via which the respective bit line BL is accessed, and a second address part ADR2, via which the respective word line WL is accessed.

The preprocessing device 3 has memory devices 4 and 5 for storing a fixed number of addresses of defective normal memory cells MC. Each of the memory devices 4 and 5 has register units 6 for storing one of the address parts ADR1 or ADR2, which are connected to one another in the form of a shift register. Outputs 61 of the register units 6 are connected to inputs 71 of a comparison device 7 . The output 72 of the comparison device 7 is connected to the output 31 of the pre-processing device 3 via the controller 9 . A comparison device 8 is connected analogously to the comparison device 7 with corresponding outputs of the storage device 5 and via the controller 9 to the output 31 of the pre-processing device 3 . A signal 91 from the controller 9 is used to switch between the signals 92 and 93 as an input signal from the controller 9 . The clock signal clk and the signal F, which is generated, for example, by a self-test unit, serve as control signals for controlling the storage process of the memory devices 4 and 5 and as input signals of the controller 9 .

The circuit arrangement has a further memory unit 10 , which is used to store addresses of defective normal memory cells MC. The further memory unit 10 is connected to the output 22 of the memory unit 2 for taking over one of the addresses stored in the memory unit 2 . The further memory unit 10 serves, for example, as an error address memory for storing error addresses from a number of function tests carried out. The further storage unit 10 can be located inside or outside the semiconductor memory.

In the following, the sequence of a functional test of the semiconductor memory and the associated mode of operation of the circuit arrangement shown in FIG. 2 is explained in more detail.

An exemplary function test is carried out, by means of which the memory cells MC are first checked along a word line WL before the next word line WL is processed. A complete failure of all the memory cells MC along a word line WL of the memory cell array 1 is also assumed for explanation. As a result of the failure of a word line WL, the memory test generates a new error address in rapid succession with each read access to one of the memory cells MC of the word line WL to be tested, which new address is first stored in the memory unit 2 and then in the error address memory, the further memory unit 10 , is transmitted. As soon as there are more than cr error addresses with the same word line address in the memory unit 2 , it has already been established that a faulty memory cell MC determined according to the following can only be repaired by replacing the corresponding word line WL with a redundant word line RWL. Not enough redundant bit lines RBL are available to replace the defective memory cells MC with redundant bit lines RBL.

For the redundancy analysis following the memory test, in which it is determined which word lines with defective memory cells are to be replaced by redundant word lines, it is therefore irrelevant whether in the error address memory cr + 1 error addresses with identical word line addresses or more have been adopted. As soon as the memory unit contains 2 cr + 1 error addresses with identical word line addresses, no further error addresses with this word line address need to be added. Since the error addresses with identical word line addresses always appear in direct sequence and not distributed over the entire test sequence in the test in question, it is sufficient to check whether the last cr + 1 error addresses have the same word line address. If this is the case, no new error address with the same word line address has to be added to the memory unit 2 . The size of the memory unit 2 is thus limited to the order of magnitude of cr + 1 error addresses.

In such a function test, a maximum of the last cr + 1 error addresses are stored in one of the memory devices 4 or 5 of the preprocessing device 3 . For example, the address part ADR2 of an error address is stored in the register units 6 of the memory device 4 , via which the respective word line device WL is accessed (word line address). The contents of the respective register units 6 , ie the last cr word line addresses, plus the current word line address are checked for agreement via the comparison device 7 . If these word line addresses match, no new error address with this word line address has to be added to the memory unit 2 . Accordingly, the storage process of the storage unit 2 is interrupted via the output 31 .

In a function test in which the word line address is first incremented or decremented before the bit line address is changed, analogous considerations provide that a maximum of rr + 1 error addresses must be stored in the memory unit 2 . It must therefore be checked in the preprocessing device 3 whether the last rr + 1 error addresses have the same bit line address. This is done with the memory device 5 in connection with the comparison device 8 with respect to the address part ADR1 (bit line address). There is a parallel comparison of the current bit line address ADR1 with the last rr addresses that are stored in the memory device 5 .

The size of the memory unit 2 is limited for both types of functional tests to the order of the maximum value from W = rr + 1 or W = cr + 1. In order to be able to guarantee the functionality in a so-called worst-case analysis, the storage unit 2 is expediently dimensioned to double the maximum value W. Such a worst case occurs, for example, when the last memory cells MC tested along a word line WL are defective and after the increment or decrement of the word line address, the memory cells MC of the next word line tested first are defective. For the above numerical example, the storage space requirement of the storage unit 2 is thus reduced to the order of 150 bytes.

The control signal 91 is used to select whether the word line addresses ADR2, bit line addresses ADR1 or both parts of the error addresses are checked for agreement, for example as a result of a changed redundancy analysis. The timing of the storage process or the relevant clock rate is controlled, for example, via the signals F and clk. The transfer of an address stored in the memory unit 2 into the further memory unit 10 is controlled via the control input 23 of the memory unit 2 .

Claims (6)

1. Circuit arrangement of an integrated semiconductor memory, which can be subjected to a memory cell test to determine functional and faulty memory cells

• addressable normal memory cells (MC),
• addressable redundant memory cells (RMC) for replacing one of the normal memory cells (MC),
• a memory unit ( 2 ) for storing addresses (ADR) of defective normal memory cells (MC) with a control input ( 21 ) for controlling the storage process of the memory unit ( 2 ) and an output ( 22 ) for outputting the memory content,
• - A preprocessing device ( 3 ) with at least one memory device ( 4 , 5 ) for storing a fixed number of addresses (ADR) defective normal memory cells (MC), for comparison between the stored addresses (ADR) and for outputting an output signal (S31) depending on the comparison result with an output ( 31 ) which is connected to the control input ( 21 ) of the memory unit ( 2 ).

2. Circuit arrangement according to claim 1, characterized in that

• - The memory cells (MC) are arranged in a matrix-shaped memory cell array ( 1 ),
• the memory cells (MC) are combined into addressable units of column lines (BL) and row lines (WL),
• - The addresses of the memory cells (MC) comprise a first address part (ADR1), via which the respective column line (BL) is accessed, and a second address part (ADR2), via which the respective row line (WL) is accessed.

3. Circuit arrangement according to claim 2, characterized in that the memory device ( 4 , 5 ) has register units ( 6 ) for storing in each case one of the address parts (ADR1, ADR2) which are connected to one another in the form of a shift register. 4. Circuit arrangement according to claim 3, characterized in that

• - outputs ( 61 ) of the register units ( 6 ) are connected to inputs ( 71 ) of a comparison device ( 7 ) for comparison between the contents of the register units ( 6 ),
• - An output ( 72 ) of the comparison device ( 7 ) is connected to the output ( 31 ) of the preprocessing device ( 3 ) for outputting the comparison result.

5. A circuit arrangement according to claim 4, characterized in that in each case the corresponding address parts (ADR2) are in the register units (6) stored, the comparison of the contents of the register units (6) takes place for a match, and if they match, the memory operation of the memory unit (2) is interrupted. 6. Circuit arrangement according to one of the preceding claims, characterized in that the circuit arrangement has a further memory unit ( 10 ) for storing addresses (ADR) of faulty normal memory cells (MC) which are connected to the output ( 22 ) of the memory unit ( 2 ) is connected to take over one of the addresses stored in the memory unit ( 2 ).