CN219873535U - Groove type MOSFET cell structure and device - Google Patents

Abstract

The utility model discloses a groove type MOSFET cell structure and a device, comprising: grid electrode groove, auxiliary source electrode groove and N ⁺ Source region, P-type base region and P ⁺ Buried layer, N drift layer, N ⁺ A substrate, wherein N ⁺ The source region is positioned in the upper part of the P-type base region and is semi-wrapped by the P-type base region, the P-type base region is positioned above the N drift layer, and the N drift layer is positioned at the bottom of the P-type base regionIn N ⁺ A gate trench vertically penetrating N above the substrate ⁺ The source region and the P-type base region extend to the N drift layer, the auxiliary source trench vertically penetrates the P-type base region and extends to the N drift layer, and P ⁺ The buried layer is arranged below the gate trench and the auxiliary source trench and is wrapped by the N drift layer, and P ⁺ The buried layer is located below the grid groove and is discontinuous in the direction parallel to the grid groove and is periodically distributed in space, and the bottom of the auxiliary source groove and P ⁺ The buried layer is in direct contact, an ohmic contact metal layer is arranged at the bottom of the auxiliary source electrode groove, and a diode is integrated on the side wall of the auxiliary source electrode groove. The utility model increases the conduction capacity of the device and reduces the conduction loss.

Description

Groove type MOSFET cell structure and device

Technical Field

The utility model belongs to the technical field of semiconductor devices, and particularly relates to a trench MOSFET cell structure with better double-side conduction capability and a device.

Background

SiC materials have a strong attraction in terms of high power due to their excellent characteristics, and are one of the ideal materials for high-performance power MOSFETs. SiC vertical power MOSFET devices mainly have a lateral double-diffused DMOSFET and a vertical gate trench structure UMOSFET. The DMOSFET structure adopts planar diffusion technology, refractory material such as polysilicon gate is used as mask, and the edge of polysilicon gate is used to define P-type base region and N-type base region ⁺ A source region using a P-type base region and N ⁺ The lateral diffusion of the source regions is differentiated to form surface channel regions. The UMOSFET of the vertical gate groove structure is named as a U-shaped groove structure, the U-shaped groove structure is formed in the gate region by utilizing reactive ion etching, and the U-shaped groove structure has high channel density, so that the on-state characteristic resistance of the device is remarkably reduced. Planar SiC MOSFETs have been studied for many years in the industry and some manufacturers have led to commercial products. For the common lateral DMOSFET structure, the modern technology progress has reached the extent that the on-resistance cannot be reduced due to the reduction of the size of MOS cells, and the main reason is that the on-resistance per unit area is difficult to be reduced to 2mΩ & cm due to the limitation of the resistance of the JFET neck region even if smaller photoetching size is adopted ² And the trench structure can effectively solve the problem. The U-shaped groove structure adopts the groove etching technology invented in each process of manufacturing the memory storage capacitor, so that the conducting channel is changed from transverse to longitudinal, compared with the common structure, the JFET neck resistance is eliminated, the cell density is greatly increased, and the current processing capacity of the power semiconductor is improved.

However, siC UMOSFET still has several problems in practical process fabrication and application: firstly, the high electric field of the SiC drift region results in a high electric field on the gate oxide layer, which is exacerbated at the corners of the trench, thereby causing rapid breakdown of the gate oxide layer at high drain voltages, electrostatic effects to harsh environments, and poor high voltage spike tolerance in the circuit. Secondly, because the SiC power MOSFET is mainly applied to the field of high voltage, high frequency and large current, parasitic parameters in the circuit can cause spike burrs such as overschot and the like to be generated in the high frequency switching process, so that instantaneous overvoltage on a current path of a device is caused, and meanwhile, the loss in the switching process is increased; or a large surge voltage is formed due to a change of a power load or the like, so that the surge voltage resistance and overvoltage protection of the MOSFET are also very important. Because the existing MOSFET device does not have anti-surge voltage self-suppression capability and overvoltage protection capability, a buffer circuit, a surge voltage suppression circuit and an overvoltage protection circuit which are complex in design are often required in practical application. The external matching suppression and overvoltage protection circuit often has time delay, and high-frequency spike voltage surge in the actual switching process is still borne by the device, so that breakdown failure of a channel region of the device and gradual failure of a gate structure and an electrode ohmic contact region are sometimes caused, and the reliability problem of the device is caused. In addition, many targeted trench gate protection structures and anti-surge designs are difficult to implement technically due to the limited ion implantation depth.

To better protect the gate oxide layer of trench MOSFETs, particularly the bottom and trench corners, the industry has three main technical solutions and device structures, including, for example, the structure of source double trench structure on both sides of the gate trench used by Rohm in Japan to shield the middle gate trench bottom, the P used by Infraise in Germany ⁺ Semi-wrapped asymmetric trench structure, P connected to source electrode is constructed on both sides under bottom of trench gate for japanese alumni ⁺ Buried structures. In practical device fabrication and product applications, the Infrax half-wrapped trench MOSFET exhibits better trench gate bottom protection capability and reliability. The device structure analysis and TCAD simulation can also show that the bottom and the groove side P are adopted ⁺ The half-wrap protection mode can construct better trench gate electric field shielding. However, using the quartz halfThe trench-containing structure results in a trench MOSFET that can only pass through one side of the channel conduction path, the other side being used to construct P ⁺ The shield layer sacrifices the conduction trenches, resulting in increased conduction loss of the device cells.

Disclosure of Invention

Aiming at the defects of the prior art, the utility model aims to provide a groove type MOSFET cell structure with better double-side conduction capability, which reduces conduction loss and improves the performance of a device.

In order to achieve the above purpose, the technical scheme adopted by the utility model is as follows:

a trench MOSFET cell structure comprising: grid electrode groove, auxiliary source electrode groove and N ⁺ Source region, P-type base region and P ⁺ Buried layer, N drift layer, N ⁺ A substrate, wherein the N is ⁺ The source region is positioned in the upper part of the P-type base region and is semi-wrapped by the P-type base region, the P-type base region is positioned above the N drift layer, and the N drift layer is positioned on the N ⁺ Above the substrate, the gate trench vertically penetrates the N ⁺ The source region and the P-type base region extend to the N drift layer, the auxiliary source trench vertically penetrates the P-type base region and extends to the N drift layer, and the P ⁺ A buried layer is arranged below the grid groove and the auxiliary source groove and is wrapped by the N drift layer, and the P is a semiconductor device ⁺ The buried layer is located under the grid electrode groove and is discontinuous in the direction parallel to the grid electrode groove and is periodically distributed in space, and the bottom of the auxiliary source electrode groove is connected with the P ⁺ The buried layer is in direct contact, an ohmic contact metal layer is arranged at the bottom of the auxiliary source electrode groove, and a diode is integrated on the side wall of the auxiliary source electrode groove.

In some embodiments, a schottky diode is integrated with a sidewall of the auxiliary source trench, the schottky diode being located in a contact region of the auxiliary source trench and the N drift layer.

In some embodiments, the sidewalls of the auxiliary source trench are integrated with a PIN diode.

In some embodiments, the gate trench bottom and the P ⁺ The buried layers are in direct contact.

In some embodiments, the gate trench bottom and the P ⁺ The buried layer is not in direct contact.

In some embodiments, the gate trench or/and the auxiliary source trench employ a stepped multi-level trench.

In some embodiments, the auxiliary source trench depth is greater than the gate trench depth.

In some embodiments, the auxiliary source trench is discontinuous in a direction parallel to the gate trench.

The utility model also provides a groove type MOSFET device which comprises the groove type MOSFET cell structure.

Compared with the prior art, the utility model has the beneficial effects that:

the utility model adopts one side to construct an auxiliary source electrode groove diode, and simultaneously combines the bottom of the groove gate to be provided with P ⁺ The buried layer is used for constructing a half-package groove type MOSFET cell structure with better double-side conduction capability, so that the conduction capability of the device is improved, and the conduction loss is reduced. Meanwhile, the schottky diode can be integrated on the side wall of the groove diode source electrode at one side, the MPS ohmic contact is integrated at the bottom of the groove diode source electrode, the schottky diode is skillfully integrated into the groove MOSFET, and better follow current characteristics are formed.

Drawings

Fig. 1 is a schematic diagram of a MOSFET structure of embodiment 1;

FIG. 2 is an enlarged schematic view of the section A in FIG. 1;

fig. 3 is a schematic diagram of a MOSFET structure of embodiment 2;

fig. 4 is a schematic diagram of a MOSFET structure of embodiment 3;

fig. 5 is a schematic diagram of a MOSFET structure of embodiment 4;

fig. 6 is a schematic diagram of a MOSFET structure of embodiment 5;

fig. 7 is a schematic diagram of a MOSFET structure of embodiment 6;

fig. 8 is a schematic diagram of a MOSFET structure of embodiment 7;

fig. 9 is a schematic diagram of a MOSFET structure of embodiment 8;

fig. 10 is a schematic diagram of a MOSFET structure of embodiment 9;

FIGS. 11 (a) - (c) are TCAD models of the MOSFET cell structure of example 9;

FIGS. 12 (a) - (c) are simulation analysis results of the TCAD model of example 9.

The attached drawings are identified: 1-N ⁺ Substrate, 2-N drift layer, 3-P ⁺ Buried layer, 4-P type base region, 5-N ⁺ Source region, 6-gate dielectric layer, 7-gate trench, 8-auxiliary source trench, 801-ohmic contact metal layer, 802-schottky diode, 9-drain.

Detailed Description

The present utility model is described in further detail below in conjunction with specific embodiments to make the present utility model more clearly understood by those skilled in the art. The examples are given solely for the purpose of illustration and are not intended to limit the scope of the utility model. In the examples of the present utility model, all raw material components are commercially available products well known to those skilled in the art unless specified otherwise; unless specifically indicated, all technical means used are conventional means well known to those skilled in the art.

The embodiment of the utility model provides a groove type MOSFET cell structure, which comprises the following components: grid electrode groove, auxiliary source electrode groove and N ⁺ Source region, P-type base region and P ⁺ Buried layer, N drift layer, N ⁺ A substrate, wherein N ⁺ The source region is positioned in the upper part of the P-type base region and is semi-wrapped by the P-type base region, the P-type base region is positioned above the N drift layer, and the N drift layer is positioned on the N ⁺ A gate trench vertically penetrating N above the substrate ⁺ The source region and the P-type base region extend to the N drift layer, the auxiliary source trench vertically penetrates the P-type base region and extends to the N drift layer, and P ⁺ The buried layer is arranged below the gate trench and the auxiliary source trench and is wrapped by the N drift layer, and P ⁺ The buried layer is located below the grid groove and is discontinuous in the direction parallel to the grid groove and is periodically distributed in space, and the bottom of the auxiliary source groove and P ⁺ The buried layer is in direct contact, an ohmic contact metal layer is arranged at the bottom of the auxiliary source electrode groove, and a diode is integrated on the side wall of the auxiliary source electrode groove.

In some embodiments, the schottky diode is integrated on the side wall of the auxiliary source trench, and the schottky diode is located in the contact region of the auxiliary source trench and the N drift layer.

In some embodiments, the sidewalls of the auxiliary source trench are integrated with a PIN diode.

In some embodiments, the gate trench bottom and P ⁺ The buried layer is in direct contact with P ⁺ The buried layer is directly contacted with the P, or the bottom of the grid groove is completely contacted with the P ⁺ The buried layer is in direct contact with, or the bottom of the gate trench is P ⁺ The buried layer is wrapped.

In some embodiments, the gate trench bottom and P ⁺ The buried layer is not in direct contact with P ⁺ The depth of the buried layer is deeper, and the better conduction capability is achieved.

In some embodiments, the gate trench and/or the auxiliary source trench are stepped multi-level trenches, and the bottom of the gate trench may be treated with a gate oxide thickening process.

In some embodiments, the auxiliary source trench depth is greater than the gate trench depth, the auxiliary source trench penetrating into P ⁺ Inside the buried layer.

In some embodiments, the auxiliary source trenches are discontinuous in a direction parallel to the gate trenches and are periodically spatially distributed with a larger on-region and a smaller on-resistance.

Example 1

The trench MOSFET cell structure provided in this embodiment, as shown in fig. 1, includes: gate trench 7, auxiliary source trench 8, N ⁺ Source region 5, P-type base region 4, P ⁺ Buried layer 3, N drift layer 2, N ⁺ Substrates 1, N ⁺ The source region 5 is positioned in the upper part of the P-type base region 4 and is semi-wrapped by the P-type base region 4, the P-type base region 4 is positioned above the N drift layer 2, and the N drift layer 2 is positioned at N ⁺ A gate trench 7 vertically penetrating N above the substrate 1 ⁺ The source region 5 and the P-type base region 4 extend to the N drift layer 2, the auxiliary source trench 8 vertically penetrates the P-type base region 4 and extends to the N drift layer 2, P ⁺ Buried layer 3 is located in gate trench 7 and auxiliary sourceThe lower part of the electrode groove 8 is wrapped by the N drift layer 2, P ⁺ The buried layer 3 is located below the gate trench 7, is discontinuous in the direction parallel to the gate trench 7, is periodically distributed in space, and is formed by the bottom part of the gate trench 7 and P ⁺ The buried layer 3 is in direct contact with the bottom of the auxiliary source trench 8 and P ⁺ The buried layer 3 is in direct contact, an ohmic contact metal layer 801 is arranged at the bottom of the auxiliary source electrode groove 8, a Schottky diode 802 is integrated on the side wall of the auxiliary source electrode groove 8, and a drain electrode 9 is positioned at N ⁺ The back of the substrate 1. The bottom and sidewall structures of the auxiliary source trench at section A in FIG. 1 are shown in FIG. 2, the bottom and P of the auxiliary source trench 8 ⁺ Ohmic contact metal layers 801 are formed between the buried layers 3; a schottky diode 802 is integrated between the sidewalls of the auxiliary source trench 8 and the N drift layer 2 to form a schottky contact.

Example 2

The difference between the trench MOSFET cell structure provided in this embodiment and that of embodiment 1 is that the gate trench bottom is completely aligned with P as shown in FIG. 3 ⁺ The buried layers are in direct contact.

Example 3

The difference between the trench MOSFET cell structure provided in this embodiment and that of embodiment 1 is that the bottom of the gate trench is P as shown in FIG. 4 ⁺ The buried layer is wrapped.

Example 4

The trench MOSFET cell structure provided in this embodiment, as shown in fig. 5, differs from embodiments 1-3 in that the sidewalls of the auxiliary source trench are integrated with PIN diodes.

Example 5

The difference between the trench MOSFET cell structure provided in this embodiment and that of embodiments 1-3 is the gate trench bottom and P as shown in FIG. 6 ⁺ The buried layer is not in direct contact.

Example 6

The difference between the trench type MOSFET cell structure provided in this embodiment and embodiments 1-3 is that the gate trench adopts a stepped two-stage trench, and the bottom of the gate trench may adopt a gate oxide thickening process, as shown in fig. 7.

Example 7

The trench MOSFET cell structure provided in this embodiment, as shown in fig. 8, is different from those of embodiments 1-3 in that the auxiliary source trench is a stepped dual-stage trench.

Example 8

The difference between the trench MOSFET cell structure provided in this embodiment and that of embodiments 1-3 is that the depth of the auxiliary source trench is greater than that of the gate trench, as shown in FIG. 9, and the auxiliary source trench extends deep into P ⁺ Inside the buried layer.

Example 9

The trench MOSFET cell structure provided in this embodiment is different from embodiment 1 in that the auxiliary source trenches are discontinuous in the direction parallel to the gate trenches and are periodically distributed in space, as shown in fig. 10.

Simulation analysis is performed on the cell structure of the embodiment based on TCAD, and the results are shown in fig. 11 (a) - (c) and fig. 12 (a) - (c).

Fig. 11 (a) - (c) are TCAD models of a cellular structure according to this embodiment, and fig. 11 (a), 11 (b) and 11 (c) are schematic diagrams of model structures under different viewing angles, respectively, and it can be seen that ohmic contact metal layers are formed at bottoms of the source and auxiliary source trenches, schottky diodes are formed on sidewalls of the auxiliary source trenches, and the auxiliary source trenches are discontinuous in a direction parallel to the gate trenches and are periodically distributed in space.

Fig. 12 (a) shows the current density distribution simulation result of the TCAD model shown in fig. 11 (a) at a gate-source voltage of 20V and a source-drain voltage of 1V, and the Z direction is a direction parallel to the gate trench. As can be seen from fig. 12 (b), at the device cross section where z=0, there is a p+ buried layer under the auxiliary source trench, and only the left side channel is on; as can be seen from fig. 12 (c), at the device cross section where z=1.5, the auxiliary source trench does not have a p+ buried layer under it, and both side channels are on.

The foregoing description of the preferred embodiments of the utility model is not intended to limit the utility model to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the utility model are intended to be included within the scope of the utility model.

Claims (9)

1. Groove type MOSFAn ET cell structure comprising: grid electrode groove, auxiliary source electrode groove and N ⁺ Source region, P-type base region and P ⁺ Buried layer, N drift layer, N ⁺ A substrate, wherein the N is ⁺ The source region is positioned in the upper part of the P-type base region and is semi-wrapped by the P-type base region, the P-type base region is positioned above the N drift layer, and the N drift layer is positioned on the N ⁺ Above the substrate, the gate trench vertically penetrates the N ⁺ The source region and the P-type base region extend to the N drift layer, the auxiliary source trench vertically penetrates the P-type base region and extends to the N drift layer, and the P ⁺ A buried layer is arranged below the grid groove and the auxiliary source groove and is wrapped by the N drift layer, and the P is a semiconductor device ⁺ The buried layer is located under the grid electrode groove and is discontinuous in the direction parallel to the grid electrode groove and is periodically distributed in space, and the bottom of the auxiliary source electrode groove is connected with the P ⁺ The buried layer is in direct contact, an ohmic contact metal layer is arranged at the bottom of the auxiliary source electrode groove, and a diode is integrated on the side wall of the auxiliary source electrode groove.

2. The trench MOSFET cell structure of claim 1, wherein a schottky diode is integrated into a sidewall of the auxiliary source trench, the schottky diode being located in a contact region of the auxiliary source trench and the N drift layer.

3. The trench MOSFET cell structure of claim 1, wherein sidewalls of the auxiliary source trench are integrated with a PIN diode.

4. A trench MOSFET cell structure according to any one of claims 1-3, wherein said gate trench bottom and said P ⁺ The buried layers are in direct contact.

5. A trench MOSFET cell structure according to any one of claims 1-3, wherein said gate trench bottom and said P ⁺ The buried layer is not in direct contact.

6. A trench MOSFET cell structure according to any of claims 1-3, wherein the gate trench or/and the auxiliary source trench are stepped multilevel trenches.

7. A trench MOSFET cell structure according to any of claims 1-3, wherein the auxiliary source trench depth is greater than the gate trench depth.

8. A trench MOSFET cell structure according to any of claims 1-3, wherein said auxiliary source trench is discontinuous in a direction parallel to said gate trench.

9. A trench MOSFET device comprising a trench MOSFET cell structure according to any one of claims 1 to 8.