CN219800110U - Circuit and device for supplying power from equipment to main equipment - Google Patents
Circuit and device for supplying power from equipment to main equipment Download PDFInfo
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- CN219800110U CN219800110U CN202320995944.1U CN202320995944U CN219800110U CN 219800110 U CN219800110 U CN 219800110U CN 202320995944 U CN202320995944 U CN 202320995944U CN 219800110 U CN219800110 U CN 219800110U
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- 230000005669 field effect Effects 0.000 claims abstract description 62
- 239000003990 capacitor Substances 0.000 claims abstract description 14
- 230000002457 bidirectional effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Abstract
The utility model provides a circuit and a device for supplying power to a main device from a slave device, wherein the circuit comprises: the first PMOS field effect transistor, the second PMOS field effect transistor, the first resistor and the capacitor. The S poles of the 2 PMOS field effect transistors are electrically connected together, the D pole of one PMOS field effect transistor is electrically connected with the VDD end of the slave device, the D pole of the other PMOS field effect transistor is electrically connected with the VBUS end of the master device, the G poles of the 2 PMOS field effect transistors are electrically connected with one control port of the power management chip of the master device, and the S poles are electrically connected with the G poles through parallel resistor and capacitor. And a control signal is sent out through the control port so as to enable the 2 PMOS field effect transistors to be conducted, and the circuit is conducted, so that when the slave equipment has surplus power supply capability, the slave equipment can supply power to the master equipment. The circuit can effectively utilize the power supply capability of the slave device, and is matched with the original circuit for supplying power to the slave device by the master device, so that safe and flexible bidirectional power supply is realized between the master device and the slave device.
Description
Technical Field
The utility model relates to the technical field of power supply of master equipment and slave equipment of computers, in particular to a circuit and a device for supplying power to master equipment from equipment.
Background
In the field of computer device technology, a master device generally refers to a device that has master rights, can actively initiate transactions and transmit data, and a slave device can respond to a master device request to transmit data to the master device or receive data from the master device, respectively. Data interaction, including power, between master and slave devices is supported in different protocols, such as PCI (Peripheral Component Interconnect, external device interconnect) bus, USB (Universal Serial Bus ), etc. For example, according to the power supply standard of the USB protocol, a master device supporting the BUS OTG function generally transmits its Vbus to a slave device through a USB cable, so as to implement charging of the slave device.
Typically, the slave devices are powered by the master device. If the master is powered by an internal power source, the slave cannot be powered when the internal power source inventory of the master is too low. Therefore, in the master-slave power supply mode, the master-slave device completely depends on the power supply at one end of the master device, and even if the power supply reserve resource of the slave device is surplus, the power cannot be supplied to the master device, and the full utilization cannot be achieved.
Disclosure of Invention
The utility model aims to provide a circuit and a device for supplying power to a main device from a slave device, wherein when the power of the slave device is redundant, the power supply from the slave device to the main device can be realized if the main device needs external power supply.
To achieve the above object, one embodiment of the present utility model provides a circuit for supplying power from a device to a master device, wherein the circuit includes:
a first PMOS field effect transistor, a second PMOS field effect transistor, a first resistor and a capacitor, wherein,
the D pole of the first PMOS field effect transistor is electrically connected with the power end VDD of the slave device, the G pole is electrically connected with one control port of the power management chip of the master device, and the S pole is electrically connected with the S pole of the second PMOS field effect transistor;
the D pole of the second PMOS field effect transistor is electrically connected with the power supply end VBUS of the main equipment, and the G pole of the second PMOS field effect transistor is electrically connected with the G pole of the first PMOS field effect transistor;
one end of the first resistor is electrically connected with the S electrode of the first PMOS field effect transistor, and the other end of the first resistor is electrically connected with the G electrode of the first PMOS field effect transistor;
the capacitor is connected in parallel with the first resistor.
Further wherein the control port is a GPIO port.
Further, the circuit for supplying power from the slave device to the master device further comprises:
a second resistor, wherein,
one end of the second resistor is electrically connected with one control port of the main equipment power management chip, and the other end of the second resistor is electrically connected with the G pole of the first PMOS field effect transistor.
Another embodiment of the present utility model provides an apparatus for supplying power from a device to a master device, wherein the apparatus includes the circuit of the above embodiment.
The working principle of the utility model is as follows:
besides a normally deployed circuit for supplying power to the slave device by the master device, the circuit provided by the utility model is deployed between the master device and the slave device, and comprises a first PMOS field effect transistor, a second PMOS field effect transistor, a first resistor and a capacitor, wherein the S poles of the 2 PMOS field effect transistors are electrically connected together, the D pole of one PMOS field effect transistor is electrically connected with the VDD end of the slave device, the D pole of the other PMOS field effect transistor is electrically connected with the VBUS end of the master device, the G poles of the 2 PMOS field effect transistors are electrically connected with one control port of a power management chip of the master device, and the S poles are electrically connected with the G poles through parallel resistors and capacitors. Under normal conditions, when the main device supplies power to the auxiliary device through a circuit for supplying power to the auxiliary device by the main device, a control signal is sent out through one control port of the main device power management chip to enable the 2 PMOS field effect transistors to be turned off, the circuit is turned off, the auxiliary device can be prevented from being reversely impacted to the main device through the circuit to affect the normal work of the main device, when the main device does not have surplus power supply capacity to supply power to the auxiliary device, a control signal is sent out through one control port of the main device power management chip to enable the 2 PMOS field effect transistors to be turned on, and when the auxiliary device has surplus power supply capacity, the circuit is turned on, and the auxiliary device can supply power to the main device.
Compared with the prior art, the utility model has the beneficial effects that:
the circuit for supplying power to the master device from the slave device can effectively utilize the power supply capability of the slave device, and can realize safe and flexible bidirectional power supply between the master device and the slave device by matching with the original circuit for supplying power to the slave device from the master device.
Drawings
Other features, objects and advantages of the present utility model will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:
FIG. 1 shows a schematic circuit diagram of a master device powering a slave device;
FIG. 2 shows a schematic circuit diagram for a slave device to power a master device in accordance with one embodiment of the utility model;
FIG. 3 shows a schematic circuit diagram of an alternative embodiment of the present utility model for powering a master device from a slave device;
FIG. 4 shows a schematic diagram of an apparatus for powering a master device from a slave device in accordance with another embodiment of the utility model;
the same or similar reference numbers in the drawings refer to the same or similar parts.
Detailed Description
The existing circuit principle for supplying power from the master device to the slave device is shown in fig. 1, wherein the VBUS terminal of the master device is electrically connected to a switch circuit, the switch circuit is also electrically connected to the VDD terminal of the slave device, and a control terminal EN1 of the power management chip of the master device is electrically connected to the enable terminal of the switch circuit. When EN1 outputs an enable signal and controls the switch circuit to be conducted, the power supply of the master device to the slave device can be realized. The circuit can be deployed on the master device side or on the slave device side. For example, the circuit is typically deployed in a master and slave device that supports USB protocol power functions. When the master device cannot meet the power supply condition, for example, the VBUS output voltage is lower than the preset power supply voltage, the master device cannot supply power to the slave device, even if the power supply of the master device cannot ensure that the master device works normally, at this time, the external device is required to supply power or charge the master device.
The utility model provides a circuit and a device for supplying power to a master device from a slave device.
The technical conception, specific structure and technical effects of a circuit and apparatus for supplying power from a slave device to a master device provided by the present utility model will be further described with reference to the accompanying drawings, so as to fully understand the objects, features and effects of the present utility model. In which embodiments and alternative embodiments of the utility model are shown, it should be understood that those skilled in the art may modify the utility model here described while still achieving the beneficial effects of the utility model. Accordingly, the following description is to be construed as illustrative, and not as a limitation of the present utility model.
Fig. 2 shows a schematic circuit diagram of an embodiment of the present utility model for supplying power from a slave device to a master device, wherein the circuit 10 comprises:
a first PMOS field effect transistor 11, a second PMOS field effect transistor 12, a first resistor 13 and a capacitor 14, wherein,
the D pole of the first PMOS field effect transistor 11 is electrically connected with the power end VDD of the slave device, the G pole is electrically connected with one control port EN2 of the power management chip of the master device, and the S pole is electrically connected with the S pole of the second PMOS field effect transistor 12;
the D pole of the second PMOS field effect tube 12 is electrically connected with the power supply end VBUS of the main equipment, and the G pole is electrically connected with the G pole of the first PMOS field effect tube 11;
one end of the first resistor 13 is electrically connected with the S electrode of the first PMOS field effect transistor 11, and the other end of the first resistor is electrically connected with the G electrode of the first PMOS field effect transistor 11;
a capacitor 14 is connected in parallel with the first resistor 13.
The two PMOS (positive channel Metal Oxide Semiconductor, P-channel metal oxide semiconductor) field effect transistors 11 and 12 have their S poles electrically connected to each other, and the two PMOS field effect transistors 11 and 12 have their G poles electrically connected to a control end EN2 of the main device power management chip, that is, the two PMOS field effect transistors 11 and 12 are reversely connected and controlled by a control signal, and a first resistor 13 is connected between the S poles and the G poles of the PMOS field effect transistors, and the control signal is divided by the first resistor 13 and then supplied to the S poles of the two PMOS field effect transistors 11 and 12 to control the two PMOS field effect transistors 11 and 12 to be turned on or off simultaneously. And a capacitor 14 is connected in parallel with the first resistor 13 between the S pole and the G pole of the PMOS field effect transistor, and when alternating current power is supplied between the master device and the slave device, instant alternating current direction conversion follow current of the alternating current power supply can be completed through the capacitor 14. In an application scenario, the tablet is used as a master device, the slave device is powered by USB, when the VBUS terminal voltage of the power supply of the tablet drops to a level that cannot supply power to the keyboard, or even may cause that a part of functions of the tablet cannot be guaranteed, a control terminal EN2 of the power management chip of the tablet may output a high-level signal, so that 2 PMOS field effect transistors 11 and 12 in the circuit described in this embodiment are turned on, if the keyboard itself has surplus electric energy, the VDD terminal voltage of the power supply of the tablet should be higher than the VBUS terminal voltage of the tablet, and the power supply flow direction is from the keyboard to the tablet, that is, direct current or alternating current power supply from the device to the master device is realized.
Further, in this embodiment, the control port is a GPIO port.
GPIO (General Purpose Input/Output) ports allow developers to customize input or Output high or low levels by software.
In an alternative embodiment, as shown in fig. 3, a circuit for powering a master device from a slave device further comprises:
a second resistor 15, which, among other things,
one end of the second resistor 15 is electrically connected to the control port EN2, and the other end is electrically connected to the G electrode of the first PMOS field-effect transistor 11.
The voltages output by the control ports EN2 of the different power control chips may be different, and a second resistor 15 is electrically connected between EN2 and the G poles of the PMOS field-effect transistors 11 and 12 for adapting to the G pole on voltage of the PMOS field-effect transistors 11 and 12.
Fig. 4 shows a schematic diagram of an apparatus for supplying power from a device to a master device according to another embodiment of the utility model, wherein the apparatus 1 comprises the circuitry of the above-described and/or alternative embodiments.
In addition to the normally deployed circuitry for the master to power the slave between the master and slave, the present utility model provides a circuit and apparatus for the slave to power the master. The circuit comprises a first PMOS field effect tube, a second PMOS field effect tube, a first resistor and a capacitor, wherein the S poles of the 2 PMOS field effect tubes are electrically connected together, the D pole of one PMOS field effect tube is electrically connected with the VDD end of the slave device, the D pole of the other PMOS field effect tube is electrically connected with the VBUS end of the master device, the G poles of the 2 PMOS field effect tubes are electrically connected with a control port of the power management chip of the master device, and the S poles are electrically connected with the G pole through the resistor and the capacitor which are connected in parallel. Under normal conditions, when the main device supplies power to the auxiliary device through a circuit for supplying power to the auxiliary device by the main device, a control signal is sent out through one control port of the main device power management chip to enable the 2 PMOS field effect transistors to be turned off, the circuit is turned off, the auxiliary device can be prevented from being reversely impacted to the main device through the circuit to affect the normal work of the main device, when the main device does not have surplus power supply capacity to supply power to the auxiliary device, a control signal is sent out through one control port of the main device power management chip to enable the 2 PMOS field effect transistors to be turned on, and when the auxiliary device has surplus power supply capacity, the circuit is turned on, and the auxiliary device can supply power to the main device. The circuit and the device for supplying power to the master device from the slave device can effectively utilize the power supply capability of the slave device, and realize safe and flexible bidirectional power supply between the master device and the slave device by matching with the original circuit for supplying power to the slave device from the master device
It should be noted that the above embodiments are only for illustrating the technical solution of the present utility model, and do not limit the present utility model. It should be understood by those skilled in the art that any equivalent replacement or modification of the technical solution and technical content disclosed in the present utility model may be made without departing from the scope of the technical solution of the present utility model, and the scope of the present utility model is covered by the scope of protection of the present utility model.
Furthermore, it is evident that the word "comprising" does not exclude other elements, units or circuits, and that the singular does not exclude a plurality. The plurality of constituent elements, units or circuits recited in the claims may also be implemented as one constituent element, unit or circuit. The terms first, second, etc. are used to denote a name, but not any particular order.
Claims (4)
1. A circuit for a slave device to a master device, the circuit comprising:
a first PMOS field effect transistor, a second PMOS field effect transistor, a first resistor and a capacitor, wherein,
the D pole of the first PMOS field effect transistor is electrically connected with the power end VDD of the slave device, the G pole is electrically connected with one control port of the power management chip of the master device, and the S pole is electrically connected with the S pole of the second PMOS field effect transistor;
the D pole of the second PMOS field effect transistor is electrically connected with the power supply end VBUS of the main equipment, and the G pole of the second PMOS field effect transistor is electrically connected with the G pole of the first PMOS field effect transistor;
one end of the first resistor is electrically connected with the S electrode of the first PMOS field effect transistor, and the other end of the first resistor is electrically connected with the G electrode of the first PMOS field effect transistor;
the capacitor is connected in parallel with the first resistor.
2. The circuit of claim 1, wherein the control port is a GPIO port.
3. The circuit of claim 1, wherein the circuit further comprises:
a second resistor, wherein,
one end of the second resistor is electrically connected with the control port, and the other end of the second resistor is electrically connected with the G electrode of the first PMOS field effect transistor.
4. An apparatus for a slave device to supply power to a master device, the apparatus comprising a circuit as claimed in any one of claims 1 to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320995944.1U CN219800110U (en) | 2023-04-26 | 2023-04-26 | Circuit and device for supplying power from equipment to main equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320995944.1U CN219800110U (en) | 2023-04-26 | 2023-04-26 | Circuit and device for supplying power from equipment to main equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219800110U true CN219800110U (en) | 2023-10-03 |
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ID=88150845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320995944.1U Active CN219800110U (en) | 2023-04-26 | 2023-04-26 | Circuit and device for supplying power from equipment to main equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219800110U (en) |
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2023
- 2023-04-26 CN CN202320995944.1U patent/CN219800110U/en active Active
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