CN219513114U - 4H-SiC-based superjunction power field effect transistor element - Google Patents
4H-SiC-based superjunction power field effect transistor element Download PDFInfo
- Publication number
- CN219513114U CN219513114U CN202221983167.0U CN202221983167U CN219513114U CN 219513114 U CN219513114 U CN 219513114U CN 202221983167 U CN202221983167 U CN 202221983167U CN 219513114 U CN219513114 U CN 219513114U
- Authority
- CN
- China
- Prior art keywords
- region
- source
- drift
- substrate
- drift region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
The utility model discloses a 4H-SiC-based super-junction power field effect transistor element, which comprises a drain electrode, a source electrode and a gate electrode; the drain electrode is attached to the lower surface of the substrate region, a first drift region is arranged on the upper surface of one side of the substrate region, a semiconductor auxiliary region is formed on the upper surface of the other side of the substrate region, a second drift region which is in contact with the first drift region is arranged on the upper surface of the semiconductor auxiliary region, part of the lower surface of the second drift region is in contact with the upper surface of the substrate region, the source region and the source electrode are embedded in the source region side by side, the source region is located on the inner side of the source electrode, the lower surface of the source region is in contact with the upper surface of the second drift region and extends to be in contact with the first drift region, an insulating layer which is in an inverse L shape is further arranged on the upper surface of the first drift region, and the gate region and the gate electrode are sequentially stacked on the insulating layer. The remarkable effects are as follows: the current conducting capability of the device is improved, the switching power consumption of the device is reduced, and the turn-off time is shortened.
Description
Technical Field
The utility model relates to the technical field of semiconductor power devices, in particular to a 4H-SiC-based super junction power field effect transistor element.
Background
Superjunction power MOSFETs, i.e., metal-oxide-semiconductor field effect transistors, are proposed to improve the contradiction between breakdown voltage and specific on-resistance in conventional power MOSFETs, and are widely used in low-to-medium power supply devices. However, the existing super-junction power MOSFET device has the defects of long turn-off time and larger switching power consumption. Therefore, how to further improve the on-current capability of the device, reduce the switching power consumption of the device, and shorten the off-time becomes a new research direction.
Disclosure of Invention
Aiming at the defects of the prior art, the utility model aims to provide a 4H-SiC-based super-junction power field effect transistor element so as to improve the current conducting capability of a device, reduce the switching power consumption of the device and shorten the turn-off time.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
a 4H-SiC based superjunction power field effect transistor element, which is characterized in that: the cell structure is formed by mutually splicing a plurality of repeated cell structures, and the cell structure comprises a drain electrode, a source electrode, a gate electrode, a substrate region, a source body region, a gate region and an insulating layer; the drain electrode is attached to the lower surface of the substrate region, a first drift region is arranged on the upper surface of one side of the substrate region, a semiconductor auxiliary region is formed on the upper surface of the other side of the substrate region, the upper surface of the semiconductor auxiliary region is located below the contact surface of the first drift region and the substrate region, a second drift region which is in contact with the first drift region is arranged on the upper surface of the semiconductor auxiliary region, the thickness of the first drift region is smaller than that of the second drift region, part of the lower surface of the second drift region is in contact with the upper surface of the substrate region, the source region and the source electrode are embedded in the source region side by side, the upper surfaces of the source region and the source electrode are flush with the upper surface of the source region, the source region is located on the inner side of the source electrode, the lower surface of the source region and the upper surface of the second drift region are in contact with the first drift region, the upper surface of the source region is also provided with a L-shaped drift layer, the source region and the lower insulating layer are stacked in sequence, the source region is in contact with the upper surface of the gate layer, the insulating layer is in contact with the lower insulating layer, and the insulating layer is in contact with the upper insulating layer.
Further, the doping types of the source region, the first drift region, the substrate region, the semiconductor auxiliary region and the gate region are different from those of the source body region and the second drift region, and when the doping types of the source region, the first drift region, the substrate region, the semiconductor auxiliary region and the gate region are N-type, the doping types of the source body region and the second drift region are P-type; and when the doping types of the source region, the first drift region, the substrate region, the semiconductor auxiliary region and the gate region are P-type, the doping types of the source body region and the second drift region are N-type.
Further, the doping type of the raised portion of the substrate region is the same as that of the source region, and the doping concentration of the raised portion of the substrate region is lower than that of the non-raised portion of the substrate region and higher than that of the first drift region.
Further, the area of the substrate region in contact with the first drift region is larger than the area of the substrate region in contact with the semiconductor auxiliary region.
Further, the source region, the first drift region, the substrate region, the source body region, the second drift region and the gate region are all made of semiconductor materials, and the drain electrode, the source electrode and the gate electrode are all made of metal materials.
Further, the two sides of the insulating layer wrap the gate region, the upper surfaces of the gate region and the insulating layer are flush with the upper surface of the source body region, and the gate electrode protrudes out of the upper surface of the source body region.
The utility model has the remarkable effects that: the structure is simple and easy to realize, the source body region is sunk, the source electrode is embedded in the sunk position, and the softness of reverse recovery current of the parasitic body diode is guaranteed, and the specific on-resistance of the device is not increased, so that a current path is effectively shortened, the on-current capacity of the device is improved, the switching power consumption of the device is reduced, the switching-off time is shortened, the specific on-resistance of the device is also reduced, the cell size of the device is reduced, the area of the device is further reduced, and the UIS avalanche tolerance capacity of the MOSFET device is improved; and the softness of the reverse recovery current of the parasitic body diode is effectively improved and the reverse recovery characteristic is improved through the arrangement of the semiconductor auxiliary area, so that the device is not easy to oscillate in the switching process, electromagnetic interference signals are inhibited, and the device works more safely and reliably.
Drawings
Fig. 1 is a schematic structural view of the present utility model.
Detailed Description
The following describes the embodiments and working principles of the present utility model in further detail with reference to the drawings.
As shown in fig. 1, a 4H-SiC-based superjunction power field effect transistor element is formed by mutually splicing a plurality of repeated cell structures, where the cell structures include a drain electrode 01, a source electrode 02, a gate electrode 03, a substrate region 12, a source region 10, a source body region 20, a gate region 30 and an insulating layer 40; the drain electrode 01 is attached to the lower surface of the substrate region 12, a first drift region 11 is disposed on the upper surface of one side of the substrate region 12, a semiconductor auxiliary region 15 is formed on the upper surface of the other side of the substrate region 12, the upper surface of the semiconductor auxiliary region 15 is located below the contact surface between the first drift region 11 and the substrate region 12, a second drift region 21 contacting the first drift region 11 is disposed on the upper surface of the semiconductor auxiliary region 15, the thickness of the first drift region 11 is smaller than the thickness of the second drift region 21, a part of the lower surface of the second drift region 21 contacts the upper surface of the substrate region 12, the source region 10 and the source electrode 02 are embedded in parallel with the source region 20, the upper surfaces of the source region 10 and the source electrode 02 are flush with the upper surface of the source region 20, the source region 10 is located inside the source electrode 02 and is connected with a part of the source region 20 through a conductor, the lower surface of the source region 20 contacts the second drift region 21 and the upper surface of the first drift region 40, the upper surface of the source region 40 is in contact with the upper surface of the first drift region 40, the upper surface of the source region 40 is in turn covered with the upper surface of the second drift region 40, the second drift region 40 is in contact with the upper surface of the first drift region 40, the upper surface of the second drift region 40 is in contact with the upper surface of the insulating layer 40, and the upper surface of the second drift region 40 is in turn, the upper surface of the insulating layer 40 is covered with the upper surface of the insulating layer 40 is in contact with the upper surface of the insulating layer 40, and the upper insulating layer 40 is in contact with the upper surface of the upper insulating layer 40.
The cell structure diagram of the 4H-SiC-based super junction power field effect transistor device comprises a voltage-resistant layer formed by a first drift 11 region of a first conductivity type and a second drift region 21 of a second conductivity type, wherein the first drift region 11 is flush with the lower surface of the second drift region 21, and the voltage-resistant layer has two surfaces; at least one source region 20 of the second conductivity type is arranged in the upper surface, at least one heavily doped source region 10 of the first conductivity type is arranged in the source region 20, and part of the source region 10 and part of the source region 20 are connected through conductors to form a source electrode 02 of the device; the surfaces of part of the source region 10, part of the source body region 20 and part of the pressure-resistant layer are covered with an insulating layer 40, the insulating layer 40 is covered with a heavily doped semiconductor polysilicon gate region 30 which is used as a gate electrode of the device, and part of the surface of the gate region 30 is covered with a conductor to form a gate electrode 03 of the device; a heavily doped semiconductor substrate region 12 of the first conductivity type is provided in the lower surface, and the surface of the substrate region 12 is covered with a conductor as a drain electrode 01.
When the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type.
In this example, the doping types of the source region 10, the first drift region 11, the substrate region 12, the semiconductor auxiliary region 15, and the gate region 30 are different from the doping types of the source region 20 and the second drift region 21, and when the doping types of the source region 10, the first drift region 11, the substrate region 12, the semiconductor auxiliary region 15, and the gate region 30 are N-type, the doping types of the source region 20 and the second drift region 21 are P-type; when the doping types of the source region 10, the first drift region 11, the substrate region 12, the semiconductor auxiliary region 15 and the gate region 30 are P-type, the doping types of the source body region 20 and the second drift region 21 are N-type.
Preferably, the raised portions of the substrate region 12 have the same doping type as the source region 10, and the raised portions of the substrate region 12 have a doping concentration lower than the non-raised portions thereof and higher than the doping concentration of the first drift region 11. The doping type of the semiconductor auxiliary region 15 is the same as that of the substrate region 12, and the doping concentration of the semiconductor auxiliary region 15 is lower than that of the first drift region 11.
Further, the area of the substrate region 12 in contact with the first drift region 11 is larger than the area in contact with the semiconductor auxiliary region 15.
Preferably, the source region 10, the first drift region 11, the substrate region 12, the source body region 20, the second drift region 21 and the gate region 30 are all made of semiconductor material, and the drain electrode 01, the source electrode 02 and the gate electrode 03 are all made of metal material. The semiconductor material is silicon, gallium arsenide, gallium nitride or silicon carbide.
The most important point of the embodiment is that the source body region 20 is sunk and the source electrode 02 is embedded in the sunk position on the premise of ensuring the softness of the reverse recovery current of the parasitic body diode and not increasing the specific on-resistance of the device, so that the current path is effectively shortened, the cell size of the device is reduced, the area of the device is further reduced, and the UIS avalanche capacity of the MOSFET device is improved. In addition, the softness of the reverse recovery current of the parasitic body diode is effectively improved and the reverse recovery characteristic is improved through the arrangement of the semiconductor auxiliary area 15, so that the device is not easy to oscillate in the switching process, electromagnetic interference signals are restrained, and the device works more safely and reliably.
The technical scheme provided by the utility model is described in detail. The principles and embodiments of the present utility model have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present utility model and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the utility model can be made without departing from the principles of the utility model and these modifications and adaptations are intended to be within the scope of the utility model as defined in the following claims.
Claims (6)
1. The 4H-SiC-based super junction power field effect transistor element is formed by mutually splicing a plurality of repeated cell structures, wherein each cell structure comprises a drain electrode, a source electrode and a gate electrode, and the device is characterized in that: the semiconductor device further comprises a substrate region, a source body region, a gate region and an insulating layer; the drain electrode is attached to the lower surface of the substrate region, a first drift region is arranged on the upper surface of one side of the substrate region, a semiconductor auxiliary region is formed on the upper surface of the other side of the substrate region, the upper surface of the semiconductor auxiliary region is located below the contact surface of the first drift region and the substrate region, a second drift region which is in contact with the first drift region is arranged on the upper surface of the semiconductor auxiliary region, the thickness of the first drift region is smaller than that of the second drift region, part of the lower surface of the second drift region is in contact with the upper surface of the substrate region, the source region and the source electrode are embedded in the source region side by side, the upper surfaces of the source region and the source electrode are flush with the upper surface of the source region, the source region is located on the inner side of the source electrode, the lower surface of the source region and the upper surface of the second drift region are in contact with the first drift region, the upper surface of the source region is also provided with a L-shaped drift layer, the source region and the lower insulating layer are stacked in sequence, the source region is in contact with the upper surface of the gate layer, the insulating layer is in contact with the lower insulating layer, and the insulating layer is in contact with the upper insulating layer.
2. The 4H-SiC-based superjunction power field effect transistor element of claim 1, wherein: the doping types of the source region, the first drift region, the substrate region, the semiconductor auxiliary region and the gate region are different from those of the source body region and the second drift region, and when the doping types of the source region, the first drift region, the substrate region, the semiconductor auxiliary region and the gate region are N-type, the doping types of the source body region and the second drift region are P-type; and when the doping types of the source region, the first drift region, the substrate region, the semiconductor auxiliary region and the gate region are P-type, the doping types of the source body region and the second drift region are N-type.
3. The 4H-SiC-based superjunction power field effect transistor element of claim 2, wherein: the doping type of the protruding portion of the substrate region is the same as that of the source region, and the doping concentration of the protruding portion of the substrate region is lower than that of the non-protruding portion of the substrate region and higher than that of the first drift region.
4. The 4H-SiC-based superjunction power field effect transistor element of claim 1, wherein: the area of the substrate region in contact with the first drift region is larger than the area in contact with the semiconductor auxiliary region.
5. The 4H-SiC-based superjunction power field effect transistor element of claim 1, wherein: the source region, the first drift region, the substrate region, the source body region, the second drift region and the gate region are all made of semiconductor materials, and the drain electrode, the source electrode and the gate electrode are all made of metal materials.
6. The 4H-SiC-based superjunction power field effect transistor element of claim 1, wherein: the grid region is wrapped on two sides of the insulating layer, the upper surfaces of the grid region and the insulating layer are flush with the upper surface of the source body region, and the grid electrode protrudes out of the upper surface of the source body region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221983167.0U CN219513114U (en) | 2022-07-29 | 2022-07-29 | 4H-SiC-based superjunction power field effect transistor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221983167.0U CN219513114U (en) | 2022-07-29 | 2022-07-29 | 4H-SiC-based superjunction power field effect transistor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219513114U true CN219513114U (en) | 2023-08-11 |
Family
ID=87530145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221983167.0U Active CN219513114U (en) | 2022-07-29 | 2022-07-29 | 4H-SiC-based superjunction power field effect transistor element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219513114U (en) |
-
2022
- 2022-07-29 CN CN202221983167.0U patent/CN219513114U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10388737B2 (en) | Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) devices having an optimization layer | |
| CN101552291B (en) | Semiconductor tube of hyperconjugation longitudinal double diffusion metal oxide with N channels | |
| CN108231903B (en) | Super junction power MOSFET with soft recovery body diode | |
| CN113130627B (en) | Silicon carbide fin-shaped gate MOSFET integrated with channel diode | |
| CN104201206A (en) | Horizontal SOI power LDMOS (lateral double-diffusion metal oxide semiconductor) device | |
| US11211485B2 (en) | Trench power transistor | |
| CN112802906B (en) | Separated gate planar MOSFET device with floating gate | |
| CN108198857A (en) | A kind of silicon carbide MOSFET device structure cell of integrated convex block shape Schottky diode | |
| CN112164722A (en) | Shielded gate MOSFET device with uniformly doped channel and processing technology | |
| CN107564965B (en) | Transverse double-diffusion MOS device | |
| CN107170801B (en) | A kind of shield grid VDMOS device improving avalanche capability | |
| CN103515443B (en) | A kind of super junction power device and manufacture method thereof | |
| CN112447822A (en) | Semiconductor power device | |
| CN107546274B (en) | LDMOS device with step-shaped groove | |
| CN111933711B (en) | SBD integrated super-junction MOSFET | |
| CN212659542U (en) | Semiconductor power device with buried conductive medium channel region split gate structure | |
| CN219513114U (en) | 4H-SiC-based superjunction power field effect transistor element | |
| CN219513115U (en) | Car rule grade 4H-SiC base super junction power MOSFET component | |
| CN109065629A (en) | A kind of slot grid superjunction devices | |
| CN217788404U (en) | 4H-SiC-based super-junction power field effect transistor structure | |
| CN217788401U (en) | 4H-SiC-based super-junction power field effect transistor device | |
| CN107863378B (en) | Super junction MOS device and manufacturing method thereof | |
| CN217788405U (en) | 4H-SiC-based super-junction power field effect transistor | |
| CN107785416A (en) | Junction field effect transistor and its manufacture method | |
| CN109994549B (en) | Semiconductor power device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |