CN218918835U

CN218918835U - Semiconductor packaging device

Info

Publication number: CN218918835U
Application number: CN202222380872.8U
Authority: CN
Inventors: 吕文隆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2022-09-07
Filing date: 2022-09-07
Publication date: 2023-04-25
Anticipated expiration: 2032-09-07

Abstract

The present application relates to semiconductor packaging devices. The semiconductor package apparatus includes: the silicon medium layer comprises a thick region and a thin region, the thickness of the thick region is larger than that of the thin region, the silicon medium layer comprises a first surface and a second surface which face opposite, and the thin region is thinned from the first surface to the second surface; and a conductive hole penetrating the thin region and electrically connecting the first surface and the second surface of the silicon interposer. The semiconductor packaging device is beneficial to reducing the manufacturing cost of the through silicon via, and meanwhile, the structural strength and the service life of the semiconductor packaging device are improved.

Description

Semiconductor packaging device

Technical Field

The application relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging device.

Background

In the process of fabricating 2.5D/3D packaged through silicon vias (through silicon via, TSV), the wafer thinning operation is performed first, but the thinned wafer is weakened in strength and is easily broken due to external force, which is limited by the aspect ratio (aspect ratio) process capability and the specification of the diameter of the through silicon vias. In addition, there is a method of not thinning, in which through-silicon vias are respectively formed from both ends of a wafer and are connected to each other, but the strength at the junction of the through-silicon vias is low, the through-silicon vias are easily broken by external force, and the cost of manufacturing two through-silicon vias is doubled.

Therefore, a new solution is needed to solve at least one of the above technical problems.

Disclosure of Invention

The application provides a semiconductor packaging device.

The application provides a semiconductor packaging apparatus, which is characterized by comprising:

a silicon interposer comprising a thick region and a thin region, the thickness of the thick region being greater than the thickness of the thin region, the silicon interposer comprising oppositely facing first and second surfaces, the thin region being thinned from the first surface to the second surface;

and a conductive hole penetrating the thin region and electrically connecting the first surface and the second surface of the silicon interposer.

In some alternative embodiments, the upper surface of the conductive via is lower than the upper surface of the thick region.

In some alternative embodiments, an isolation layer is disposed between the conductive via and the thin region sidewall.

In some alternative embodiments, the upper surface of the isolation layer is higher than the upper surface of the thin region.

In some alternative embodiments, the upper surface of the conductive via is higher than the upper surface of the isolation layer.

In some alternative embodiments, the thin region has a thickness greater than zero.

In some alternative embodiments, the upper surface of the conductive via is higher than the upper surface of the thin region.

In some alternative embodiments, the second surface of the silicon interposer is provided with a wiring layer.

In some alternative embodiments, the first surface of the wiring layer is electrically connected to the second surface of the silicon interposer, and the second surface of the wiring layer is electrically connected to an external element.

In some alternative embodiments, the wiring layer is a rewiring layer.

In some alternative embodiments, the thin region has a thickness of zero.

In some alternative embodiments, the first surface of the thin region is provided with electronic components.

The semiconductor packaging device utilizes the thin area to manufacture the through silicon via, reduces the depth of the through silicon via, simultaneously utilizes the thick area to provide enough supporting strength for the whole structure, avoids wafer breakage, is favorable for reducing the manufacturing cost of the through silicon via, and simultaneously improves the structural strength and the service life of the semiconductor packaging device.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:

FIG. 1 is a schematic diagram of a prior art semiconductor package apparatus;

fig. 2-9 are schematic diagrams of semiconductor package apparatus according to embodiments of the present application;

fig. 10 to 17 are schematic views of a manufacturing process of a semiconductor package apparatus according to an embodiment of the present application.

Symbol description:

11. a silicon interposer; 12. an insulating material; 13. a through silicon via; 14. a first conductive via; 15. a second conductive via; 100. a silicon interposer; 110. a thick region; 120. a thin region; 121. a first conductive pad; 130. a first electronic component; 140. a groove; 200. a conductive hole; 210. an isolation layer; 220. a seed layer; 230. solder; 300. a circuit layer; 302. a second conductive pad; 310. an electrical connection hole; 400. a second electronic component; 500. a molding material; 900. a carrier; 910. a barrier layer; 920. opening holes; 930. and (3) a protective layer.

Detailed Description

The technical problems to be solved by the present application and the technical effects to be produced will be readily apparent to those skilled in the art from the descriptions of the present application, which are described in the following detailed description of the present application with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting of the utility model. In addition, for convenience of description, only a portion related to the related utility model is shown in the drawings.

It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are merely used in conjunction with the descriptions of the embodiments and should not be construed as limiting the applicable limitations of the present application, so that any modification, variation of proportions, or adjustment of sizes of structures, proportions, etc. which are not intended to affect the efficacy of the present application or the objects achieved, are still within the scope of what is disclosed herein. Also, the terms "upper", "first", "second", and "a" and "an" as used in the present specification are merely for descriptive purposes and are not intended to limit the scope of the utility model in which the utility model may be practiced or their relative relationships may be altered or modified without materially altering the technical context.

It should be further noted that, in the embodiment of the present application, the corresponding longitudinal section may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the upper view direction.

It should be readily understood that the meanings of "on," "above," and "above" in this application should be interpreted in the broadest sense so that "on" means not only "directly on" but also "on" including intermediate components or layers that exist therebetween.

Moreover, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In addition, embodiments and features of embodiments in this application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 is a schematic view of a semiconductor package apparatus in the prior art.

The first way of making through silicon vias is shown in the upper part of fig. 1. As shown in the upper part of fig. 1, the silicon interposer 11 is thinned (the upper part is the thinned silicon interposer 11 and the lower part is the non-thinned silicon interposer 11 in comparison with the upper part and the lower part of fig. 1), and then an insulating material 12 and a through silicon via 13 are disposed on the thinned silicon interposer 11 to electrically connect both sides of the silicon interposer 11.

In the above-described manner, the thinned silicon interposer 11 becomes weak in strength and is easily broken by external force.

The lower part of fig. 1 shows a second way of making through silicon vias. As shown in the lower part of fig. 1, the original thickness of the silicon interposer 11 is maintained, and first conductive vias 14 are provided from the upper surface of the silicon interposer 11, and second conductive vias 15 are provided from the lower surface of the silicon interposer 11. The first conductive via 14 and the second conductive via 15 are communicated inside the silicon interposer 11, and together, the electrical connection of both sides of the silicon interposer 11 is achieved.

In the above manner, the joint between the first conductive hole 14 and the second conductive hole 15 has low strength, is easily broken by external force, and the cost of manufacturing the two conductive holes is doubled.

Fig. 2 is a schematic view of a semiconductor package apparatus according to an embodiment of the present application. As shown in fig. 2, the semiconductor package apparatus includes a silicon interposer 100 and conductive vias 200.

The silicon interposer 100 includes thick regions 110 and thin regions 120. The thickness of the silicon material of thick region 110 is greater than the thickness of the silicon material of thin region 120. The thin region 120 is thinned from the upper surface of the silicon interposer 100 to the lower surface of the silicon interposer 100. The lower surface of thin region 120 is at the same level as the lower surface of thick region 110. The upper surface of thin region 120 is lower than the upper surface of thick region 110. The upper surface of thin region 120 and the inner sidewall of thick region 110 together form a recess 140.

Conductive vias 200 extend through thin region 120 to electrically connect the upper and lower surfaces of silicon interposer 100.

In some embodiments, as shown in fig. 2, the lower surface of the silicon interposer 100 is provided with a wiring layer 300. The wiring layer 300 is, for example, a rewiring layer (Re-distribution Layer, RDL). The lower surface of the wiring layer 300 may be provided with an external element (not shown). The wiring layer 300 can electrically connect the silicon interposer 100 with external components (not shown).

In some embodiments, as shown in fig. 2, a lower surface of the silicon interposer 100 is provided with a first electronic component 130. The first electronic component 130 is, for example, a sensor (sensor).

In some embodiments, as shown in fig. 2, the upper surface of the conductive via 200 is higher than the upper surface of the Bao Ou, and the portion of the conductive via 200 that is higher than the upper surface of the thin region 120 can be used to connect other electronic components, such as the second electronic component 400 of fig. 5.

Fig. 3 is a partial enlarged view of the semiconductor package apparatus of fig. 2. As shown in fig. 3, the lower surface of the thin region 120 is provided with a first conductive pad 121. The wiring layer 300 includes an electrical connection hole 310 and a second conductive pad 302. The electrical connection hole 310 electrically connects the first conductive pad 121 and the second conductive pad 302. The lower end of the conductive via 200 is electrically connected to the second conductive pad 302, and the upper end of the conductive via 200 is provided with solder 230. A seed layer 220 and an isolation layer 210 are disposed between the sidewalls of the thin region 120 and the conductive via 200.

The conductive via 200 may be fabricated by an electroplating process and the seed layer 220 may serve as a base layer for metal growth during the electroplating process.

The isolation layer 210 is an insulating material for electrically isolating the conductive via 200 from the thin region 120.

In some embodiments, as shown in fig. 3, the upper surface of the spacer layer 210 is higher than the upper surface of Bao Ou. If the upper surface of the isolation layer 210 is flush with the upper surface of the thin region 120, the solder 230 may overflow around in a molten state, and thus may overflow to the upper surface of the thin region 120 through the upper surface of the isolation layer 210, thereby damaging the electrical isolation between the conductive via 200 and the thin region 120. In the case that the upper surface of the isolation layer 210 is higher than the upper surface of the Bao Ou, the surface tension of the solder 230 in the molten state limits the surface tension to the upper surface of the isolation layer 210, so that the solder 230 is prevented from overflowing to the upper surface of the thin region 120, and the electrical isolation between the conductive via 200 and the thin region 120 is ensured.

In some embodiments, as shown in fig. 3, the upper surface of the conductive via 200 is higher than the upper surface of the isolation layer 210. The portion of the conductive via 200 above the isolation layer 210 may serve as a core for the solder 230 to coalesce in the molten state, reducing the risk of solder 230 overflowing.

Fig. 4 shows a top view of the semiconductor package apparatus of fig. 2 and its vicinity. As shown in fig. 4, the silicon interposer 100 includes a thick region 110 and four thin regions 120. The upper surface of each thin region 120 forms a recess 140 with the sidewalls of the thick region 110. A plurality of conductive vias 200 are disposed within each recess 140.

Fig. 5 shows a modification of the semiconductor package apparatus of fig. 2. As shown in fig. 5, the upper surface of the thin region 120 is provided with a second electronic component 400. The second electronic component 400 is located in the recess 140 formed in the upper surface of the thin region 120 and the inner side wall of the thick region 110. The second electronic component 400 is, for example, a functional chip. The above-described manner is advantageous in reducing the longitudinal dimension of the semiconductor package apparatus relative to the arrangement of the second electronic component 400 on the surface of the thick region 110.

As shown in fig. 5, a molding material 500 is provided above the silicon interposer 100. The molding material 500 is used to protect the silicon interposer 100 and the second electronic component 400.

Fig. 6 and 7 show variations of the semiconductor package apparatus of fig. 3, respectively. In fig. 3, the upper surface of the isolation layer 210 is higher than the upper surface of Bao Ou, and the upper end of the seed layer 220 is flush with the upper surface of the isolation layer 210. In fig. 6, the upper surface of the isolation layer 210 is flush with the upper surface of the thin region 120, and the upper end of the seed layer 220 is higher than the upper surface of the isolation layer 210. In fig. 7, the upper surface of the isolation layer 210 is flush with the upper surface of the thin region 120, and the upper end of the seed layer 220 is flush with the upper surface of the isolation layer 210.

Fig. 8 shows a modification of the semiconductor package apparatus of fig. 2. In fig. 2, the lateral dimensions of the wiring layer 300 are smaller than the lateral dimensions of the silicon interposer 100. In fig. 8, the lateral dimensions of the wiring layer 300 are equal to those of the silicon interposer 100.

Fig. 9 shows a modification of the semiconductor package apparatus of fig. 8. In fig. 8, the thickness of thin region 120 is greater than zero. In fig. 9, the thickness of the silicon material of the thin region 120 (see fig. 8) is zero, the groove 140 is formed by the thick region 110 and the wiring layer 300 together, and the bottom surface of the groove 140 is formed by the upper surface of the wiring layer 300.

The semiconductor package apparatus of fig. 9 may be obtained by further etching away all of the silicon material of the thin region 120 on the basis of the semiconductor package apparatus of fig. 8. The conductive via 200 in fig. 9 is formed on the basis of the thin region 120 (see fig. 8), but the silicon material of the thin region 120 is removed in the final structure, which is a "TSV-less" technology.

In the semiconductor packaging device of this embodiment, the conductive holes 200 (through-silicon vias) are fabricated by using the thin regions 120, so that the depth of the through-silicon vias is reduced, and meanwhile, the thick regions 110 are used to provide sufficient supporting strength for the whole structure, so that wafer breakage is avoided, the fabrication cost of the through-silicon vias is reduced, and meanwhile, the structural strength and the service life of the semiconductor packaging device are improved.

In one example, the thin region 120 has a thickness between tens of microns to the substrate microns. The distance between the outer sidewall and the nearest inner sidewall (i.e., the "shoulder width") of thick region 110 is greater than or equal to 10 microns and less than or equal to 200 microns. The distance between adjacent conductive vias 200 is greater than or equal to 5 microns and less than or equal to 50 microns. Thin region 120 has a thickness greater than or equal to zero and less than or equal to 100 microns. The diameter of the upper end of the conductive via 200 is greater than or equal to 1 micron and less than or equal to 20 microns. The thin region 120 has an opening diameter greater than or equal to 2 microns and less than or equal to 30 microns. The ratio of the diameter of the upper end of the conductive via 200 to the diameter of the opening of the thin region 120 is greater than or equal to 0.2 and less than or equal to 1. The ratio of the thickness of thin region 120 to the diameter of the opening of thin region 120 is greater than or equal to 0.1 and less than or equal to 20. The difference in height between the upper surface of spacer layer 210 and the upper surface of thin region 120 is greater than or equal to 1 micron and less than or equal to 20 microns. The difference in height between the upper surface of the conductive via 200 and the upper surface of the isolation layer 210 is greater than or equal to 1 micron and less than or equal to 20 microns.

Fig. 10 to 17 are schematic views of a manufacturing process of a semiconductor package apparatus according to an embodiment of the present application. The manufacturing process comprises the following steps:

in a first step, as shown in fig. 10, a silicon interposer 100 is provided, wherein a first electronic component 130 is disposed on an upper surface of the silicon interposer 100 (since the silicon interposer 100 is flipped in a subsequent step, the first electronic component 130 is disposed on a lower surface of the silicon interposer 100 in the final structure).

In the second step, as shown in fig. 11, the silicon interposer 100 is turned over, and the thin region 120 is etched on the silicon interposer 100 by the processes of photoresist coating, exposure, development, etching, etc., the non-etched portion forms the thick region 110, and the upper surface of the thin region 120 and the inner sidewall of the thick region 110 together form the groove 140.

Third, as shown in fig. 12, a barrier layer 910 is provided on the upper surface of the silicon interposer 100. The material of the blocking layer 910 is, for example, polyimide (PI).

Fourth, as shown in fig. 13, the silicon interposer 100 is flipped over again and placed on the carrier 900, and openings 920 are formed in the thin regions 120 of the silicon interposer 100 by photoresist coating, exposure, development, etching, and the like. Wherein the barrier layer 910 is capable of blocking the etching down to prevent the thick region 110 or the carrier 900 from being etched.

Fifth, as shown in fig. 14, a protective layer 930 is disposed on the surface of the first electronic component 130. The material of the protective layer 930 is, for example, polyimide (PI). The protection layer 930 is capable of protecting the first electronic component 130 during a subsequent process (e.g., etching).

Sixth, as shown in fig. 15, conductive holes 200 are formed in the thin region 120 by Physical Vapor Deposition (PVD), photoresist coating, exposure, development, electroplating, and the like.

Seventh, as shown in fig. 16, a wiring layer 300 is formed on the upper surface of the silicon interposer 100, and the carrier 900 and the protective layer 930 are removed.

In the eighth step, as shown in fig. 17, the silicon interposer 100 is turned over again, and the thin region 120 is further thinned (etched) to obtain the semiconductor package device, wherein the conductive via protrudes from the upper surface of the thin region 120. Further, the thin region 120 is completely removed (completely etched away), resulting in a "TSV-less" structure as shown in FIG. 9.

While the present application has been described and illustrated with reference to particular embodiments thereof, the description and illustration is not intended to be limiting. It will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments thereof without departing from the true spirit and scope of the application as defined by the appended claims. The illustrations may not be drawn to scale. There may be a distinction between technical reproductions in this application and actual equipment due to variables in the manufacturing process, etc. Other embodiments of the present application not specifically described may exist. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present application. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present application. Thus, unless specifically indicated herein, the order and grouping of operations is not a limitation of the present application.

Claims

1. A semiconductor package apparatus, comprising:

2. The semiconductor package apparatus according to claim 1, wherein an upper surface of the conductive via is lower than an upper surface of the thick region.

3. The semiconductor package apparatus according to claim 2, wherein an isolation layer is provided between the conductive via and the thin-region sidewall.

4. A semiconductor package apparatus according to claim 3, wherein an upper surface of the isolation layer is higher than an upper surface of the thin region.

5. The semiconductor package apparatus according to claim 4, wherein an upper surface of the conductive via is higher than an upper surface of the isolation layer.

6. The semiconductor package apparatus of claim 1, wherein the thickness of the thin region is greater than zero.

7. The semiconductor package apparatus according to claim 6, wherein an upper surface of the conductive via is higher than an upper surface of the thin region.

8. The semiconductor package apparatus of claim 1, wherein the second surface of the silicon interposer is provided with a wiring layer.

9. The semiconductor package apparatus of claim 8, wherein the first surface of the wiring layer is electrically connected to the second surface of the silicon interposer, and wherein the second surface of the wiring layer is electrically connected to an external component.

10. The semiconductor package apparatus according to claim 9, wherein the thickness of the thin region is zero.