CN216793620U - Semiconductor processing apparatus - Google Patents

Abstract

The present invention provides a semiconductor processing apparatus, comprising: a first chamber portion; a second chamber portion movable relative to the first chamber portion between an open position and a closed position, wherein when the second chamber portion is in the closed position relative to the first chamber portion, a microchamber is formed between the first chamber portion and the second chamber portion in which a semiconductor wafer can be received, and when the second chamber portion is in the open position relative to the first chamber portion, the semiconductor wafer can be taken out or placed in; at least one of the first chamber part and the second chamber part comprises a main body part and an embedded part, wherein a surface of the main body part facing the micro chamber is provided with a embedded groove, and the embedded part is embedded into the embedded groove to form a whole with the main body part. Thus, the deformation error of the embedded part caused by the difference between the processing temperature and the working temperature can be greatly reduced, thereby improving the precision of the semiconductor processing device.

Description

Semiconductor processing apparatus

[ technical field ] A method for producing a semiconductor device

The present invention relates to the field of semiconductor wafer processing, and more particularly to a semiconductor processing apparatus.

[ background of the utility model ]

The precise edge etch process of semiconductor wafers is a challenging process. It requires that the micron-scale precise etching of the wafer edge be realized without damaging or contaminating the remaining portion of the film. In the epitaxial wafer process and the advanced integrated circuit process, the wafer edge etching process is an important step for ensuring the film formation quality and improving the chip yield.

Please refer to fig. 1a to fig. 1d, wherein: FIG. 1a is a schematic diagram of a semiconductor wafer 400, and FIG. 1b is a cross-sectional view E-E of FIG. 1 a; FIG. 1c is a partial cross-sectional view of the outer edge of a semiconductor wafer prior to outer edge processing; FIG. 1d is a cross-sectional view of a peripheral portion of a semiconductor wafer after peripheral processing. As shown in fig. 1a to 1d, the semiconductor wafer 400 includes a substrate layer 401 and a thin film layer 402 formed on a first edge surface and a second edge surface of the substrate layer 401. After the selective etching process for the first edge surface 404, the second wafer surface 406, and the outer-end bevel edge 408 of the outer edge portion of the semiconductor wafer 400, the thin film layer 402 of the outer edge portion of the semiconductor wafer 400 is removed, and the first edge surface and the second edge surface of the base material layer 401 are exposed.

The existing wafer edge etching equipment can be divided into a dry method and a wet method. The dry method is mainly divided into a plasma method and a polishing method. The plasma edge etching method has high equipment cost and relatively complex method, and is mainly applied to the manufacture procedure of integrated circuit chips. The polishing method is to remove the film by rotating the wafer and utilizing physical friction and chemical gas-liquid combination. The polishing method has low equipment cost, but is easy to damage and pollute the reserved film part, and is mainly applied to the manufacturing process of wafers with the thickness of less than 200 mm. The wet method mainly includes a film pasting method and a vacuum adsorption method. The film sticking method adopts pure anticorrosive PTFE, PE and other plastic films to protect the part of the film to be preserved, and then the whole film is exposed to a chemical corrosive gas environment or soaked in a chemical corrosive liquid to corrode the exposed part. The film pasting method has multiple process steps and needs to be completed by using various devices, wherein the devices comprise film pasting, wet etching, cleaning, film removing and the like. The vacuum adsorption method uses a vacuum suction head to suck the wafer, the vacuum suction head has the functions of sucking the wafer, protecting the part of the thin film to be kept in the vacuum suction head, exposing the part of the thin film to be removed out of the vacuum suction head, and then soaking the vacuum suction head and the wafer in a chemical etching solution to etch off the part of the thin film exposed out of the vacuum suction head. The vacuum adsorption method has simple process steps and lower equipment cost, but the condition that the part of the preserved film is damaged and polluted is easy to occur, and the method is mainly applied to the manufacturing process of the wafer with the thickness of less than 200 mm.

Chinese patent application No. 201821459515.8 entitled "a semiconductor processing apparatus" discloses an edge processing scheme for semiconductor wafers. However, the difference between the manufacturing temperature and the operating temperature of the upper chamber part and the lower chamber part may cause a slight error between the size during manufacturing and the size during operation, which affects the wafer edge processing accuracy.

In view of the foregoing, there is a need for an improved semiconductor processing apparatus that reduces the effects of thermal expansion and contraction.

[ Utility model ] content

The utility model aims to provide a semiconductor processing device which can reduce the influence caused by thermal expansion and cold contraction.

To achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor processing apparatus comprising: a first chamber portion; a second chamber part movable relative to the first chamber part between an open position and a closed position, wherein when the second chamber part is in the closed position relative to the first chamber part, a microchamber is formed between the first chamber part and the second chamber part, and a semiconductor wafer can be accommodated in the microchamber, and when the second chamber part is in the open position relative to the first chamber part, the semiconductor wafer can be taken out or put in; at least one of the first chamber part and the second chamber part comprises a main body part and an embedded part, wherein a surface of the main body part facing the micro chamber is provided with a embedded groove, and the embedded part is embedded into the embedded groove to form a whole with the main body part.

Compared with the prior art, at least one of the first chamber part and the second chamber part in the utility model consists of a main body part and an embedded part, wherein a surface of the main body part facing the micro chamber is provided with an embedded groove, the embedded part is embedded into the embedded groove to form a whole with the main body part, the thermal expansion coefficient of the main body part in a normal temperature state is smaller than that of the embedded part in the normal temperature state, the volume of the embedded part is reduced, the total expansion or reduction degree caused by temperature change is reduced, and meanwhile, the expansion range of the embedded part can be controlled through the size selection of the embedded groove of the main body part and the size selection of the embedded part, so that the influence of the thermal contraction and expansion on the embedded part can be controlled.

[ description of the drawings ]

The present invention will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:

FIG. 1a is a schematic view of a semiconductor wafer;

FIG. 1b is a cross-sectional view E-E of FIG. 1 a;

FIG. 1c is a cross-sectional view of a peripheral portion of a semiconductor wafer prior to peripheral processing;

FIG. 1d is a cross-sectional view of a peripheral portion of a semiconductor wafer after peripheral processing;

FIG. 2a is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a first embodiment;

FIG. 2b is an enlarged schematic view of circle A in FIG. 2 a;

FIG. 3a is a bottom view of a first chamber portion of the semiconductor processing apparatus of FIG. 2 a;

FIG. 3b is a top view of a second chamber portion of the semiconductor processing apparatus of FIG. 2 a;

FIG. 4 is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a second embodiment;

FIG. 5 is an enlarged schematic view of circle B in FIG. 4;

FIG. 6a is a bottom view of a first chamber portion of the semiconductor processing apparatus of FIG. 4;

FIG. 6b is a top view of a second chamber portion of the semiconductor processing apparatus of FIG. 4;

FIG. 7a is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a third embodiment;

FIG. 7b is an enlarged schematic view of circle D in FIG. 7 a;

figure 8 is an exploded isometric view of the lower chamber portion of figure 7 a.

[ detailed description ] embodiments

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least an implementation of the utility model. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. The terms "plurality" or "a plurality" in the present invention mean two or more. "and/or" in the present invention means "and" or ".

The first embodiment:

referring to fig. 2a to fig. 3b, schematic structural diagrams of a semiconductor processing apparatus 100 according to a first embodiment of the present invention are shown, wherein: FIG. 2a is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a first embodiment; FIG. 2b is an enlarged schematic view of circle A in FIG. 2 a; FIG. 3a is a bottom view of a first chamber portion of the semiconductor processing apparatus of FIG. 2 a; figure 3b is a top view of a second chamber portion of the semiconductor processing apparatus of figure 2 a.

Referring to fig. 2a to 3b, the semiconductor processing apparatus 100 includes a first chamber part 110 and a second chamber part 120. The first chamber portion 110 includes a first chamber plate 119 and a flange 118 extending from a periphery of the first chamber plate 119. The second chamber portion 120 includes a second chamber plate 129 and a flange 128 extending around the periphery of the second chamber plate 129.

The first chamber portion 110 is movable relative to the second chamber portion 120 between an open position and a closed position. It should be noted that the movement of the first chamber portion 110 and the second chamber portion 120 is relative, and the first chamber portion 110 may be fixed to allow the second chamber portion 120 to move relative to each other, the second chamber portion 120 may be fixed to allow the first chamber portion 110 to move relative to each other, and the first chamber portion 110 and the second chamber portion 120 may both move simultaneously, as long as the first chamber portion 110 and the second chamber portion 120 can move relative to each other. When the first chamber portion 110 is in a closed position relative to the second chamber portion 120, the ledge 118 cooperates with the ledge 128 to form a micro chamber 140 between the first chamber plate 118 and the second chamber plate 128, and a semiconductor wafer 400 to be processed can be received in the micro chamber 140 to be subsequently processed. When the first chamber portion 110 is in an open position relative to the second chamber portion 120, the ledge 118 is spaced from the ledge 128 and the semiconductor wafer 400 to be processed can be removed from or placed in the microchamber 140.

The first chamber portion 110 has a first annular channel 116 formed on a side facing the microchamber 140, and the second chamber portion 120 has a second annular channel 126 formed on a side facing the microchamber 140. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 is received in the micro chamber, the first channel 116 and the second channel 126 together form an edge micro processing volume 130, and the outer edge of the semiconductor wafer 400 received in the micro chamber extends into the edge micro processing volume 130.

As shown in fig. 2a to 3b, in the present embodiment, the first channel 116 and the second channel 126 are annular channels. When the second chamber portion 120 is located in the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 is received in the micro chamber, the wall surface 117 of the first chamber portion 110 located inside the first channel 116 abuts against the first edge surface of the semiconductor wafer 400 to be processed, the wall surface 127 of the second chamber portion 120 located inside the second channel 126 abuts against the second edge surface of the semiconductor wafer 400 to be processed, the first channel 116 and the second channel 126 enclose the closed annular rim micro-processing space 130, and the rim portion of the semiconductor wafer 400 to be processed, which is to be processed, is received in the rim micro-processing space 130.

Therefore, in this embodiment, the edge micro-processing space 130 can selectively process the entire peripheral portion of the semiconductor wafer 400 to be processed.

Of course, the first slot 116 and the second slot 126 may be configured as arcuate slots having an arc of less than 360 degrees. At this point, the first channel 116 and the second channel 126 form a closed, arcuate peripheral micro-processing space 130 having an arc less than 360 degrees therebetween. Accordingly, a partial arc of the outer edge of the semiconductor wafer 400 to be processed is accommodated within the edge micro-processing space 130. Thus, the edge micro-processing volume 130 now only enables selective processing of a partial arc of the outer edge of the semiconductor wafer 400 to be processed.

The first chamber part 110 has at least two edge treatment through holes 112 passing through the first chamber part 110 from the outside to communicate with the edge micro treatment space 130, wherein: at least one edge treatment through hole serves as a fluid inlet and at least one edge treatment through hole serves as a fluid outlet. In this embodiment, 4 edge processing through holes are provided. Of course, the second chamber part 120 may be provided with an edge processing through hole communicating with the edge micro processing space 130.

In use, a processing fluid can enter the edge micro processing space 130 through one of the edge processing through holes 112, the fluid entering the edge micro processing space 130 can flow in the edge micro processing space 130, and the processing fluid can contact and process the peripheral portion of the semiconductor wafer 400 to be processed contained in the edge micro processing space 130, and the fluid processed on the semiconductor wafer 400 to be processed can flow out through the other edge processing through hole 112 or out through an edge processing through hole disposed on the second chamber part 120 and communicated with the edge micro processing space 130. During processing, processing fluid can be continuously or at intervals introduced into the edge micro processing volume 130 through an edge processing via 112, and the fluid in the edge micro processing volume 130 can flow during processing, which can increase processing speed.

Of course, the treatment may be an etching treatment on the outer edge of the semiconductor wafer 400 to remove the thin film layer on the outer edge of the semiconductor wafer 400, or may be a selective cleaning of only the outer edge of the semiconductor wafer 400, or the like.

Take the example of the corrosion removal of the thin film layer at the outer edge portion of the semiconductor wafer 400 to be processed. Referring to fig. 1a to 1d and fig. 2a to 3b in combination, when it is required to etch away the thin film layers of the first and second sides of the outer edge of the semiconductor wafer 400 to be processed. Only the corresponding processing fluid having a corrosive effect on the thin film layer needs to be introduced into the edge micro processing space 130 through one edge processing through hole 112, and the processing fluid flows in the edge micro processing space 130 and directly contacts the outer edge portion of the semiconductor wafer 400 to be processed. The processing fluid flows along the edge of the semiconductor wafer 400 to be processed and reacts with the surface of the wafer accommodated in the edge micro-processing space, so that the thin film layer 402 on the first edge surface, the second edge surface and the bevel edge of the outer edge of the semiconductor wafer 400 to be processed is removed by erosion. As shown in fig. 1d, after the processing, the portion of the thin film layer 402 of the outer edge of the semiconductor wafer 400 accommodated in the edge micro-processing space 130 is etched away, and the first edge surface, the second edge surface and the outer end bevel edge of the substrate layer 401 of the outer edge of the semiconductor wafer 400 are exposed. The fluid processed on the semiconductor wafer 400 to be processed flows out through the other edge processing vias.

It can be seen that, based on the edge micro-processing space 130, the semiconductor processing apparatus 100 of the present embodiment only needs to consume a small amount of processing fluid to realize selective etching treatment on the outer edge of the semiconductor wafer 400 to be processed, which greatly reduces the processing cost and the amount of production waste liquid. In addition, the semiconductor processing apparatus 100 of the present embodiment has a significant advantage of simple structure, convenience in use, and low requirement for the operating skill of the operator, as compared with the dry method apparatus of the related art.

It can be seen that the semiconductor processing apparatus 100 provided in the present embodiment can realize selective processing of the outer edge of the semiconductor wafer 400 to be processed. In addition, by controlling the flow rate of the processing fluid within the semiconductor wafer 400 to be processed, the amount of the processing fluid can be saved while ensuring the processing effect. With continued reference to fig. 2a to 2b, in the present embodiment, the first chamber portion 110 further has a first recess 115 formed on an inner wall surface of the first chamber portion 110 facing the micro chamber, the first recess being located inside the first channel 116, and the second chamber portion 120 further has a second recess 125 formed on an inner wall surface of the second chamber portion 120 facing the micro chamber, the second recess being located inside the second channel 126. The first recess 115 and the second recess 125 are also annular. When the second chamber part 120 is located at the closed position relative to the first chamber part 110 and the semiconductor wafer 400 to be processed is accommodated in the micro chamber, a partial region of the second edge surface of the semiconductor wafer 400 to be processed covers the top of the second recess 125 to form a second inner micro-space, a partial region of the first edge surface of the semiconductor wafer 400 to be processed covers the top of the first recess 115 to form a first inner micro-space, and the first inner micro-space and the second inner micro-space are located inside the edge micro-processing space 130.

Correspondingly, the first chamber part 110 has a first inner process through hole communicating with the first recess 115, and the second chamber part 120 has a second inner process through hole communicating with the second recess 125. When the edge of the semiconductor wafer 400 is etched using the edge micro processing space 130, a liquid or gas, such as water or nitrogen, may be introduced into the first recess 115 and the second recess 125, i.e., into the first inner micro space and the second inner micro space, to prevent the liquid in the edge micro processing space 130 from penetrating inward.

Similarly, the first and second recesses 115 and 125 may be curved.

With continued reference to fig. 2 a-2 b, in this embodiment, the second chamber portion 120 and the first chamber portion 110 further have a micro chamber 140 formed in the middle thereof when in the closed position, the second chamber portion 120 has a middle process through hole 123 in communication with the micro chamber 140, and the first chamber portion 110 has a middle process through hole 113 in communication with the micro chamber 140.

Referring to fig. 2b, the first chamber part 110 has a sealing joint 210 located outside the first channel 116, and the second chamber part 120 has a joint groove 122 corresponding to the sealing joint 210. The sealing interface 210 includes a leading surface 211 at the distal end and an inboard surface 212. When the second chamber portion 120 is located at the closed position relative to the first chamber portion 110, the end of the sealing joint 210 extends into the joint groove 122, the end portion of the inner surface 212 is in sealing engagement with the groove wall of the joint groove 122, and the upper end portion of the inner surface 212 forms the outer side of the rim micro-processing space 130. In addition, the end portion of the inner side surface 212 of the sealing joint 210 and the sealing surface of the groove wall of the joint groove 122 are located below the outer edge micro-processing space 130 and perpendicular to the extending direction of the semiconductor wafer 400, so that the wall surface 117 of the first chamber part 110 located inside the first channel 116 abuts against the first edge surface of the semiconductor wafer 400 to be processed more tightly, and the wall surface 127 of the second chamber part 120 located inside the second channel 126 abuts against the second edge surface of the semiconductor wafer 400 to be processed more tightly, thereby preventing the corrosive liquid from penetrating inwards.

In the embodiment of fig. 2b, the inner side surface 212 of the sealing joint 210 may enable centering of the semiconductor wafer 400 during closing of the second chamber part 120 relative to the first chamber part 110, i.e. if the center of the semiconductor wafer 400 when placed deviates from the desired center, the inner edge surface 212 of the sealing joint 210 may also be corrected to the desired center by pressing against the semiconductor wafer 140. In one example, it is desirable that the center deviation of the semiconductor wafer 400 not exceed 0.2mm when edge processing is performed, and in this manner of the present invention, the center deviation can be adjusted to within 0.1 mm. The guide surface 211 may guide the sealing engagement portion 210 into the engagement groove 122 when the first chamber part 110 and the second chamber part 120 are closed. The sealing engagement portion 210 may be caught in the engagement groove 122.

Referring to fig. 2a, the first chamber portion 110 includes a positioning groove 114, and the second chamber portion 120 includes a positioning post 124, so that the first chamber portion 110 and the second chamber portion 120 can be positioned correctly when closed. During the closing process of the first chamber portion 110 and the second chamber portion 120, the positioning posts 124 are first positioned and engaged with the positioning slots 114 to achieve the initial positioning, and then the ends of the sealing joints 210 extend into the joint grooves 122.

In one embodiment, the semiconductor processing apparatus 100 of the present invention is used to perform a silicon oxide wafer edge etching process, and the specific method may include closing the chamber, HF acid etching, DIW rinsing, IPA rinsing, nitrogen drying, and opening the chamber. The specific procedures of HF acid etching, DIW (deionized water) rinsing and IPA (isopropyl alcohol) rinsing can all be operated in accordance with the above-described flow scheme. In particular, during the HF acid etching, a liquid or gas, such as water or nitrogen, etc., may be introduced into the first and second recesses 115 and 125 to prevent the liquid in the edge micro-processing space 130 from penetrating inward.

Second embodiment

Referring to fig. 4 to fig. 6b, schematic structural diagrams of a semiconductor processing apparatus 200 according to a second embodiment of the present invention are shown, wherein: FIG. 4 is a schematic cross-sectional view of a semiconductor processing apparatus in accordance with the present invention in a first embodiment; FIG. 5 is an enlarged schematic view of circle B in FIG. 4; FIG. 6a is a bottom view of a first chamber portion of the semiconductor processing apparatus of FIG. 4; figure 6b is a top view of a second chamber portion of the semiconductor processing apparatus of figure 4.

The semiconductor processing apparatus 200 in the second embodiment has the same structure as the semiconductor processing apparatus 100 in the first embodiment, and therefore the same reference numerals are used for the same parts, and the difference between them is mainly: the seal joint 310 of the semiconductor processing apparatus 200 and the seal joint 210 of the semiconductor processing apparatus 100 have some differences in structure.

As shown in fig. 5, the first chamber part 110 has the sealing joint part 310 located outside the first channel 116, and the second chamber part 120 has the joint groove 122 corresponding to the sealing joint part 210.

The sealing joint 310 includes a leading surface 311 at a distal end, an inner side surface 312 at an inner upper end, and a projection 313 at an inner distal end. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110, the end of the sealing joint 310 extends into the engaging groove 122, the protrusion 313 thereof is in sealing fit with the groove wall of the engaging groove 122, and the inner surface 312 thereof forms the outer side of the peripheral micro-processing space 130. The inner side surface 312 is still spaced a distance from the outer edge of the semiconductor wafer 400.

The sealing surface formed by the projection 313 of the sealing joint 310 and the groove wall of the joint groove 122 is located below the outer edge micro processing space 130 and is perpendicular to the extending direction of the semiconductor wafer 400, so that the wall surface 117 of the first chamber part 110 located at the inner side of the first channel 116 abuts against the first side surface of the semiconductor wafer 400 to be processed more tightly, and the wall surface 127 of the second chamber part 120 located at the inner side of the second channel 126 abuts against the second side surface of the semiconductor wafer 400 to be processed more tightly, thereby preventing the corrosive liquid from penetrating inwards.

In the embodiment of fig. 2b, during the closing of the second chamber part 120 relative to the first chamber part 110, the bump 313 of the sealing joint 310 may enable the centering of the semiconductor wafer 140, i.e. if the center of the semiconductor wafer 140 when placed deviates from the desired center, the bump 313 of the sealing joint 310 may also be adjusted to the desired center by pressing against the semiconductor wafer 140.

Since the inner side surface 312 is still spaced a distance from the outer edge of the semiconductor wafer 400. Thus, the semiconductor wafer 400 may not be easily clamped by the sealing interface 310 when the second chamber portion 120 is disengaged with respect to the first chamber portion 110.

In another embodiment, the bump 313 may not be used for centering the semiconductor wafer 400, i.e., the bump 313 does not contact the edge of the semiconductor wafer 400. While the wall edges of the first channel 116 may be used to center the semiconductor wafer 400.

Third embodiment

FIG. 7a is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a third embodiment; FIG. 7b is an enlarged schematic view of circle D in FIG. 7 a; figure 8 is an exploded isometric view of the lower chamber portion of figure 7 a.

As shown in fig. 7a and 7b, the semiconductor processing apparatus includes a first chamber part 110 and a second chamber part 120. When the second chamber part 120 is located at the closed position with respect to the first chamber part 110, a micro chamber in which the semiconductor wafer 400 can be accommodated is formed between the first chamber part 110 and the second chamber part 120, and when the second chamber part 120 is located at the open position with respect to the first chamber part 110, the semiconductor wafer 400 can be taken out or put in.

Similar to the first and second embodiments, the first channel formed in the first chamber part 110 and the second channel formed in the second chamber part 120 communicate with each other and may form an edge micro processing space together with the edge of the semiconductor wafer, and the edge micro processing space may be used to perform an edge process on the semiconductor wafer 400. The structure and description of the edge processing of the semiconductor wafer 400 using the edge micro-processing space will not be repeated in this embodiment.

The difference compared to the first and second embodiments is that the first chamber part 110 in this embodiment includes a first main body portion 1105 and a first embedded portion 1104. A first fitting groove 1106 is formed in a surface of the first body portion 1105 facing the micro chamber, and the first fitting portion 1104 is fitted into the first fitting groove 1106 integrally with the first body portion 1105. As shown in fig. 8, the second chamber portion 120 includes a second body portion 1205 and a second insertion portion 1204, a second fitting groove 1206 is formed on a surface of the second body portion 1205 facing the micro chamber, and the second insertion portion 1204 is inserted into the second fitting groove 1206 and is integrally formed with the second body portion 1205.

As shown in fig. 7a and 8, the fitting grooves 1106 and 1206 are both ring-shaped, the embedding parts 1104 and 1204 are ring-shaped to match with the fitting grooves 1106 and 1206, respectively, when the semiconductor wafer 400 is accommodated in the micro chamber, the edge part of the semiconductor wafer 400 corresponds to the surfaces of the embedding parts 1104 and 1204, the edge part of the semiconductor wafer 400 is located between the embedding parts 1104 and 1204, and the middle part of the semiconductor wafer 400 corresponds to the main body parts 1105 and 1205.

In one embodiment, the main body portion has a thermal expansion coefficient smaller than that of the embedded portion at normal temperature, which may be 10 to 30 degrees, for example. More specifically, the insertion portion may be made of PTFE (polytetrafluoroethylene), and the main body portion may be made of PVC (polyvinyl chloride). When the low-temperature embedding part is placed into the embedding groove of the main body part during manufacturing, the embedding part expands to fully support the embedding groove when the normal temperature state is reached, and therefore the embedding part and the main body part can be assembled. Thereafter, the first chamber part or the second chamber part may be made of a material in which the insert part and the body part are integrated.

There may be a temperature difference, for example, between 3 degrees and 10 degrees, between the temperature at which the first and second chamber portions are made and the temperature at which the first and second chamber portions are used. However, since the coefficient of thermal expansion of the PTFE material is large at normal temperature, the first chamber part and the second chamber part made of the PTFE material have large dimensional changes due to the temperature difference between the first chamber part and the second chamber part during manufacture and use, which causes a problem of excessive error. For example, when the edge etching process is performed, the diameter of the etched edge line of the semiconductor wafer has a certain error due to thermal expansion and contraction of the first chamber and the second chamber, which affects the etching accuracy, and the error is sometimes unacceptable. In the present invention, the insert part is made of PTFE material only, and the main body part is made of PVC material, which has a lower coefficient of thermal expansion at normal temperature than PTFE material, and since the insert part has a reduced volume and is held by the main body part, the thermal expansion of the insert part is suppressed by the main body part, so that the influence of the temperature difference between the manufacture and use on the first chamber part and the second chamber part can be reduced. In addition, the PVC material is cheaper than the PTFE material, and the manufacturing cost is reduced by the mode of the utility model.

The first chamber portion and/or the second chamber portion in the first and second embodiments may be formed by combining an insertion portion and a main body portion, in which case the first channel may be formed on the insertion portion of the first chamber portion, the second channel may be formed on the insertion portion of the second chamber portion, the sealing engagement portion may be formed on the insertion portion of the first chamber portion, and the engagement groove may be formed on the insertion portion of the second chamber portion.

In another embodiment, only one of the first chamber portion and the second chamber portion may be formed by combining the insert portion and the main body portion.

In another alternative embodiment, the fitting groove may be circular, and the embedding portion may be circular to match the fitting groove, and when the semiconductor wafer is accommodated in the micro chamber, both the middle portion and the edge portion of the semiconductor wafer correspond to the surface of the embedding portion.

In another alternative embodiment, the semiconductor processing apparatus including the chamber portion formed by combining the embedded portion and the main body portion may be used not only for edge processing of the semiconductor wafer but also for other processes of the semiconductor wafer, such as cleaning, drying, etching of the entire surface, and the like.

The foregoing description has disclosed fully preferred embodiments of the present invention. It should be noted that those skilled in the art can make modifications to the embodiments of the present invention without departing from the scope of the appended claims. Accordingly, the scope of the claims of the present invention should not be limited to the particular embodiments described.

Claims (11)

1. A semiconductor processing apparatus, comprising:

a first chamber portion;

a second chamber portion movable relative to the first chamber portion between an open position and a closed position, wherein when the second chamber portion is in the closed position relative to the first chamber portion, a microchamber is formed between the first chamber portion and the second chamber portion in which a semiconductor wafer can be received, and when the second chamber portion is in the open position relative to the first chamber portion, the semiconductor wafer can be taken out or placed in;

at least one of the first chamber part and the second chamber part comprises a main body part and an embedded part, wherein a surface of the main body part facing the micro chamber is provided with a embedded groove, and the embedded part is embedded into the embedded groove to form a whole with the main body part.

2. The semiconductor processing apparatus according to claim 1, wherein the fitting groove has an annular shape, the fitting portion has an annular shape matching the fitting groove, and when the semiconductor wafer is accommodated in the micro chamber, an edge portion of the semiconductor wafer corresponds to a surface of the fitting portion, and a middle portion of the semiconductor wafer corresponds to a surface of the main body portion; alternatively, the first and second liquid crystal display panels may be,

the embedding groove is circular, the embedding part is circular matched with the embedding groove, and when the semiconductor wafer is accommodated in the micro-chamber, the middle part and the edge part of the semiconductor wafer correspond to the surface of the embedding part.

3. The semiconductor processing apparatus of claim 1, wherein a coefficient of thermal expansion of the main body portion in a range of 10-30 degrees is smaller than a coefficient of thermal expansion of the embedded portion in a range of 10-30 degrees,

the embedding part is made of PTFE (polytetrafluoroethylene), the main body part is made of PVC (polyvinyl chloride), the low-temperature embedding part is placed in the embedding groove of the main body part, and the embedding part can expand to fully support the embedding groove in a normal temperature state.

4. The semiconductor processing apparatus according to any one of claims 1 to 3,

the first chamber part is provided with a first channel, the second chamber part is provided with a second channel, when the second chamber part is positioned at the closed position relative to the first chamber part and the micro chamber contains a semiconductor wafer, the first channel and the second channel are communicated and form an edge micro-processing space together with the edge of the semiconductor wafer, the outer edge of the semiconductor wafer contained in the micro chamber extends into the edge micro-processing space which is communicated with the outside through an edge processing through hole, and fluid enters or flows out of the edge micro-processing space through the edge processing through hole,

the first channel is formed on the embedded portion of the first chamber portion, and the second channel is formed on the embedded portion of the second chamber portion.

5. The semiconductor processing apparatus of claim 4,

the first chamber part is provided with a sealing joint part positioned outside the first channel, the second chamber part is provided with a joint groove corresponding to the sealing joint part, the sealing joint part is formed on the embedded part of the first chamber part, the joint groove is formed on the embedded part of the second chamber part,

a first edge surface, a second edge surface, and an outer bevel edge face of the outer edge of the semiconductor wafer exposed to the edge micro-processing volume, one or more of the edge processing through holes serving as a fluid inlet, one or more of the edge processing through holes serving as a fluid outlet,

the edge micro-processing space is annular or arc-shaped, the outer edge of the semiconductor wafer extends into the edge micro-processing space, and the edge micro-processing space is a closed space and is communicated with the outside through an edge processing through hole;

the top surface of the inner side wall part of the first channel abuts against the first edge surface of the semiconductor wafer close to the first chamber part, and the top surface of the inner side wall part of the second channel abuts against the second edge surface of the semiconductor wafer close to the second chamber part.

6. The semiconductor processing apparatus according to claim 5, wherein the first chamber further has a first recess formed on an inner wall surface of the first chamber facing the micro chamber, the first recess is located inside the first channel, the second chamber further has a second recess formed on an inner wall surface of the second chamber facing the micro chamber, the second recess is located inside the second channel, a partial region of the second edge surface of the semiconductor wafer covers a top of the second recess to form a second inner micro space, and a partial region of the first edge surface of the semiconductor wafer covers a top of the first recess to form a first inner micro space when the second chamber is located at the closed position with respect to the first chamber and the semiconductor wafer is accommodated in the micro chamber, the first inner micro-processing space and the second inner micro-processing space are positioned at the inner side of the edge micro-processing space, the first chamber part is provided with a first inner side processing through hole communicated with the first sunken part, and the second chamber part is provided with a second inner side processing through hole communicated with the second sunken part.

7. The semiconductor processing apparatus of claim 6, wherein the first and second recesses are annular or arcuate, and wherein a liquid or gas is introduced into the first and second recesses to prevent inward penetration of the liquid in the edge micro-processing volume while etching the edge of the semiconductor wafer using the edge micro-processing volume.

8. The semiconductor processing apparatus of claim 5, wherein the sealing land includes an inner edge surface on an inner side, and a distal end of the sealing land extends into the engaging recess when the second chamber part is in the closed position relative to the first chamber part, and a distal end portion of the inner edge surface thereof is in sealing engagement with a groove wall of the engaging recess, and an upper end portion of the inner edge surface thereof forms an outer side surface of the peripheral micro-processing space.

9. The semiconductor processing apparatus of claim 8, wherein a sealing surface of an end portion of the inner peripheral surface of the sealing land and a groove wall of the land groove is located below the outer edge micro processing space and is perpendicular to an extending direction of the semiconductor wafer.

10. The semiconductor processing apparatus of claim 8, wherein the inner edge surface of the sealing joint effects centering of the semiconductor wafer during closing of the second chamber portion relative to the first chamber portion, and wherein the inner edge surface of the sealing joint is corrected to a desired center by pressing against the semiconductor wafer if the center of the semiconductor wafer when placed deviates from the desired center.

11. The semiconductor processing apparatus of claim 5, wherein the first chamber portion includes a positioning groove and the second chamber portion includes a positioning post, the positioning post and the positioning groove cooperate to properly position the first chamber portion and the second chamber portion when closed, the sealing joint includes an inner edge surface at an inner upper end and a projection at an inner end, the end of the sealing joint extends into the engagement groove when the second chamber portion is in the closed position relative to the first chamber portion, the projection sealingly engages a wall of the engagement groove, the inner edge surface forms an outer side of the peripheral micro-processing space, the inner edge surface is spaced a distance from an outer edge of the semiconductor wafer, and a sealing surface formed by the projection of the sealing joint and the wall of the engagement groove is located below the peripheral micro-processing space, and the sealing surface is perpendicular to the extension direction of the semiconductor wafer, the bump of the sealing joint effects a centering of the semiconductor wafer during the closing of the second chamber part relative to the first chamber part, and if the center of the semiconductor wafer when placed deviates from the desired center, the bump of the sealing joint is corrected to the desired center by pressing against the semiconductor wafer so that its center is aligned to the desired center.

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