CN116230577A - Semiconductor processing apparatus - Google Patents

Abstract

The present invention provides a semiconductor processing apparatus, comprising: a first chamber portion; a second chamber portion movable between an open position and a closed position with respect to the first chamber portion, wherein a micro chamber is formed between the first chamber portion and the second chamber portion when the second chamber portion is located at the closed position with respect to the first chamber portion, wherein a semiconductor wafer can be accommodated in the micro chamber, and wherein the semiconductor wafer can be taken out or put in when the second chamber portion is located at the open position with respect to the first chamber portion; at least one of the first chamber portion and the second chamber portion includes a main body portion, on a surface of which faces the micro chamber, a fitting groove is formed, and an insertion portion, which is inserted into the fitting groove to form one body with the main body portion. In this way, the deformation error of the embedded part due to the difference of the processing temperature and the working temperature can be greatly reduced, thereby improving the precision of the semiconductor processing device.

Description

Semiconductor processing apparatus

[ field of technology ]

The present invention relates to the field of processing semiconductor wafers, and more particularly to semiconductor processing apparatus.

[ background Art ]

The precise edge etching process of semiconductor wafers is a challenging process. It is required to achieve accurate corrosion of the wafer edge micron level without damaging or contaminating the film of the remaining portion. In epitaxial wafer processing and advanced integrated circuit processing, wafer edge etching is an important step for ensuring film formation quality and improving chip yield.

Please refer to fig. 1a to 1d, wherein: FIG. 1a shows a schematic structure of a semiconductor wafer 400, and FIG. 1b is a cross-sectional E-E view of FIG. 1 a; FIG. 1c is a partial cross-sectional view of the outer edge of a semiconductor wafer prior to outer edge processing; fig. 1d is a cross-sectional view of the outer edge portion of the semiconductor wafer after outer edge processing. As shown in fig. 1a to 1d, the semiconductor wafer 400 includes a substrate layer 401 and a thin film layer 402 formed on a first edge surface and a second edge surface of the substrate layer 401. After the selective etching treatment for the first edge surface 404, the second wafer surface 406 and the outer end bevel 408 of the outer edge portion of the semiconductor wafer 400, the thin film layer 402 of the outer edge portion of the semiconductor wafer 400 is removed, and the first edge surface and the second edge surface of the base material layer 401 are exposed.

Existing wafer edge etching equipment can be divided into two main types, namely dry method and wet method. The dry method is mainly divided into a plasma method and a polishing method. The plasma edge etching method has high equipment cost and complex method, and is mainly applied to the integrated circuit chip manufacturing process. The polishing method is to remove the contacted film by rotating the wafer and utilizing physical friction and chemical gas-liquid combination. The polishing method has lower equipment cost, but is easy to cause the damage and pollution of the reserved film part, and is mainly applied to the wafer manufacturing process below 200 mm. The wet method mainly comprises a film pasting method and a vacuum adsorption method. The film pasting method adopts pure and anti-corrosion plastic films such as PTFE, PE and the like to protect the part of the film to be reserved, and then the film is wholly exposed in a chemical corrosive gas environment or soaked in chemical corrosive liquid to corrode the exposed part. The film pasting method has a plurality of process steps and needs to be completed by using various equipment, wherein the equipment comprises film pasting, wet etching, cleaning, film removing and the like. The vacuum adsorption method uses a vacuum suction head to suck a wafer, the vacuum suction head has the function of sucking the wafer to protect the part of the film to be kept in the vacuum suction head, exposing the part of the film to be removed outside the vacuum suction head, and then soaking the vacuum suction head and the wafer together in a chemical etching solution to etch away the part of the film exposed outside the vacuum suction head. The vacuum adsorption method has simple process steps and lower equipment cost, but is easy to cause the damage and pollution of the reserved film part, and is mainly applied to the wafer manufacturing process below 200 mm.

The chinese patent application No. 201821459515.8 entitled "a semiconductor processing apparatus" discloses an edge processing scheme for semiconductor wafers. However, the upper chamber portion and the lower chamber portion have a difference between the manufacturing temperature and the use temperature, which may cause a small error between the dimension at the time of manufacturing and the dimension at the time of using, and affect the wafer edge processing accuracy.

In view of this, there is a need for an improved semiconductor processing apparatus that reduces the effects of thermal expansion and contraction.

[ invention ]

The invention aims to provide a semiconductor processing device, which can reduce the influence caused by thermal expansion and cold contraction.

To achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor processing apparatus comprising: a first chamber portion; a second chamber portion movable between an open position and a closed position with respect to the first chamber portion, wherein a micro chamber is formed between the first chamber portion and the second chamber portion when the second chamber portion is located at the closed position with respect to the first chamber portion, wherein a semiconductor wafer can be accommodated in the micro chamber, and wherein the semiconductor wafer can be taken out or put in when the second chamber portion is located at the open position with respect to the first chamber portion; at least one of the first chamber portion and the second chamber portion includes a main body portion, on a surface of which faces the micro chamber, a fitting groove is formed, and an insertion portion, which is inserted into the fitting groove to form one body with the main body portion.

Compared with the prior art, at least one of the first chamber part and the second chamber part consists of the main body part and the embedded part, the surface of the main body part facing the micro chamber is provided with the embedded groove, the embedded part is embedded into the embedded groove to form a whole with the main body part, the thermal expansion coefficient of the main body part at normal temperature is smaller than that of the embedded part at normal temperature, the volume of the embedded part is reduced, the total expansion or reduction degree caused by temperature change is also reduced, and meanwhile, the expansion range of the embedded part can be controlled through the size selection of the embedded groove of the main body part and the size selection of the embedded part, so that the influence of thermal expansion and cold contraction on the embedded part can be controlled.

[ description of the drawings ]

The invention will be more readily understood by reference to the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:

FIG. 1a is a schematic diagram of a semiconductor wafer;

FIG. 1b is a cross-sectional E-E view of FIG. 1 a;

fig. 1c is a cross-sectional view of an outer edge portion of a semiconductor wafer prior to outer edge processing;

FIG. 1d is a cross-sectional view of the outer edge portion of a semiconductor wafer after outer edge processing;

FIG. 2a is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a first embodiment;

FIG. 2b is an enlarged schematic view of circle A in FIG. 2 a;

FIG. 3a is a bottom view of a first chamber portion of the semiconductor processing apparatus of FIG. 2 a;

FIG. 3b is a top view of a second chamber portion of the semiconductor processing apparatus of FIG. 2 a;

FIG. 4 is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a second embodiment;

FIG. 5 is an enlarged schematic view of circle B in FIG. 4;

fig. 6a is a bottom view of a first chamber portion of the semiconductor processing apparatus of fig. 4;

fig. 6b is a top view of a second chamber portion of the semiconductor processing apparatus of fig. 4;

FIG. 7a is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a third embodiment;

FIG. 7b is an enlarged schematic view of circle D in FIG. 7 a;

fig. 8 is an exploded perspective view of the lower chamber portion of fig. 7 a.

[ detailed description ] of the invention

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. The terms "plurality" and "a plurality" as used herein mean two or more. "and/or" in the present invention means "and" or ".

First embodiment:

referring to fig. 2a to 3b, a schematic structural diagram of a semiconductor processing apparatus 100 according to a first embodiment of the present invention is shown, wherein: FIG. 2a is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a first embodiment; FIG. 2b is an enlarged schematic view of circle A in FIG. 2 a; FIG. 3a is a bottom view of a first chamber portion of the semiconductor processing apparatus of FIG. 2 a; fig. 3b is a top view of the second chamber portion of the semiconductor processing apparatus of fig. 2 a.

Referring to fig. 2a to 3b, the semiconductor processing apparatus 100 includes a first chamber portion 110 and a second chamber portion 120. The first chamber portion 110 includes a first chamber plate 119 and a flange 118 extending from a periphery of the first chamber plate 119. The second chamber portion 120 includes a second chamber plate 129 and a flange 128 extending around the periphery of the second chamber plate 129.

The first chamber portion 110 is movable relative to the second chamber portion 120 between an open position and a closed position. It should be noted that the movement of the first chamber portion 110 and the second chamber portion 120 are opposite, the first chamber portion 110 may be fixed so that the second chamber portion 120 is moved relatively, the second chamber portion 120 may be fixed so that the first chamber portion 110 is moved relatively, and both the first chamber portion 110 and the second chamber portion 120 may be moved at the same time, as long as the first chamber portion 110 and the second chamber portion 120 are able to move relatively. With the first chamber portion 110 in a closed position relative to the second chamber portion 120, the flange 118 cooperates with the flange 128 to form a micro chamber 140 between the first chamber plate 118 and the second chamber plate 128, and a semiconductor wafer 400 to be processed can be accommodated within the micro chamber 140 awaiting subsequent processing. The flange 118 is separated from the flange 128 when the first chamber portion 110 is in an open position relative to the second chamber portion 120, and the semiconductor wafer 400 to be processed can be removed from or placed into the micro-chamber 140.

An annular first channel 116 is formed on the side of the first chamber portion 110 facing the micro chamber 140, and a second channel 126 is formed on the side of the second chamber portion 120 facing the micro chamber 140. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 is received in the micro-chamber, the first channel 116 and the second channel 126 together form an edge micro-processing space 130, and an outer edge of the semiconductor wafer 400 received in the micro-chamber protrudes into the edge micro-processing space 130.

As shown in fig. 2a to 3b, in this embodiment, the first channel 116 and the second channel 126 are annular channels. When the second chamber portion 120 is located at the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 is accommodated in the micro chamber, the wall surface 117 of the first chamber portion 110 located inside the first channel 116 abuts against the first edge surface of the semiconductor wafer 400 to be processed, the wall surface 127 of the second chamber portion 120 located inside the second channel 126 abuts against the second edge surface of the semiconductor wafer 400 to be processed, the first channel 116 and the second channel 126 are surrounded to form a closed, annular outer edge micro processing space 130, and the outer edge portion of the semiconductor wafer 400 to be processed is accommodated in the outer edge micro processing space 130.

Therefore, in the present embodiment, the edge micro-process space 130 can implement selective processing of the entire outer edge portion of the semiconductor wafer 400 to be processed.

Of course, the first channel 116 and the second channel 126 may be configured as arc-shaped channels having an arc less than 360 degrees. At this time, the first channel 116 and the second channel 126 form the closed outer edge micro-processing space 130 having an arc shape with an arc less than 360 degrees. Accordingly, a partial arc of the outer edge of the semiconductor wafer 400 to be processed is accommodated in the edge micro-processing space 130. Thus, the edge micro-processing space 130 only enables selective processing of a portion of the arc segment of the outer edge of the semiconductor wafer 400 to be processed at this time.

The first chamber part 110 has at least two edge processing through holes 112 penetrating the first chamber part 110 from the outside to communicate with the edge micro-processing space 130, wherein: at least one edge-treated through-hole serves as a fluid inlet and at least one edge-treated through-hole serves as a fluid outlet. In this embodiment, 4 edge processing through holes are provided. Of course, an edge processing through hole communicating with the edge micro-processing space 130 may be provided in the second chamber 120.

In use, a processing fluid can enter the edge micro-processing space 130 through one edge processing through-hole 112, the fluid entering the edge micro-processing space 130 can flow in the edge micro-processing space 130, at this time, the processing fluid can contact and process the outer edge portion of the semiconductor wafer 400 to be processed contained in the edge micro-processing space 130, and the fluid processed by the semiconductor wafer 400 to be processed can flow out through another edge processing through-hole 112 or flow out through an edge processing through-hole provided on the second chamber portion 120 and communicating with the edge micro-processing space 130. During processing, processing fluid can be introduced into the edge micro-processing space 130 through an edge processing through-hole 112 continuously or at intervals, and the fluid in the edge micro-processing space 130 can flow during processing, so that the processing speed can be increased.

Of course, the treatment may be etching treatment of the outer edge of the semiconductor wafer 400 to remove the thin film layer of the outer edge portion of the semiconductor wafer 400, selective cleaning of only the outer edge of the semiconductor wafer 400, or the like.

Taking as an example the etching removal of the thin film layer at the outer edge portion of the semiconductor wafer 400 to be processed. Referring to fig. 1a to 1d and 2a to 3b in combination, when it is required to etch away the thin film layers of the first and second sides of the outer edge of the semiconductor wafer 400 to be processed. Only the corresponding processing fluid having an etching effect on the thin film layer is introduced into the edge micro-processing space 130 through one edge processing through hole 112, and the processing fluid flows in the edge micro-processing space 130 and directly contacts the outer edge portion of the semiconductor wafer 400 to be processed. The processing fluid flows along the edge of the semiconductor wafer 400 to be processed, and chemically or physically reacts with the wafer surface of the wafer to be processed which is accommodated in the edge micro-processing space, so that the first edge surface, the second edge surface and the thin film layer 402 on the bevel edge of the semiconductor wafer 400 to be processed are continuously etched away. After the process is completed, as shown in fig. 1d, the thin film layer 402 of the portion of the outer edge of the semiconductor wafer 400 accommodated in the edge micro-process space 130 is etched away, and the first edge surface, the second edge surface and the outer end bevel edge of the substrate layer 401 of the outer edge of the semiconductor wafer 400 are exposed. The fluid processed by the semiconductor wafer 400 is flowed out through other edge processing vias.

It can be seen that, based on the edge micro-processing space 130, the semiconductor processing apparatus 100 in this embodiment consumes only a small amount of processing fluid to achieve selective etching treatment on the outer edge of one piece of the semiconductor wafer 400 to be processed, which greatly reduces the processing cost and the amount of production waste liquid. In addition, the semiconductor processing apparatus 100 in the present embodiment has the remarkable advantages of simple structure, convenient use, and low requirement on the operation skills of operators, as compared with the dry process apparatus in the related art.

It can be seen that the semiconductor processing apparatus 100 provided in this embodiment can implement selective processing on the outer edge of the semiconductor wafer 400 to be processed. In addition, by controlling the flow rate of the processing fluid within the semiconductor wafer 400 to be processed, the amount of processing fluid can be saved while ensuring the processing effect. With continued reference to fig. 2 a-2 b, in the present embodiment, the first chamber portion 110 further has a first recess 115 formed on an inner wall surface of the first chamber portion 110 facing the micro chamber, the first recess being located inside the first channel 116, and the second chamber portion 120 further has a second recess 125 formed on an inner wall surface of the second chamber portion 120 facing the micro chamber, the second recess being located inside the second channel 126. The first recess 115 and the second recess 125 are also annular. When the second chamber portion 120 is located at the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 to be processed is accommodated in the micro-chamber, a partial area of the second edge surface of the semiconductor wafer 400 to be processed covers the top of the second recess 125 to form a second inner micro-space, a partial area of the first edge surface of the semiconductor wafer 400 to be processed covers the top of the first recess 115 to form a first inner micro-space, and the first inner micro-space and the second inner micro-space are located inside the edge micro-processing space 130.

Correspondingly, the first chamber portion 110 has a first inner processing through hole communicating with the first recess portion 115, and the second chamber portion 120 has a second inner processing through hole communicating with the second recess portion 125. When the edge of the semiconductor wafer 400 is etched using the edge micro-process space 130, a liquid or gas, such as water or nitrogen, may be introduced into the first recess 115 and the second recess 125, that is, into the first inner micro-space and the second inner micro-space, to prevent the liquid in the edge micro-process space 130 from penetrating inward.

Likewise, the first recess 115 and the second recess 125 may be arc-shaped.

With continued reference to fig. 2a to 2b, in the present embodiment, when the second chamber portion 120 and the first chamber portion 110 are in the closed position, the micro chamber 140 is further formed in the middle thereof, the second chamber portion 120 has a middle processing through hole 123 communicating with the micro chamber 140, and the first chamber portion 110 has a middle processing through hole 113 communicating with the micro chamber 140.

Referring to fig. 2b, the first chamber portion 110 has a sealing engagement portion 210 thereon located outside the first channel 116, and the second chamber portion 120 has an engagement groove 122 thereon corresponding to the sealing engagement portion 210. The sealing joint 210 includes a guide surface 211 at the distal end and an inner side surface 212 at the inner side. When the second chamber portion 120 is located at the closed position with respect to the first chamber portion 110, the tip end of the seal engaging portion 210 protrudes into the engaging groove 122, the tip end portion of the inner side surface 212 thereof is in seal engagement with the groove wall of the engaging groove 122, and the upper end portion of the inner side surface 212 thereof forms the outer side surface of the outer-edge micro-processing space 130. Further, the sealing surface of the distal end portion of the inner side surface 212 of the seal joint 210 and the groove wall of the joint groove 122 is located below the outer edge micro processing space 130 and perpendicular to the extending direction of the semiconductor wafer 400, and this arrangement makes it possible to make the wall surface 117 of the first chamber portion 110 located inside the first groove 116 abut against the first edge surface of the semiconductor wafer 400 to be processed more closely, and the wall surface 127 of the second chamber portion 120 located inside the second groove 126 abuts against the second edge surface of the semiconductor wafer 400 to be processed more closely, avoiding the penetration of the etching liquid inward.

In the embodiment of fig. 2b, the inner side surface 212 of the sealing joint 210 may effect centering of the semiconductor wafer 400 during closing of the second chamber part 120 with respect to the first chamber part 110, i.e. if the center of the semiconductor wafer 400 when placed deviates from the desired center, the inner edge surface 212 of the sealing joint 210 may also be corrected to the desired center by pressing against the semiconductor wafer 140. In one example, when edge processing is performed, it is required that the center deviation of the semiconductor wafer 400 does not exceed 0.2mm, and in this way, the center deviation can be adjusted to within 0.1 mm. The guide surface 211 may guide the sealing engagement portion 210 into the engagement groove 122 when the first and second chamber portions 110 and 120 are closed. The sealing engagement portion 210 may be caught in the engagement groove 122.

Referring to fig. 2a, the first chamber portion 110 includes a positioning groove 114 and the second chamber portion 120 includes a positioning post 124, so that the first chamber portion 110 and the second chamber portion 120 can be properly positioned when closed. During the closing process of the first chamber portion 110 and the second chamber portion 120, the positioning post 124 is first engaged with the positioning groove 114 to achieve the initial positioning, and then the end of the sealing engagement portion 210 protrudes into the engagement groove 122.

In one embodiment, the silicon oxide wafer edge etching process performed using the semiconductor processing apparatus 100 of the present invention may include a closed chamber, an HF acid etch, a DIW rinse, an IPA rinse, a nitrogen gas dry, and an open chamber. The specific processes in which the HF acid etch, DIW (deionized water) rinse, and IPA (isopropyl alcohol) rinse are all operated with reference to the above-described procedure. In particular, during the HF acid etching, a liquid or gas, such as water or nitrogen, may be introduced into the first recess 115 and the second recess 125 to prevent the liquid in the edge micro-process space 130 from penetrating inward.

Second embodiment

Referring to fig. 4 to 6b, a schematic structural diagram of a semiconductor processing apparatus 200 according to a second embodiment of the present invention is shown, wherein: FIG. 4 is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a first embodiment; FIG. 5 is an enlarged schematic view of circle B in FIG. 4; fig. 6a is a bottom view of a first chamber portion of the semiconductor processing apparatus of fig. 4; fig. 6b is a top view of a second chamber portion of the semiconductor processing apparatus of fig. 4.

The semiconductor processing apparatus 200 in the second embodiment is largely identical in structure to the semiconductor processing apparatus 100 in the first embodiment, and therefore identical parts thereof are denoted by the same reference numerals, and the difference therebetween is mainly that: the seal joint 310 of the semiconductor processing apparatus 200 and the seal joint 210 of the semiconductor processing apparatus 100 are somewhat different in structure.

As shown in fig. 5, the first chamber portion 110 has the seal engaging portion 310 located outside the first channel 116, and the second chamber portion 120 has the engaging groove 122 corresponding to the seal engaging portion 210.

The seal joint 310 includes a guide surface 311 at the distal end, an inner side surface 312 at the inner side upper end, and a projection 313 at the inner side distal end. When the second chamber portion 120 is located at the closed position relative to the first chamber portion 110, the tip of the seal engaging portion 310 protrudes into the engaging groove 122, the projection 313 thereof is in sealing engagement with the groove wall of the engaging groove 122, and the inner side surface 312 thereof forms the outer side surface of the outer-edge micro-processing space 130. The inner side surface 312 is spaced a distance from the outer edge of the semiconductor wafer 400.

The sealing surface formed by the protrusion 313 of the sealing joint 310 and the groove wall of the joint groove 122 is located below the outer edge micro-processing space 130 and perpendicular to the extending direction of the semiconductor wafer 400, and this arrangement can make the wall surface 117 of the first chamber portion 110 located inside the first groove 116 abut against the first side surface of the semiconductor wafer 400 to be processed more tightly, and the wall surface 127 of the second chamber portion 120 located inside the second groove 126 abuts against the second side surface of the semiconductor wafer 400 to be processed more tightly, so that the etching liquid is prevented from penetrating inward.

In the embodiment of fig. 2b, the bump 313 of the sealing joint 310 may achieve a centering of the semiconductor wafer 140 during closing of the second chamber part 120 with respect to the first chamber part 110, i.e. if the center of the semiconductor wafer 140 is offset from the desired center when placed, the bump 313 of the sealing joint 310 may also be corrected to the desired center by pressing against the semiconductor wafer 140.

There is still a distance between the inner side surface 312 and the outer edge of the semiconductor wafer 400. Such that the semiconductor wafer 400 may not be easily pinched by the seal joint 310 when the second chamber portion 120 is disengaged from the first chamber portion 110.

In another embodiment, the bump 313 may not be used to center the semiconductor wafer 400, i.e., the bump 313 does not contact the edge of the semiconductor wafer 400. While the centering of the semiconductor wafer 400 may be achieved with the wall edges of the first channel 116.

Third embodiment

FIG. 7a is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a third embodiment; FIG. 7b is an enlarged schematic view of circle D in FIG. 7 a; fig. 8 is an exploded perspective view of the lower chamber portion of fig. 7 a.

As shown in fig. 7a and 7b, the semiconductor processing apparatus includes a first chamber portion 110 and a second chamber portion 120. When the second chamber portion 120 is located at the closed position with respect to the first chamber portion 110, a micro chamber is formed between the first chamber portion 110 and the second chamber portion 120, the semiconductor wafer 400 can be accommodated in the micro chamber, and when the second chamber portion 120 is located at the open position with respect to the first chamber portion 110, the semiconductor wafer 400 can be taken out or put in.

Similar to the first and second embodiments, the first channel formed on the first chamber portion 110 and the second channel formed on the second chamber portion 120 communicate and may form an edge micro-process space with an edge of the semiconductor wafer, with which the semiconductor wafer 400 may be edge-processed. The related structure and description of the edge processing of the semiconductor wafer 400 using the edge micro-processing space will not be described in detail in this embodiment.

The difference compared to the first and second embodiments is that the first chamber portion 110 in the present embodiment includes a first main body portion 1105 and a first embedding portion 1104. A first fitting groove 1106 is formed on a surface of the first main body portion 1105 facing the micro chamber, and the first fitting portion 1104 is fitted into the first fitting groove 1106 to be integral with the first main body portion 1105. As shown in fig. 8, the second chamber 120 includes a second body 1205 and a second fitting portion 1204, and a second fitting groove 1206 is formed on a surface of the second body 1205 facing the micro chamber, and the second fitting portion 1204 is fitted into the second fitting groove 1206 to be integral with the second body 1205.

As shown in fig. 7a and 8, the fitting grooves 1106 and 1206 are each in a ring shape, the fitting portions 1104 and 1204 are respectively in a ring shape matching with the fitting grooves 1106 and 1206, when the semiconductor wafer 400 is accommodated in the micro chamber, edge portions of the semiconductor wafer 400 correspond to surfaces of the fitting portions 1104 and 1204, the edge portions of the semiconductor wafer 400 are located between the fitting portions 1104 and 1204, and middle portions of the semiconductor wafer 400 correspond to the main body portions 1105 and 1205.

In one embodiment, the body portion has a coefficient of thermal expansion that is less than the coefficient of thermal expansion of the insert portion at ambient temperature, such as 10-30 degrees. More specifically, the embedded portion may be made of PTFE (polytetrafluoroethylene), and the main body portion may be made of PVC (polyvinyl chloride). In the manufacturing process, the low-temperature embedded part is placed in the embedded groove of the main body part, and when the embedded part reaches the normal temperature state, the embedded part expands to fill the embedded groove, so that the embedded part and the main body part can be assembled. After that, the first chamber portion or the second chamber portion may be made of a material integrated by the embedded portion and the main body portion.

Since the temperatures at which the first chamber portion and the second chamber portion are made and the temperatures at which the first chamber portion and the second chamber portion are used may differ, for example, by 3 degrees to 10 degrees. Since the coefficient of thermal expansion of the PTFE material is large at ordinary temperature, the first chamber portion and the second chamber portion made of the PTFE material have large variations in dimensions due to the temperature difference between the time of manufacture and the time of use, which causes a problem of excessive errors. For example, in the edge etching process, the diameter of the etched edge line of the semiconductor wafer may have a certain error due to thermal expansion and contraction of the first chamber portion and the second chamber portion, which may not be acceptable in some cases. In the present invention, the embedded portion is made of only PTFE material, and the main body portion is made of PVC material having a smaller thermal expansion coefficient at normal temperature than the PTFE material, and the embedded portion is held by the main body portion while the embedded portion is reduced in volume, so that the thermal expansion of the embedded portion is suppressed by the main body portion, and the influence of the temperature difference between the first chamber portion and the second chamber portion in the production and use can be reduced. In addition, the PVC material is cheaper than the PTFE material, and the mode of the invention can reduce the manufacturing cost.

The first chamber portion and/or the second chamber portion in the first embodiment and the second embodiment may be formed by combining the insert portion and the main body portion, in which case the first channel may be formed on the insert portion of the first chamber portion, the second channel may be formed on the insert portion of the second chamber portion, the seal engaging portion may be formed on the insert portion of the first chamber portion, and the engaging groove may be formed on the insert portion of the second chamber portion.

In another embodiment, only one of the first chamber portion and the second chamber portion may be formed by combining the insert portion and the main body portion.

In another alternative embodiment, the fitting groove may be circular, and the fitting portion may be circular to match the fitting groove, and when the semiconductor wafer is accommodated in the micro chamber, both a middle portion and an edge portion of the semiconductor wafer correspond to a surface of the fitting portion.

In another alternative embodiment, the semiconductor processing apparatus including the chamber portion formed by combining the insert portion and the body portion may be used not only for edge processing of the semiconductor wafer but also for other processing of the semiconductor wafer, such as cleaning, drying, etching of the entire surface, and the like.

The foregoing description has fully disclosed specific embodiments of this invention. It should be noted that any modifications to the specific embodiments of the invention may be made by those skilled in the art without departing from the scope of the invention as defined in the appended claims. Accordingly, the scope of the claims of the present invention is not limited to the specific embodiments.

Claims (14)

1. A semiconductor processing apparatus, comprising:

a first chamber portion;

a second chamber portion movable between an open position and a closed position with respect to the first chamber portion, wherein a micro chamber is formed between the first chamber portion and the second chamber portion when the second chamber portion is located at the closed position with respect to the first chamber portion, wherein a semiconductor wafer can be accommodated in the micro chamber, and wherein the semiconductor wafer can be taken out or put in when the second chamber portion is located at the open position with respect to the first chamber portion;

at least one of the first chamber portion and the second chamber portion includes a main body portion, on a surface of which faces the micro chamber, a fitting groove is formed, and an insertion portion, which is inserted into the fitting groove to form one body with the main body portion.

2. The semiconductor processing apparatus according to claim 1, wherein the fitting groove is annular, the fitting portion is annular matching the fitting groove, an edge portion of the semiconductor wafer corresponds to a surface of the fitting portion, and a middle portion of the semiconductor wafer corresponds to a surface of the main body portion when the semiconductor wafer is accommodated in the microcavity; or alternatively, the process may be performed,

the embedded groove is round, the embedded part is round matched with the embedded groove, and when the semiconductor wafer is accommodated in the micro-cavity, the middle part and the edge part of the semiconductor wafer correspond to the surface of the embedded part.

3. The semiconductor processing apparatus according to claim 1, wherein a coefficient of thermal expansion of the body portion in a range of 10-30 degrees is smaller than a coefficient of thermal expansion of the embedded portion in a range of 10-30 degrees,

the embedded part is made of PTFE, the main body part is made of PVC, the embedded part with low temperature is placed in the embedded groove of the main body part, and the embedded part expands to fill the embedded groove when the embedded part is at normal temperature.

4. A semiconductor processing apparatus according to any one of claims 1 to 3, wherein,

the first chamber part is provided with a first channel, the second chamber part is provided with a second channel, when the second chamber part is positioned at the closed position relative to the first chamber part and the micro chamber is internally provided with a semiconductor wafer, the first channel and the second channel are communicated and form an edge micro-processing space together with the edge of the semiconductor wafer, the outer edge of the semiconductor wafer accommodated in the micro chamber stretches into the edge micro-processing space, the edge micro-processing space is communicated with the outside through an edge processing through hole, fluid enters or flows out of the edge micro-processing space through the edge processing through hole,

the first channel is formed on the embedded part of the first chamber part, and the second channel is formed on the embedded part of the second chamber part.

5. The semiconductor processing apparatus of claim 4, wherein,

the first chamber part is provided with a sealing joint part positioned outside the first channel, the second chamber part is provided with a joint groove corresponding to the sealing joint part, the sealing joint part is formed on the embedded part of the first chamber part, the joint groove is formed on the embedded part of the second chamber part,

the first edge surface, the second edge surface, and the outer end bevel surface of the outer edge of the semiconductor wafer are exposed to the edge micro-processing space, one or more of the edge processing through holes serves as a fluid inlet, one or more of the edge processing through holes serves as a fluid outlet,

the edge micro-processing space is annular or arc-shaped, the outer edge of the semiconductor wafer stretches into the edge micro-processing space, and the edge micro-processing space is a closed space and is communicated with the outside through an edge processing through hole;

the inner sidewall portion top surface of the first channel abuts against a first edge surface of the semiconductor wafer adjacent the first chamber portion, and the inner sidewall portion top surface of the second channel abuts against a second edge surface of the semiconductor wafer adjacent the second chamber portion.

6. The semiconductor processing apparatus of claim 5, wherein the first chamber portion further has a first recess formed in an inner wall surface of the first chamber portion facing the micro chamber, the first recess being located inside the first channel, the second chamber portion further has a second recess formed in an inner wall surface of the second chamber portion facing the micro chamber, the second recess being located inside the second channel, a partial region of a second edge surface of the semiconductor wafer covering a top of the second recess to form a second inner micro-space, a partial region of a first edge surface of the semiconductor wafer covering a top of the first recess to form a first inner micro-space, the first inner micro-space and the second inner micro-space being located inside the edge micro-processing space, the first chamber portion having a first recess surface in communication with a second through-hole communicating with the second chamber portion when the second chamber portion is located in the closed position with respect to the first chamber portion.

7. The semiconductor processing apparatus according to claim 6, wherein the first recess and the second recess are annular or arc-shaped, and liquid or gas is introduced into the first recess and the second recess to prevent the liquid in the edge micro-processing space from penetrating inward when the edge of the semiconductor wafer is etched by the edge micro-processing space.

8. The semiconductor processing apparatus according to claim 5, wherein the seal engaging portion includes an inner edge surface located on an inner side, a tip end of the seal engaging portion extending into the engaging recess when the second chamber portion is located at the closed position with respect to the first chamber portion, a tip end portion of the inner edge surface thereof being in sealing engagement with a wall of the engaging recess, and an upper end portion of the inner edge surface thereof forming an outer side face of the outer edge micro-processing space.

9. The semiconductor processing apparatus according to claim 8, wherein a sealing surface of a distal end portion of an inner edge surface of the seal joint and a groove wall of the joint groove is located below the outer edge micro-processing space, and the sealing surface is perpendicular to an extending direction of the semiconductor wafer.

10. The semiconductor processing apparatus according to claim 8, wherein the inner edge surface of the sealing joint achieves centering of the semiconductor wafer during closing of the second chamber portion with respect to the first chamber portion, and if the center of the semiconductor wafer when placed deviates from a desired center, the inner edge surface of the sealing joint is corrected to the desired center by pressing against the semiconductor wafer so that the center thereof is centered.

11. The semiconductor processing apparatus of claim 5, wherein the first chamber portion includes a detent and the second chamber portion includes a detent, the detent and the detent cooperating to enable the first chamber portion and the second chamber portion to be properly positioned when closed.

12. The semiconductor processing apparatus according to claim 5, wherein the sealing engagement portion includes an inner edge surface at an inner upper end and a projection at an inner end, the end of the sealing engagement portion extending into the engagement recess when the second chamber portion is in the closed position with respect to the first chamber portion, the projection being in sealing engagement with a wall of the engagement recess, the inner edge surface forming an outer side of the outer edge micro-processing space, the inner edge surface being spaced apart from an outer edge of the semiconductor wafer.

13. The semiconductor processing apparatus according to claim 12, wherein a sealing surface formed by the projection of the seal joint and the wall of the joint groove is located below the outer edge micro-processing space, and the sealing surface is perpendicular to the extending direction of the semiconductor wafer.

14. The semiconductor processing apparatus of claim 12, wherein the bump of the sealing joint achieves centering of the semiconductor wafer during closing of the second chamber portion relative to the first chamber portion, and if the center of the semiconductor wafer when placed deviates from a desired center, the bump of the sealing joint is corrected to the desired center by pressing against the semiconductor wafer such that the center thereof is corrected to the desired center.

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