CN210899105U

CN210899105U - Electric leakage feedback dynamic D trigger, data operation unit, chip, force calculation board and computing equipment

Info

Publication number: CN210899105U
Application number: CN201921665547.8U
Authority: CN
Inventors: 刘杰尧; 张楠赓; 吴敬杰; 马晟厚
Original assignee: Hangzhou Canaan Creative Information Technology Ltd
Current assignee: Hangzhou Canaan Creative Information Technology Ltd
Priority date: 2019-09-30
Filing date: 2019-09-30
Publication date: 2020-06-30
Anticipated expiration: 2029-09-30

Abstract

The utility model provides a dynamic D trigger of electric leakage feedback, data arithmetic unit, chip, calculation power board and computational equipment. The leakage feedback dynamic D trigger comprises an input end, an output end and a clock signal end; a first data transmission unit; a first data latch unit; a second data transmission unit; a second data latch unit; the first data transmission unit, the first data latch unit, the second data transmission unit and the second data latch unit are sequentially connected in series between the input end and the output end, and a node is arranged between the first data transmission unit and the first data latch unit; the leakage current feedback unit is electrically connected between the node and the output end. The dynamic leakage current of the node can be effectively compensated, and the safety and accuracy of data are improved.

Description

Electric leakage feedback dynamic D trigger, data operation unit, chip, force calculation board and computing equipment

Technical Field

The utility model relates to a storage device that receives clock control especially relates to an electric leakage feedback developments D trigger, data arithmetic element, chip, calculation power board and the computational equipment who uses in extensive data arithmetic equipment.

Background

The dynamic D trigger has wide application and can be used for registering digital signals. Fig. 1 is a circuit configuration diagram of a conventional dynamic D flip-flop. As shown in fig. 1, the dynamic D flip-flop includes a transmission gate 101, an inverter 102, a transmission gate 103, and an inverter 104 connected in series between an input terminal D and an output terminal Q. The node S0 is formed between the transmission gate 101 and the inverter 102, the node S1 is formed between the transmission gate 103 and the inverter 104, and data is temporarily stored at the node S0 and/or the node S1 through the inverter 102 and the parasitic capacitance of the transistors in the inverter 104. However, node S0 is prone to dynamic leakage, resulting in temporary data loss.

Therefore, how to effectively reduce the dynamic leakage of the leakage feedback dynamic D flip-flop is a problem to be solved.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that a electric leakage feedback developments D trigger is provided, the dynamic leakage current of node can effectively be compensated, the security and the exactness of improvement data.

In order to achieve the above object, the present invention provides a leakage feedback dynamic D flip-flop, which includes an input end for inputting a data; an output terminal for outputting the data; a clock signal terminal for providing a clock signal; a first data transmission unit for transmitting the data under the control of the clock signal; the first data latch unit is used for latching the data transmitted by the first data transmission unit; the second data transmission unit is used for transmitting the data latched by the first data latch unit under the control of the clock signal; the second data latch unit is used for latching the data transmitted by the second data transmission unit; the first data transmission unit, the first data latch unit, the second data transmission unit and the second data latch unit are sequentially connected in series between the input end and the output end, and a node is arranged between the first data transmission unit and the first data latch unit; the leakage current feedback unit is electrically connected between the node and the output end.

In the above leakage feedback dynamic D flip-flop, the leakage feedback unit has a first end, a second end and a control end, the first end is electrically connected to the output end, and the second end is electrically connected to the node.

In the above leakage feedback dynamic D flip-flop, the leakage feedback unit includes a PMOS transistor and an NMOS transistor, and the PMOS transistor and the NMOS transistor are connected in series between the output terminal and the node.

In the above leakage feedback dynamic D flip-flop, the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the output terminal, the drain terminal of the PMOS transistor is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the node.

In the above leakage feedback dynamic D flip-flop, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a ground.

In the above leakage feedback dynamic D flip-flop, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to the node.

In the above leakage feedback dynamic D flip-flop, the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the NMOS transistor is electrically connected to the output terminal, the drain terminal of the NMOS transistor is electrically connected to the drain terminal of the PMOS transistor, and the source terminal of the PMOS transistor is electrically connected to the node.

In the above leakage feedback dynamic D flip-flop, the gate terminals of the PMOS transistor and the NMOS transistor are connected in parallel and electrically connected to a power supply.

In the above leakage feedback dynamic D flip-flop, the leakage feedback unit includes a PMOS transistor, the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the output terminal, the drain terminal of the PMOS transistor is electrically connected to the node, and the gate terminal of the PMOS transistor is electrically connected to a power source.

In the above leakage feedback dynamic D flip-flop, the leakage feedback unit includes an NMOS transistor having a source terminal, a drain terminal and a gate terminal, the drain terminal of the NMOS transistor is electrically connected to the output terminal, the source terminal is electrically connected to the node, and the gate terminal is electrically connected to a ground.

In the above leakage feedback dynamic D flip-flop, the clock signal includes a first clock signal and a second clock signal, and the first clock signal and the second clock signal are in opposite phases.

In the above leakage feedback dynamic D flip-flop, the first data transmission unit and/or the second data transmission unit are transmission gates.

In the above leakage feedback dynamic D flip-flop, the first data latch unit and/or the second data latch unit is an inverter.

Use the utility model discloses a dynamic D trigger of electric leakage feedback can effectively compensate the dynamic leakage current of node, improves the security and the exactness of data.

In order to better achieve the above object, the present invention further provides a data operation unit, which comprises a control circuit, an operation circuit, and a plurality of leakage feedback dynamic D flip-flops connected in series and/or in parallel; the plurality of leakage feedback dynamic D triggers are any one of the leakage feedback dynamic D triggers.

In order to better achieve the above object, the present invention further provides a chip, wherein the chip comprises at least one data operation unit.

To better achieve the above objects, the present invention also provides a computing board for a computing device, wherein at least one chip as described above is included.

In order to better achieve the above object, the utility model also provides a computing device, including power strip, control panel, connecting plate, radiator and a plurality of power strip, the control panel passes through the connecting plate with power strip connects, the radiator sets up around power strip, the power strip be used for to the connecting plate the control panel the radiator and power strip provides the power, wherein, power strip is foretell power strip.

The utility model has the beneficial effects that: the dynamic leakage current of the node can be effectively compensated, and the safety and accuracy of data are improved.

The present invention will be described in detail with reference to the accompanying drawings and specific embodiments, but the present invention is not limited thereto.

Drawings

FIG. 1 is a schematic circuit diagram of a conventional dynamic D flip-flop;

fig. 2 is a schematic circuit structure diagram of a leakage feedback dynamic D flip-flop according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a leakage feedback dynamic D flip-flop according to another embodiment of the present invention;

fig. 4 is a schematic circuit diagram of a leakage feedback dynamic D flip-flop according to another embodiment of the present invention;

fig. 5 is a schematic circuit diagram of a leakage feedback dynamic D flip-flop according to yet another embodiment of the present invention;

fig. 6 is a schematic diagram of a circuit structure of a leakage feedback dynamic D flip-flop according to an embodiment of the present invention;

fig. 7 is a schematic circuit diagram of a leakage feedback dynamic D flip-flop according to another embodiment of the present invention;

fig. 8 is a schematic structural diagram of the data operation unit of the present invention;

fig. 9 is a schematic structural diagram of the chip of the present invention;

fig. 10 is a schematic structural view of the force calculating plate of the present invention;

fig. 11 is a schematic structural diagram of the computing device of the present invention.

Wherein, the reference numbers:

100: dynamic D flip-flop

101. 103: transmission gate

102. 104: inverter with a capacitor having a capacitor element

200: leakage feedback dynamic D trigger

201: first data transmission unit

202: first data latch unit

203: second data transmission unit

204: second data latch unit

205: leakage feedback unit

201P, 203P, 205P: PMOS transistor

201N, 203N, 205N: NMOS transistor

800: data arithmetic unit

801: control circuit

802: arithmetic circuit

900: chip and method for manufacturing the same

901: control unit

1000: force calculating board

1100: computing device

1101: connecting plate

1102: control panel

1103: heat radiator

1104: power panel

D: input terminal

Q: output end

CKP, CKN: clock signal

S0, S1: node point

Detailed Description

The following describes the structural and operational principles of the present invention in detail with reference to the accompanying drawings:

certain terms are used throughout the description and following claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This specification and the claims that follow do not intend to distinguish between components that differ in name but not function.

In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, the term "connected" is intended to encompass any direct or indirect electrical connection. Indirect electrical connection means include connection by other means.

The first embodiment is as follows:

fig. 2 is a schematic diagram of a circuit structure of an embodiment of the dynamic D flip-flop with leakage feedback. As shown in fig. 2, the leakage feedback dynamic D flip-flop 200 includes an input terminal D, an output terminal Q, a clock signal terminal CKN, a clock signal terminal CKP, a first data transmission unit 201, a first data latch unit 202, a second data transmission unit 203, a second data latch unit 204, and a leakage feedback unit 205. The first data transfer unit 201, the first data latch unit 202, the second data transfer unit 203, and the second data latch unit 204 are sequentially connected in series between the input terminal D and the output terminal Q, and a node S0 is formed between the first data transfer unit 201 and the first data latch unit 202. The leakage feedback unit 205 is electrically connected between the node S0 and the output terminal Q. The input end D is used for inputting data, the output end is used for outputting data, the clock signal end CKN and the clock signal end CKP are used for providing a clock signal CKN and a clock signal CKP, and the clock signal CKN and the clock signal CKP are inverted clock signals.

Specifically, as shown in fig. 2, the first data transmission unit 201 of the leakage feedback dynamic D flip-flop 200 is a transmission gate structure, and the data transmission unit 201 includes a PMOS transistor 201P and an NMOS transistor 201N connected in parallel. The source terminal of the PMOS transistor 201P and the source terminal of the NMOS transistor 201N are connected in parallel and electrically connected to the input terminal D of the leakage feedback dynamic D flip-flop 200, and the drain terminal of the PMOS transistor 201P and the drain terminal of the NMOS transistor 201N are connected in parallel and electrically connected to the node S0. The gate of the NMOS transistor 201N is electrically connected to the clock signal CKN, and the gate of the PMOS transistor 201P is electrically connected to the clock signal CKP. When CKP is low, CKN is high, the PMOS transistor 201P and the NMOS transistor 201N are both in a conducting state, and the data at the input end D of the leakage feedback dynamic D flip-flop 200 is transmitted to the node S0 through the first data transmission unit 201. When CKP is high, CKN is low, PMOS transistor 201P and NMOS transistor 201N are both in a non-conducting state, and data at input D of the leakage feedback dynamic D flip-flop 200 cannot be transmitted to node S0 through the first data transmission unit 201. In this embodiment, the first data transmission unit 201 is exemplified by a transmission gate structure, and of course, other types of data transmission units may be used as long as the switching function can be realized under the control of the clock signal, and the present invention is not limited thereto.

With continued reference to fig. 2, the first data latch unit 202 of the leakage feedback dynamic D flip-flop 200 is an inverter structure, and the first data latch unit 202 can temporarily store the data transmitted from the first data transmission unit 201, i.e., the data at the node S0, by using its parasitic capacitance, and can also invert the data at the node S0 and transmit the inverted data to the second data transmission unit 203.

As shown in fig. 2, the second data transmission unit 202 of the leakage feedback dynamic D flip-flop 200 is a transmission gate structure, and the second data transmission unit 203 includes a PMOS transistor 203P and an NMOS transistor 203N connected in parallel. The source terminal of the PMOS transistor 203P and the source terminal of the NMOS transistor 203N are connected in parallel and electrically connected to the first data latch unit 202, and the drain terminal of the PMOS transistor 203P and the drain terminal of the NMOS transistor 203N are connected in parallel and electrically connected to the second data latch unit 204. The gate of the NMOS transistor 203N is electrically connected to the clock signal CKP, and the gate of the PMOS transistor 203P is electrically connected to the clock signal CKN. When CKN is low, CKP is high, both the PMOS transistor 203P and the NMOS transistor 203N are turned on, and the data output from the first data latch unit 202 is transmitted to the second data latch unit 204 through the second data transmission unit 203. When CKN is high, CKP is low, the PMOS transistor 203P and the NMOS transistor 203N are both in a non-conducting state, and the data at the input end D of the leakage feedback dynamic D flip-flop 200 cannot be transmitted to the second data latch unit 204 through the second data transmission unit 203. In this embodiment, the second data transmission unit 203 is exemplified by a transmission gate structure, and of course, other types of data transmission units are also possible as long as the switching function can be realized under the control of the clock signal, and the present invention is not limited thereto.

Continuing to refer to fig. 2, the second data latch unit 204 of the leakage feedback dynamic D flip-flop 200 is an inverter structure, and the second data latch unit 204, like the first data latch unit 202, can not only temporarily store the data transmitted from the second data transmission unit 203 by using its parasitic capacitance, but also invert the received data and transmit the inverted data to the output Q of the leakage feedback dynamic D flip-flop 200.

As can be seen, the first data transmission unit 201 and the second data transmission unit 203 are controlled by the inverted clock signal, that is, the first data transmission unit 201 and the second data transmission unit 203 are not turned on and/or off at the same time, and the first data latch unit 202 and the second data latch unit 204 in the leakage feedback dynamic D flip-flop 200 function as data registers according to the clock signal. And, the data at the input end D of the leakage feedback dynamic D flip-flop 200 passes through the inverse phases of the first data latch unit 202 and the second data latch unit 204, so that the data at the output end Q is in phase with the data at the input end D. Meanwhile, the first data latch unit 202 and the second data latch unit 204 may also function to improve data driving capability.

As shown in fig. 2, the leakage feedback dynamic D flip-flop 200 further includes a leakage feedback unit 205. In the present embodiment, the leakage feedback unit 205 includes a PMOS transistor 205P and an NMOS transistor 205N, and the PMOS transistor 205P and the NMOS transistor 205N are connected in series between the output terminal Q and the node S0. The source terminal of the PMOS transistor 205P is electrically connected to the output terminal Q, the drain terminal of the PMOS transistor 205P is electrically connected to the drain terminal of the NMOS transistor 205N, the source terminal of the NMOS transistor 205N is electrically connected to the node S0, and the gate terminals of the PMOS transistor 205P and the NMOS transistor 205N are connected together in parallel and are electrically connected to ground VSS.

Since the gate terminals of the PMOS transistor 205P and the NMOS transistor 205N are also electrically connected to ground VSS, the PMOS transistor 205P is in the on state and the NMOS transistor 205N is in the off state under the driving of the low-level signal of ground VSS. At this time, the leakage feedback unit 205 may feed back the leakage current of the output terminal Q to the node S0, compensate the dynamic leakage current at the node S0, and increase the stability of the data at the node S0.

Example two:

fig. 3 is a schematic circuit diagram of a leakage feedback dynamic D flip-flop according to another embodiment of the present invention. Fig. 3 is a schematic diagram of a circuit structure of a leakage feedback dynamic D flip-flop according to an embodiment of the present invention. As shown in fig. 3, the leakage feedback dynamic D flip-flop 200 includes an input terminal D, an output terminal Q, a clock signal terminal CKN, a clock signal terminal CKP, a first data transmission unit 201, a first data latch unit 202, a second data transmission unit 203, a second data latch unit 204, and a leakage feedback unit 205. The first data transfer unit 201, the first data latch unit 202, the second data transfer unit 203, and the second data latch unit 204 are sequentially connected in series between the input terminal D and the output terminal Q, and a node S0 is formed between the first data transfer unit 201 and the first data latch unit 202. The leakage feedback unit 205 is electrically connected between the node S0 and the output terminal Q. The input end D is used for inputting data, the output end is used for outputting data, the clock signal end CKN and the clock signal end CKP are used for providing a clock signal CKN and a clock signal CKP, and the clock signal CKN and the clock signal CKP are inverted clock signals.

Specifically, as shown in fig. 3, the first data transmission unit 201 of the leakage feedback dynamic D flip-flop 200 is a transmission gate structure, and the data transmission unit 201 includes a PMOS transistor 201P and an NMOS transistor 201N connected in parallel. The source terminal of the PMOS transistor 201P and the source terminal of the NMOS transistor 201N are connected in parallel and electrically connected to the input terminal D of the leakage feedback dynamic D flip-flop 200, and the drain terminal of the PMOS transistor 201P and the drain terminal of the NMOS transistor 201N are connected in parallel and electrically connected to the node S0. The gate of the NMOS transistor 201N is electrically connected to the clock signal CKN, and the gate of the PMOS transistor 201P is electrically connected to the clock signal CKP. When CKP is low, CKN is high, the PMOS transistor 201P and the NMOS transistor 201N are both in a conducting state, and the data at the input end D of the leakage feedback dynamic D flip-flop 200 is transmitted to the node S0 through the first data transmission unit 201. When CKP is high, CKN is low, PMOS transistor 201P and NMOS transistor 201N are both in a non-conducting state, and data at input D of the leakage feedback dynamic D flip-flop 200 cannot be transmitted to node S0 through the first data transmission unit 201. In this embodiment, the first data transmission unit 201 is exemplified by a transmission gate structure, and of course, other types of data transmission units may be used as long as the switching function can be realized under the control of the clock signal, and the present invention is not limited thereto.

With continued reference to fig. 3, the first data latch unit 202 of the leakage feedback dynamic D flip-flop 200 is an inverter structure, and the first data latch unit 202 can temporarily store the data transmitted from the first data transmission unit 201, i.e., the data at the node S0, by using its parasitic capacitance, and can also invert the data at the node S0 and transmit the inverted data to the second data transmission unit 203.

As shown in fig. 3, the second data transmission unit 202 of the leakage feedback dynamic D flip-flop 200 is a transmission gate structure, and the second data transmission unit 203 includes a PMOS transistor 203P and an NMOS transistor 203N connected in parallel. The source terminal of the PMOS transistor 203P and the source terminal of the NMOS transistor 203N are connected in parallel and electrically connected to the first data latch unit 202, and the drain terminal of the PMOS transistor 203P and the drain terminal of the NMOS transistor 203N are connected in parallel and electrically connected to the second data latch unit 204. The gate of the NMOS transistor 203N is electrically connected to the clock signal CKP, and the gate of the PMOS transistor 203P is electrically connected to the clock signal CKN. When CKN is low, CKP is high, both the PMOS transistor 203P and the NMOS transistor 203N are turned on, and the data output from the first data latch unit 202 is transmitted to the second data latch unit 204 through the second data transmission unit 203. When CKN is high, CKP is low, the PMOS transistor 203P and the NMOS transistor 203N are both in a non-conducting state, and the data at the input end D of the leakage feedback dynamic D flip-flop 200 cannot be transmitted to the second data latch unit 204 through the second data transmission unit 203. In this embodiment, the second data transmission unit 203 is exemplified by a transmission gate structure, and of course, other types of data transmission units are also possible as long as the switching function can be realized under the control of the clock signal, and the present invention is not limited thereto.

As shown in fig. 3, the second data latch unit 204 of the leakage feedback dynamic D flip-flop 200 is an inverter structure, and the second data latch unit 204, like the first data latch unit 202, can not only temporarily store the data transmitted from the second data transmission unit 203 by using its parasitic capacitance, but also invert the data and transmit the data to the output Q of the leakage feedback dynamic D flip-flop 200.

As shown in fig. 3, the leakage compensation dynamic register 200 further includes a leakage feedback unit 205. The difference from the embodiment shown in fig. 2 is that in the present embodiment, the leakage feedback unit 205 includes a PMOS transistor 205P and an NMOS transistor 205N, and the PMOS transistor 205P and the NMOS transistor 205N are connected in series between the output terminal Q and the node S0. The source terminal of the PMOS transistor 205P is electrically connected to the node S0, the drain terminal of the PMOS transistor 205P is electrically connected to the drain terminal of the NMOS transistor 205N, the source terminal of the NMOS transistor 205N is electrically connected to the output terminal Q, and the gate terminals of the PMOS transistor 205P and the NMOS transistor 205N are connected together in parallel and electrically connected to the power VDD.

Since the gate terminals of the PMOS transistor 205P and the NMOS transistor 205N are also electrically connected to the power supply VDD, the PMOS transistor 205P is in the off state and the NMOS transistor 205N is in the on state under the driving of the high-level signal of the power supply VDD. Therefore, the leakage feedback unit 205 can feed back the leakage current of the output terminal Q to the node S0, and can compensate the leakage current at the node S0, thereby increasing the stability of the data at the node S0.

Modification example:

fig. 4 is a schematic circuit diagram of a leakage compensation dynamic register according to another embodiment of the present invention. As shown in fig. 2 and 4, the difference between the embodiments of fig. 2 and the leakage feedback unit 205 is that in the present embodiment, the gate terminals of the PMOS transistor 205P and the NMOS transistor 205N are connected together in parallel and electrically connected to the node S0.

Since the gate terminals of the PMOS transistor 205P and the NMOS transistor 205N are also electrically connected to the node S0, under the driving of the same level signal, the PMOS transistor 205P and the NMOS transistor 205N are not turned on at the same time, and only one is turned on and the other is turned off. For example, when the potential at the node S0 is high level, the PMOS transistor 205P is in an off state, and the NMOS transistor 205N is in an on state; when the potential at the node S0 is low, the PMOS transistor 205P is in an on state, and the NMOS transistor 205N is in an off state. Therefore, the leakage feedback unit 205 can feed back the leakage current of the output terminal Q to the node S0, and can compensate the leakage current at the node S0, thereby increasing the stability of the data at the node S0.

Fig. 5 is a schematic circuit diagram of a leakage compensation dynamic register according to another embodiment of the present invention. As shown in fig. 3 and 5, the difference between the embodiments of fig. 3 is that in the leakage feedback unit 205 of the present embodiment, the gate terminals of the PMOS transistor 205P and the NMOS transistor 205N are connected together in parallel and electrically connected to the node S0.

Fig. 6 is a schematic circuit diagram of an embodiment of the dynamic register with leakage compensation according to the present invention. As shown in fig. 6, the leakage feedback unit 205 of the leakage compensated dynamic register 200 includes a PMOS transistor 205P, a source terminal of the PMOS transistor 205P is electrically connected to the output terminal, a drain terminal of the PMOS transistor 205P is electrically connected to the node S0, and a gate terminal of the PMOS transistor 205P is electrically connected to the power VDD.

Since the gate terminal of the PMOS transistor 205P is electrically connected to the power supply VDD, the PMOS transistor 205P is in the off state driven by the high level signal of the power supply VDD. Therefore, the leakage feedback unit 205 can feed back the leakage current of the output terminal Q to the node S0, and can compensate the leakage current at the node S0, thereby increasing the stability of the data at the node S0.

Fig. 7 is a schematic circuit diagram of a leakage compensation dynamic register according to another embodiment of the present invention. As shown in fig. 7, the leakage feedback unit 205 of the leakage compensated dynamic register 200 includes an NMOS transistor 205N, a source terminal of the NMOS transistor 205N is electrically connected to the node S0, a drain terminal of the NMOS transistor 205N is electrically connected to the output terminal Q, and a gate terminal of the NMOS transistor 205N is electrically connected to the ground VSS.

Since the gate terminal of the NMOS transistor 205N is electrically connected to ground VSS, the NMOS transistor 205N is in the off state driven by the low-level signal of ground VSS. Therefore, the leakage feedback unit 205 can feed back the leakage current of the output terminal Q to the node S0, and can compensate the leakage current at the node S0, thereby increasing the stability of the data at the node S0.

The utility model also provides a data arithmetic unit, figure 8 is the utility model discloses data arithmetic unit's schematic structure diagram. As shown in fig. 8, the data operation unit 800 includes a control circuit 801, an operation circuit 802, and a plurality of leakage feedback dynamic D flip-flops 200. The control circuit 801 refreshes data in the leakage feedback dynamic D flip-flop 200 and reads data from the leakage feedback dynamic D flip-flop 200, and the arithmetic circuit 802 performs arithmetic on the read data and outputs an arithmetic result from the control circuit 801.

The utility model also provides a chip, fig. 9 is the utility model discloses the structural schematic of chip. As shown in fig. 9, the chip 900 includes a control unit 901, and one or more data operation units 900. The control unit 901 inputs data to the data operation unit 900 and processes the data output by the data operation unit 900.

The utility model discloses still provide a calculate the power board, fig. 10 is the utility model discloses calculate the structural schematic diagram of power board. As shown in fig. 10, each computing board 1000 includes one or more chips 900 for performing large-scale operations on the working data sent by the computing device.

The utility model also provides a computing equipment, computing equipment is preferred to be used for excavating the operation of virtual digital currency, of course computing equipment also can be used for any other magnanimity operation. Fig. 11 is a schematic structural diagram of the computing device of the present invention. As shown in fig. 11, each computing device 1100 includes a connection board 1101, a control board 1102, a heat sink 1103, a power board 1104, and one or more computing boards 1000. The control board 1102 is connected to the force computing board 1000 via a connection board 1101, and a heat sink 1103 is disposed around the force computing board 1000. The power board 1104 is used for supplying power to the connection board 1101, the control board 1102, the heat sink 1103 and the computing power board 1000.

It should be noted that, in the description of the present invention, the terms "lateral", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In other words, the present invention may have other embodiments, and those skilled in the art can make various corresponding changes and modifications according to the present invention without departing from the spirit and the essence of the present invention, and these corresponding changes and modifications should fall within the protection scope of the appended claims.

Claims

1. A leakage feedback dynamic D flip-flop, comprising:

an input end for inputting a data;

an output terminal for outputting the data;

a clock signal terminal for providing a clock signal;

a first data transmission unit for transmitting the data under the control of the clock signal;

the first data latch unit is used for latching the data transmitted by the first data transmission unit;

the second data transmission unit is used for transmitting the data latched by the first data latch unit under the control of the clock signal;

the second data latch unit is used for latching the data transmitted by the second data transmission unit;

the first data transmission unit, the first data latch unit, the second data transmission unit and the second data latch unit are sequentially connected in series between the input end and the output end, and a node is arranged between the first data transmission unit and the first data latch unit;

the leakage current feedback unit is electrically connected between the node and the output end.

2. The leaky feedback dynamic D flip-flop of claim 1, wherein: the leakage feedback unit has a first end, a second end and a control end, wherein the first end is electrically connected to the output end, and the second end is electrically connected to the node.

3. The leaky feedback dynamic D flip-flop of claim 2, wherein: the leakage feedback unit comprises a PMOS transistor and an NMOS transistor which are connected in series between the output end and the node.

4. The leaky feedback dynamic D flip-flop of claim 3, wherein: the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the PMOS transistor is electrically connected to the output terminal, the drain terminal of the PMOS transistor is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the node.

5. The leaky feedback dynamic D flip-flop of claim 4, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to a power supply.

6. The leaky feedback dynamic D flip-flop of claim 4, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to the node.

7. The leaky feedback dynamic D flip-flop of claim 3, wherein: the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal of the NMOS transistor is electrically connected to the output terminal, the drain terminal of the NMOS transistor is electrically connected to the drain terminal of the PMOS transistor, and the source terminal of the PMOS transistor is electrically connected to the node.

8. The leaky feedback dynamic D flip-flop of claim 7, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to the ground.

9. The leaky feedback dynamic D flip-flop of claim 7, wherein: the grid ends of the PMOS transistor and the NMOS transistor are connected in parallel and are electrically connected to the node.

10. The leaky feedback dynamic D flip-flop of claim 2, wherein: the leakage feedback unit comprises a PMOS transistor, wherein the PMOS transistor is provided with a source end, a drain end and a grid end, the source end of the PMOS transistor is electrically connected to the output end, the drain end of the PMOS transistor is electrically connected to the node, and the grid end of the PMOS transistor is electrically connected to a power supply.

11. The leaky feedback dynamic D flip-flop of claim 2, wherein: the leakage feedback unit comprises an NMOS transistor, wherein the NMOS transistor is provided with a source end, a drain end and a grid end, the drain end of the NMOS transistor is electrically connected to the output end, the source end is electrically connected to the node, and the grid end is electrically connected to the ground.

12. The leaky feedback dynamic D flip-flop of claim 1, wherein: the clock signal comprises a first clock signal and a second clock signal, and the first clock signal and the second clock signal are in opposite phases.

13. The leaky feedback dynamic D flip-flop of claim 1, wherein: the first data transmission unit and/or the second data transmission unit are transmission gates.

14. The leaky feedback dynamic D flip-flop of claim 1, wherein: the first data latch unit and/or the second data latch unit are inverters.

15. A data arithmetic unit comprises a control circuit, an arithmetic circuit and a plurality of leakage feedback dynamic D triggers which are connected in an interconnecting way, wherein the leakage feedback dynamic D triggers are connected in series and/or in parallel; the method is characterized in that: the leakage feedback dynamic D flip-flops of any one of claims 1-14.

16. A chip comprising at least one data arithmetic unit as claimed in claim 15.

17. An computing force board for a computing device comprising at least one chip as recited in claim 16.

18. A computing device comprises a power panel, a control panel, a connecting plate, a radiator and a plurality of computing plates, wherein the control panel is connected with the computing plates through the connecting plate, the radiator is arranged around the computing plates, the power panel is used for providing power for the connecting plate, the control panel, the radiator and the computing plates, and the computing plates are characterized in that: the force computing board is as claimed in claim 17.