CN209182771U - On-chip series power supply system and arithmetic unit, chip, force computing board and computing equipment using same - Google Patents
On-chip series power supply system and arithmetic unit, chip, force computing board and computing equipment using same Download PDFInfo
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- CN209182771U CN209182771U CN201821680948.6U CN201821680948U CN209182771U CN 209182771 U CN209182771 U CN 209182771U CN 201821680948 U CN201821680948 U CN 201821680948U CN 209182771 U CN209182771 U CN 209182771U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The utility model provides an on-chip series connection power supply system and use its arithmetic unit, chip, calculation power board and computational equipment. The on-chip series power supply system comprises two or more voltage domains to be supplied, wherein the voltage domains to be supplied are connected between a power supply and the ground in series; the power supply device comprises two or more isolation regions, a power supply voltage domain and a power supply voltage domain, wherein the isolation regions are formed in the isolation regions and used for isolating the power supply voltage domain; the isolation regions are connected in series between the power supply and the ground; the power supply compensation unit is connected between the voltage domain to be supplied and the isolation region and is used for providing power supply compensation for the voltage domain to be supplied; the device also comprises a voltage stabilizing unit, wherein the voltage stabilizing unit is connected to two ends of each isolation region in parallel. The utility model discloses a series connection power supply system in piece can effectively reduce the consumption, reduces the design degree of difficulty, practices thrift chip area, reduces manufacturing cost.
Description
Technical field
The utility model relates to a kind of multiple voltage domain power supply system, in particular to it is a kind of with voltage regulation unit based on substrate
In the piece that benchmark compensates supply voltage cascade electric power system and application its arithmetic element, chip, calculate power plate and calculating
Equipment.
Background technique
Ideal money (such as bit coin, ether coin) is a kind of digital cash of P2P form, and bit coin system was pushed away from 2009
It has just been had received widespread attention since out.The system is the Distributed sharing general ledger based on block chain building, can guarantee in this way be
The safe and reliable and decentralization of system operation.
In Hash operation and proof of work, bit coin is based on the unique correct cryptographic Hash being calculated, to demonstrate,prove
Bright workload is packaged block power to obtain book keeping operation, therefore is rewarded, and here it is proof of work (Pow).At present in addition to sudden and violent
Outside power calculates, there are no effective algorithms to carry out Hash operation.A new generation is set for excavating the calculating of virtual digit currency
For standby, digging mine process is exactly the logic calculation assembly line for carrying out a large amount of repeatability.
Such core for calculating equipment design is power dissipation ratio of performance, and higher performance and lower power consumption indicate to dig mine
It is more efficient, while meaning to can be realized under identical power consumption and more calculating power.
In addition, the logic calculation of a large amount of repeatability is needed to the biggish electric current of equipment offer is calculated, this be will lead to except logic
Except power consumption needed for calculating, the extra power consumption for calculating equipment is also larger.Therefore, it is necessary to reduce the operating current for calculating equipment,
To reduce its extra power consumption.
CN206039425U discloses a kind of series-fed circuit, as shown in Figure 1, serial between feeder ear VCC and ground
Multiple encapsulation units are connected, one or more groups of elements are respectively included in each encapsulation unit, every set of pieces includes one and is connected
Chip and Auxiliary Power Units to be powered, be connected in series a signal respectively between the chip to be powered in two groups of adjacent elements
Level conversion unit.Although the series-fed circuit may be implemented to provide low supply voltage to each chip to be powered, its
It is directed to different encapsulation units on printed circuit board and series-fed is provided, cannot achieve to chip interior different voltages domain
Between series-fed.
Multiple voltage domain (Multi-supply voltage domain) power supply technique is more and more widely used on piece core
Piece system (System-on-chip, SoC) and multiprocessor calculate in structure.In the chip for applying multiple voltage domain technology,
The chip usually contains multiple independent voltage domains or voltage island, and the module under each voltage domain is according to the requirement of its timing
Work is under appropriate supply voltage.Generally, for the more crucial module of timing, it is usually operated at high power supply electricity
It depresses under (VDDH), to meet requirement of the chip to speed ability；And for non-key circuit module, it then works low
Under supply voltage (VDDL) even subthreshold value supply voltage, to reduce the power consumption consumption and energy consumption of chip.
CN206523836U discloses a kind of chip interior cascade electric power system, as shown in Fig. 2, in series-fed chip,
A chip core (core) can be respectively included in each unit to be powered, alternatively, can distinguish in each unit to be powered
Chip core including multiple parallel connections.The chip core in every step voltage domain respectively includes the oxidation of P-channel metal in circuit
Object semiconductor (P-channel Metal Oxide Semiconductor, PMOS) pipe and N-channel metal-oxide semiconductor (MOS)
(N-channel metal oxide semiconductor, NMOS) pipe.The chip core in every step voltage domain, PMOS tube
Substrate is connected with the supply voltage of the same level voltage domain or operating voltage (VDD), and the VDD and upper level of the same level voltage domain
The ground (VSS) of voltage domain is connected, and further includes n for realizing the deep trap being isolated between different voltages domain in series-fed chip,
This n deep trap is arranged independently of each other, is mutually not attached to, and each of n units to be powered unit to be powered is located at a depth
In trap, to realize the isolation between different voltages domain on the same chip, effectively prevent being formed between different voltages domain short
Road.Although the chip interior cascade electric power system realizes the series-fed between chip interior different voltages domain, still, each
Voltage domain is other than power vd D is powered, it is also necessary to be additionally provided auxiliary voltage source VDD_1, VDD_2 etc., not only assist
Voltage source difficult design, and a large amount of chip area can be occupied, generate larger power consumption.
Utility model content
The technical problem to be solved by the utility model is to provide cascade electric power system in a kind of piece based on substrate benchmark,
Cascade electric power system not only reduces power consumption in sheet above, also reduces design difficulty, saves chip area, and reduction is produced into
This.
To achieve the goals above, the utility model provides a kind of interior cascade electric power system, comprising:
Two or more voltage domains to be powered, the voltage domain to be powered are connected in series between power supply and ground；
Two or more area of isolation, the voltage domain to be powered are formed in the area of isolation, it is described every
From region for the voltage domain to be powered to be isolated；
The area of isolation is connected in series between the power supply and the ground；
Power supply compensating unit is connected between the voltage domain to be powered and the area of isolation, for described wait supply
Piezoelectric voltage domain provides power supply compensation；
It wherein, further include voltage regulation unit, the voltage regulation unit is connected in each area of isolation both ends in parallel.
Cascade electric power system in above-mentioned piece, wherein the power supply compensating unit is by work in saturation state to described
Voltage domain to be powered provides power supply compensation.
Cascade electric power system in above-mentioned piece, wherein form the first power end and the at each area of isolation both ends
One ground terminal, first power end and/or first ground terminal are used to provide reference voltage to the power supply compensating unit.
Cascade electric power system in above-mentioned piece, wherein form second source end at each voltage domain both ends to be powered
With the second ground terminal, the power supply compensating unit provides power supply compensation to the second source end and/or second ground terminal.
Cascade electric power system in above-mentioned piece, wherein on the basis of the reference voltage, when the second source end and/
Or the voltage change range of second ground terminal is when being more than the threshold value of the power supply compensating unit, power supply compensating unit work
In the saturation state.
Cascade electric power system in above-mentioned piece, wherein the power supply compensating unit is switching transistor.
Cascade electric power system in above-mentioned piece, wherein the switching transistor is that PMOS switch transistor and/or NMOS are opened
Close transistor.
Cascade electric power system in above-mentioned piece, wherein the PMOS switch transistor and/or the NMOS switch crystal
Pipe is one or more.
Cascade electric power system in above-mentioned piece, wherein be formed with one or more semiconductors in the voltage domain to be powered
Device, the second source end and/or second ground terminal provide substrate bias to the semiconductor devices.
Cascade electric power system in above-mentioned piece, wherein the semiconductor devices includes PMOS transistor and/or NMOS brilliant
Body pipe, the second source end provide substrate bias to the PMOS transistor, and second ground terminal is to the NMOS transistor
Substrate bias is provided.
Cascade electric power system in above-mentioned piece, wherein the voltage regulation unit is for the first power end and/or institute described in pressure stabilizing
State the voltage of the first ground terminal.
Cascade electric power system in above-mentioned piece, wherein the voltage regulation unit includes one of resistance, capacitor or diode
Or it is a variety of.
Cascade electric power system in above-mentioned piece, wherein the voltage regulation unit be connected directly between first power end and
Between first ground terminal, or it is connected between first power end and first ground terminal by analog switch.
Cascade electric power system in above-mentioned piece, wherein be arranged one between first ground terminal and second ground terminal
Analog switch.
To achieve the goals above, the utility model also provides a kind of Data Computation Unit, wherein the data operation list
Member includes cascade electric power system in the control circuit of interconnection connection, computing circuit, storage circuit, and one or more pieces,
In, described interior cascade electric power system is cascade electric power system in any one above-mentioned piece.
To achieve the goals above, the utility model also provides a kind of chip, wherein the chip includes above-mentioned any
A kind of Data Computation Unit.
To achieve the goals above, the utility model also provides a kind of for calculating the calculation power plate in equipment, wherein described
Calculating power plate includes any one above-mentioned chip.
To achieve the goals above, the utility model also provides a kind of calculating equipment, including power panel, control panel, connection
Plate, radiator and multiple calculation power plates, the control panel are connect by the connecting plate with the calculation power plate, and the radiator is set
It sets around the calculation power plate, the power panel is used for the connecting plate, the control panel, the radiator and described
It calculates power plate and power supply is provided, wherein the calculation power plate is any one the above-mentioned calculation power plate.
The beneficial functional of the utility model is: using cascade electric power system in the piece of the utility model, may be implemented
Under the premise of not needing accessory power supply, relatively stable operating voltage can also be provided to voltage domain to be powered.This not only reduces
Power consumption also reduces design difficulty, saves chip area, reduces production cost.
The utility model is described in detail below in conjunction with the drawings and specific embodiments, but not as to the utility model
Restriction.
Detailed description of the invention
Fig. 1 is existing series-fed circuit diagram；
Fig. 2 is existing chip interior cascade electric power system schematic diagram；
Fig. 3 be the utility model not in lozenge cascade electric power system series-fed electrical block diagram；
Fig. 4 is cascade electric power system schematic diagram in the piece of an embodiment of the present invention；
Fig. 5 is cascade electric power system schematic diagram in the piece of another embodiment of the utility model；
Fig. 6 is cascade electric power system schematic diagram in the piece of another embodiment of the utility model；
Fig. 7 is cascade electric power system schematic diagram in the piece of the utility model another embodiment；
Fig. 8 is cascade electric power system schematic diagram in the piece containing voltage regulation unit of an embodiment of the present invention；
Fig. 9 is cascade electric power system schematic diagram in the piece containing voltage regulation unit of another embodiment of the utility model；
Figure 10 is the utility model Data Computation Unit schematic diagram；
Figure 11 is the utility model chip schematic diagram；
Figure 12 is that the utility model calculates power plate schematic diagram；
Figure 13 is that the utility model calculates equipment schematic diagram.
Wherein, appended drawing reference:
10: series-fed circuit
100: cascade electric power system in piece
101-1,101-2 ... 101-n: voltage domain
102-1,102-2 ... 102-n: deep N-well
103-1,103-2 ... 103-n:P trap
104-1,104-2 ... 104-n:N trap
105,105 ': switching transistor
106: bulk resistor 107: voltage regulation unit
108: analog switch
VDD1, VDD2 ... VDDn: the power end of voltage domain
VSS1, VSS2 ... VSSn: the ground terminal of voltage domain
VPP1, VPP2 ... VPPn: the power end of deep N-well
VBB1, VBB2 ... VBBn: the ground terminal of deep N-well
VDD: system power supply GND: systematically
S: source terminal D: drain electrode end
G: gate terminal B: substrate terminal
700- Data Computation Unit 701- control circuit
702- computing circuit 703- storage circuit
800: chip 801: control unit
900: calculating power plate 1000: calculating equipment
1001: connecting plate 1002: control panel
1003: radiator 1004: power panel
Specific embodiment
The structural principle of the utility model and working principle are described in detail with reference to the accompanying drawing:
Some vocabulary has been used in specification and subsequent claim to censure specific components.Have in fields
Usually intellectual is, it is to be appreciated that manufacturer may call the same component with different nouns.This specification and subsequent
Claim not by the difference of title as distinguish component in a manner of, but with the difference of component functionally as
The criterion of differentiation.Throughout the specification, identical appended drawing reference indicates identical element.
" comprising " and "comprising" mentioned in working as in specification in the whole text and subsequent claim are an open use
Language, therefore should be construed to " including but not limited to ".In addition, " connection " word is directly and indirectly electrically to connect comprising any herein
Take over section.Indirect means of electrical connection includes being attached by other devices.
Fig. 3 be the utility model not in lozenge cascade electric power system series-fed electrical block diagram.Such as Fig. 3 institute
Show, by taking chip substrate is P type substrate as an example, n voltage domain 101-1,101- to be powered are formed in series-fed circuit 10
2......101-n wherein n is the positive integer greater than 1.Each voltage domain 101-1,101-2......101-n pass through one respectively
A corresponding deep N-well 102-1,102-2......102-n realizes the isolation between different voltages domain, to avoid different voltages domain
Between short circuit.A certain number of p-wells 103-1,103- are respectively formed in deep N-well 102-1,102-2......102-n
2......103-n and N trap 104-1,104-2......104-n.
PMOS transistor and/or NMOS transistor are all formed in each voltage domain 101-1,101-2......101-n,
If it is necessary, the other kinds of device such as resistance, capacitor can also be formed.Wherein, PMOS transistor is in N trap 104-1,104-
2......104-n it is formed in, NMOS transistor is formed in p-well 103-1,103-2......103-n.PMOS transistor and
NMOS transistor for realizing chip various functions.
Each voltage domain 101-1,101-2......101-n to be powered be sequentially connected in series in system power supply VDD and
Systematically between GND.The ground terminal VSS1 of power end VDD1 connection the system power supply VDD, voltage domain 101-1 of voltage domain 101-1 connect
It is connected to the power end VDD2 of next stage voltage domain 101-2, the ground terminal VSS2 of voltage domain 101-2 is connected to next stage voltage domain
The power end VDD3 of 101-3, successively connects to next stage, and the ground terminal VSSn of voltage domain 101-n is connected to systematically GND.Thus
Form n voltage domain of series-fed.
PMOS transistor or NMOS transistor have tetra- ports S/D/G/B, are referred to as source terminal, drain electrode end, grid
End and substrate terminal.Under normal conditions, the substrate terminal of the PMOS transistor in each voltage domain 101-1,101-2......101-n
Power end VDD1, VDD2......VDDn of the voltage domain, the substrate terminal of NMOS transistor and source are connected to together with source terminal
It is extremely connected to ground terminal VSS1, VSS2......VSSn of the voltage domain together.When the voltage between gate terminal and substrate terminal is super
When crossing threshold voltage, can in substrate formed source terminal arrive drain electrode end conductive channel, allow carrier source terminal with
Flowing in substrate between drain electrode end, forms electric current.
When n voltage domain of series-fed works normally, the power end VDD1 of each voltage domain,
VDD2......VDDn and the current potential of ground terminal VSS1, VSS2......VSSn are kept substantially stable state.Work as series-fed
N voltage domain in one of voltage domain 101-m (1≤m≤n) occur high current in the case where, due to voltage domain 101-m
The reason of self-resistance, the both ends of voltage domain 101-m form biggish voltage difference, will lead to other voltages for not generating high current
The voltage at domain both ends is affected to generate the drift of supply voltage, as the variation of electric current constantly generates drift, drift and
Size of current positive correlation, so as to cause the disabler of chip.
In order to avoid the generation of above situation, generally can all be improved by the way of increasing accessory power supply, i.e., every
Increase an accessory power supply on one voltage domain to be powered to the voltage domain.The utility model provides a kind of based on substrate benchmark
Cascade electric power system in piece can reduce the voltage drift at voltage domain both ends in the case where not increasing accessory power supply.
Embodiment one
Fig. 4 is cascade electric power system schematic diagram in the piece of an embodiment of the present invention.As shown in figure 4, with chip substrate
Be formed in cascade electric power system 100 for P type substrate, in the utility model piece n voltage domain 101-1 to be powered,
101-2......101-n, wherein n is the positive integer greater than 1.Each voltage domain 101-1,101-2......101-n lead to respectively
The isolation between a corresponding deep N-well 102-1,102-2......102-n realization different voltages domain is crossed, to avoid different electricity
Press the short circuit between domain.Be respectively formed in deep N-well 102-1,102-2......102-n a certain number of p-well 103-1,
103-2......103-n and N trap 104-1,104-2......104-n.
PMOS transistor and/or NMOS transistor are all formed in each voltage domain 101-1,101-2......101-n,
If it is necessary, the other kinds of device such as resistance, capacitor can also be formed.Wherein, PMOS transistor be formed in N trap 104-1,
In 104-2......104-n, NMOS transistor is formed in p-well 103-1,103-2......103-n.PMOS transistor and
NMOS transistor for realizing chip various functions.
Each voltage domain 101-1,101-2......101-n to be powered be sequentially connected in series in system power supply VDD and
Systematically between GND.The ground terminal VSS1 of power end VDD1 connection the system power supply VDD, voltage domain 101-1 of voltage domain 101-1 connect
It is connected to the power end VDD2 of next stage voltage domain 101-2, the ground terminal VSS2 of voltage domain 101-2 is connected to next stage voltage domain
The power end VDD3 of 101-3, successively connects to next stage, and the ground terminal VSSn of voltage domain 101-n is connected to systematically GND.Thus
Form n voltage domain of series-fed, the power end of each voltage domain 101-1,101-2......101-n be respectively VDD1,
VDD2......VDDn, ground terminal are respectively VSS1, VSS2......VSSn.
Deep N-well 102-1,102-2......102-n is for realizing the isolation between different voltages domain.It is above-mentioned in addition to being formed
Series-fed access except, the utility model also divides system power supply VDD using p-well and/or the bulk resistor of N trap 106
Pressure generates partial pressure at the both ends of deep N-well 102-1,102-2......102-n.Wherein, the power end VPP1 of deep N-well 102-1 connects
It is connected to system power supply VDD, the ground terminal VBB1 of deep N-well 102-1 is connected to the power end VPP2 of next stage deep N-well 102-2, deep N-well
The ground terminal VBB2 of 102-2 is connected to the power end VPP3 of next stage deep N-well 102-3, successively connects to next stage；Deep N-well 102-
The ground terminal VBBn of n is connected to systematically GND.It is formed and is sequentially connected in series and two terminal potentials between system power supply VDD and ground GND
Metastable deep N-well, the power end of deep N-well 102-1,102-2......102-n be respectively VPP1,
VPP2......VPPn, ground terminal are respectively VBB1, VBB2......VBBn.
Ideally, power end VDD1, VDD2......VDDn of voltage domain 101-1,101-2......101-n
Voltage is identical as the voltage of power end VPP1, VPP2......VPPn of deep N-well 102-1,102-2......102-n respectively,
The voltage of ground terminal VSS1, VSS2......VSSn of voltage domain 101-1,101-2......101-n respectively with deep N-well 102-1,
The voltage of ground terminal VBB1, VBB2......VBBn of 102-2......102-n is identical.
In the present embodiment, the source terminal connection of the PMOS transistor in each voltage domain 101-1,101-2......101-n
To power end VDD1, VDD2......VDDn of the voltage domain, the substrate terminal of PMOS transistor is connected to deep N-well 102-1,102-
2......102-n power end VPP1, VPP2......VPPn；In each voltage domain 101-1,101-2......101-n
The source terminal of NMOS transistor is connected to ground terminal VSS1, VSS2......VSSn of the voltage domain, the substrate terminal of NMOS transistor
It is connected to ground terminal VBB1, VBB2......VBBn of deep N-well 102-1,102-2......102-n.
In addition, cascade electric power system 100 further includes switching transistor 105, switching transistor 105 in the piece of the utility model
For NMOS transistor, it is formed in voltage domain 101-2,101-3......101- (n-1).By taking voltage domain 101-2 as an example, voltage
The drain electrode end D of switching transistor 105 in the 101-2 of domain is connected to the power end VDD1 of upper level voltage domain 101-1, switchs crystal
The source terminal S of pipe 105 is connected to the power end VDD2 of the same level voltage domain 101-2, and the gate terminal G of switching transistor 105 is connected to
The power end VPP2 of the same level deep N-well 102-2, the substrate terminal B of switching transistor 105 are connected to the ground terminal of the same level deep N-well 102-2
VBB2。
The gate terminal G and substrate terminal B of switching transistor 105 are respectively connected to VPP2, VBB2, due to gate capacitance and lining
The influence of bottom body capacitance does not flow through electric current between grid and substrate, so that the current potential of VPP2 keeps stablizing.In ideal situation
Under, the voltage VPP2 of 105 gate terminal G of switching transistor is greater than the voltage VBB2 of substrate terminal B, and then forms conduction in the substrate
Channel.But since the voltage VDD1 of switching transistor drain electrode end D is greater than the voltage VPP2 of gate terminal G, the voltage of gate terminal G
VPP2 is identical as the voltage VDD2 of source terminal S, i.e. Vd> Vg=Vs, that is, Vgs=0, form conducting channel folder in the substrate
It is disconnected, there is no electric current to flow through between source terminal S and drain electrode end D.
When the power vd D2 electricity shortage of the same level voltage domain, the voltage of VDD2 declines, i.e. 105 source terminal of switching transistor
The voltage of S declines, and since the voltage VPP2 of gate terminal G is remained unchanged, then will form VgsThe state of > 0.Due to Vds> Vgs, when
Vgs=VthWhen, switching transistor 105 is opened and is worked in saturation region, at this point, switching transistor 105 source terminal S and drain electrode end D
Between electric current are as follows: IDS=[K* (W/L) * (Vgs-Vth)2]/2.At this point, the VDD1 of drain electrode end D gives the VDD2 of source terminal S
With sufficient charge supplement, the current potential of VDD2 be will be clamped in (VPP2-Vth), it can't further decrease.
Based on same reason, when the drain electrode end D of switching transistor 105 connects the ground terminal VSS1 in voltage order one domain, source electrode
When end S meets the ground terminal VSS2 of the same level voltage domain, so that it may clamp the current potential of the same level voltage domain VSS2 in (VSS2-Vth) range
It is interior.
Embodiment two
Fig. 5 is cascade electric power system schematic diagram in the piece of another embodiment of the utility model.As shown in figure 5, the present embodiment
It is that the type of switching transistor 105 ' and connection type are different from the difference of embodiment one.
In the present embodiment, cascade electric power system 100 equally includes switching transistor 105 ', switching transistor 105 ' in piece
For PMOS transistor, it is formed in voltage domain 101-2,101-3......101- (n-1).By taking voltage domain 101-2 as an example, voltage
The drain electrode end D of switching transistor 105 ' in the 101-2 of domain is connected to the ground terminal VSS3 of next stage voltage domain 101-3, switchs crystal
The source terminal S of pipe 105 ' is connected to the ground terminal VSS2 of the same level voltage domain 101-2, and the gate terminal G of switching transistor 105 ' is connected to
The ground terminal VBB2 of the same level deep N-well 102-2, the substrate terminal B of switching transistor 105 ' are connected to the power supply of the same level deep N-well 102-2
Hold VPP2.
The gate terminal G and substrate terminal B of switching transistor 105 ' are respectively connected to VBB2, VPP2, due to gate capacitance and
The influence of substrate body capacitance does not flow through electric current between grid and substrate, so that the current potential of VBB2, VPP2 keep stablizing.It is resonable
In the case of thinking, the voltage VBB2 of 105 ' gate terminal G of switching transistor is less than the voltage VPP2 of substrate terminal B, and then shape in the substrate
At conducting channel.But since the voltage VSS3 of 105 ' drain electrode end D of switching transistor is lower than the voltage VBB2 of gate terminal G, grid
The extreme voltage VSS2 of voltage VBB2 and source terminal S of G is identical, i.e. Vd> Vg=Vs, that is, Vgs=0, it is formed in the substrate
Conducting channel pinch off does not have electric current to flow through between source terminal S and drain electrode end D.
When the VSS2 of the same level voltage domain forms overcurrent, the current potential of VSS2 rises, i.e. 105 ' source terminal of switching transistor
The voltage of S increases, and since the voltage VBB2 of gate terminal G is remained unchanged, then will form VgsThe state of < 0.Switching transistor 105 '
Threshold voltage be Vth, due to Vds> Vgs, work as Vgs=VthWhen, switching transistor 105 ' is opened and is worked in saturation region, at this point,
Electric current between switching transistor 105 ' source terminal S and drain electrode end D are as follows: IDS=[K* (W/L) * (Vgs-Vth)2]/2.At this point, leakage
The VSS3 of poles D gives the VSS2 of source terminal S with sufficient charge discharging resisting, and the current potential of VSS2 will be clamped in (VSS2+Vth) model
In enclosing, can't further it increase.
Based on same reason, when the drain electrode end D of switching transistor 105 ' connects the power end VDD3 of next stage voltage domain, source
When extreme S meets the power end VDD2 of the same level voltage domain, so that it may clamp the current potential of the same level voltage domain power end VDD2 in (VDD2
+Vth) in range.
Embodiment three
It is a seed type that embodiment one and embodiment two, which illustrate only the switching transistor formed in same voltage domain,
It perhaps is that PMOS transistor or the situation for NMOS transistor in different situations can also be simultaneously in each voltage domain
PMOS transistor and NMOS transistor are formed as switching transistor.
Fig. 6 is cascade electric power system schematic diagram in the piece of another embodiment of the utility model.As shown in fig. 6, to be gone here and there in piece
For the m step voltage domain 101-m of alliance electric system 100, switching transistor 105 is formd in voltage domain 101-m and is opened
Close transistor 105 '.Wherein, switching transistor 105 is NMOS transistor, switching transistor in connection type and embodiment one
105 connection type is identical；Switching transistor 105 ' is PMOS transistor, switching transistor in connection type and embodiment two
105 ' connection type is identical.
Example IV
Embodiment three is shown is formed simultaneously a PMOS transistor and a NMOS transistor in same voltage domain
Situation as switching transistor.If one group of switching transistor 105,105 ' is only set, the circuit closed on when it occur compared with
When big curent change, it can compensate rapidly.But when compared with the circuit at distant positions high current variation occurs for distance, no
It can compensate in time, it is possible to the supply voltage of entire voltage domain occur as operating current generates variation, and then cause whole
The circuit cisco unity malfunction of a voltage domain.In actual design and production, the quantity of switching transistor can be set to
It is multiple.
Fig. 7 is cascade electric power system schematic diagram in the piece of the utility model another embodiment.As shown in fig. 7, series connection in piece
Multiple switch transistor 105,105 ' has been respectively formed in every voltage order one domain 101 of power supply system 100.
In every voltage order one domain 101 other than forming the region of necessary device, also there is certain spare area.In order to fast
Speed to close on circuit provide power supply compensate and improve power supply compensation ability, can the spare area in voltage domain 101 as far as possible
More formation switching transistors 105,105 ', particular number can be determined according to the size of spare area in voltage domain 101.Its
In, the multiple switch transistor 105,105 ' of formation both can uniformly arrange, and non-homogeneous can also arrange.
Embodiment five
In circuit real work, due to the conducting and/or closing of transistor, the bulk resistor of p-well and/or N trap will lead to
Change, so the voltage of power end VPP1, VPP2......VPPn of deep N-well 102-1,102-2......102-n with
And the voltage of ground terminal VBB1, VBB2......VBBn of deep N-well 102-1,102-2......102-n can also become therewith
Change.In order to guarantee the voltage of VPP1, VPP2......VPPn and the stabilization of VBB1, VBB2......VBBn voltage, need to protect
The bulk resistor for demonstrate,proving p-well and/or N trap keeps relative constant state, can be in the parallel connection of the both ends of p-well and/or N trap bulk resistor 106
One voltage regulation unit.
Fig. 8 is cascade electric power system schematic diagram in the piece containing voltage regulation unit of an embodiment of the present invention.Such as Fig. 8 institute
Show, by taking the m step voltage domain 101-m of cascade electric power system 100 in piece as an example, deep N-well 102-m power end VPPm and
One voltage regulation unit 107 of the both ends ground terminal VBBm parallel connection, that is, in a p-well bulk resistor both ends voltage regulation unit 107 in parallel, pressure stabilizing
Unit 107 can be one of resistance, capacitor and diode or a variety of.Voltage regulation unit 107 not necessarily, can two
End carries out choosing whether to connect by analog switch 108.
Embodiment six
In circuit practical work process, power end VDD1, VDD2......VDDn and ground terminal VSS1 of each voltage domain,
The voltage of VSS2......VSSn can change, and power end VPP1, VPP2......VPPn and ground terminal of deep N-well
The voltage of VBB1, VBB2......VBBn keep relative stability.Ideally the voltage at the end VDD1, VDD2......VDDn with
VPP1, VPP2......VPPn are identical, the voltage at the end VSS1, VSS2......VSSn and the electricity of VBB1, VBB2......VBBn
It presses identical.
Fig. 9 is cascade electric power system schematic diagram in the piece containing voltage regulation unit of the utility model another embodiment.Such as Fig. 9 institute
Show, equally by taking the m step voltage domain 101-m of cascade electric power system 100 in piece as an example, shown in embodiment shown in Fig. 9 and Fig. 8
The difference of embodiment is, is connected with an analog switch between the ground terminal VSSm of voltage domain 101-m and the ground terminal VBBm of deep N-well
108, it can determine whether be connected between VSSm and VBBm by being opened or closed for analog switch 108.
The utility model also provides a kind of Data Computation Unit, and Figure 10 is the utility model Data Computation Unit schematic diagram.
As shown in Figure 10, Data Computation Unit 700 includes control circuit 701, the computing circuit 702, storage circuit 703 that interconnection connects,
And cascade electric power system 100 in one or more pieces.
The utility model also provides a kind of chip, and Figure 11 is the utility model chip schematic diagram.As shown in Figure 11, chip
800 include control unit 801, and one or more Data Computation Units 700.Control unit 801 is to Data Computation Unit 700
Input data is simultaneously handled the data that Data Computation Unit 700 exports.
The utility model also provides a kind of calculation power plate, and Figure 12 is that the utility model calculates power plate schematic diagram.As shown in figure 12,
It includes on one or more chips 800 on power plate 900 that each, which is calculated, carries out Hash operation to the operational data that mine pond issues.
The utility model also provides a kind of calculating equipment, and the equipment that calculates is preferred for excavating the fortune of virtual digit currency
It calculates, certain calculating equipment can be used for other any magnanimity operations.Figure 13 is that the utility model calculates equipment schematic diagram.
As shown in figure 13, each calculating equipment 1000 includes connecting plate 1001, control panel 1002, radiator 1003, power panel 1004,
And one or more calculation power plates 900.Control panel 1002 is connect by connecting plate 1001 with power plate 900 is calculated, and radiator 1003 is set
It sets and is calculating around power plate 900.Power panel 1004 be used for the connecting plate 1001, control panel 1002, radiator 1003 and
It calculates power plate 900 and power supply is provided.
It should be noted that in the description of the present invention, term " transverse direction ", " longitudinal direction ", "upper", "lower", " preceding ",
The orientation or positional relationship of the instructions such as " rear ", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside" be based on
Orientation or positional relationship shown in the drawings, is merely for convenience of describing the present invention and simplifying the description, and is not instruction or dark
Show that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as pair
The limitation of the utility model.
It is not only in the description and the implementation although the embodiments of the present invention have been disclosed as above
Listed utilization, it can be applied to various fields suitable for the present invention completely, for those skilled in the art,
Other modifications may be easily implemented, therefore without departing from the general concept defined in the claims and the equivalent scope, this reality
It is not limited to specific details and legend shown and described herein with novel.
In other words, the utility model can also have other various embodiments, without departing substantially from the spirit of the present invention and its essence
In the case where, those skilled in the art work as can make various corresponding changes and modifications, but this according to the utility model
A little corresponding changes and modifications all should belong to the protection scope of the utility model the attached claims.
Claims (18)
1. a kind of interior cascade electric power system characterized by comprising
Two or more voltage domains to be powered, the voltage domain to be powered are connected in series between power supply and ground；
Two or more area of isolation, the voltage domain to be powered are formed in the area of isolation, the isolated area
Domain is for being isolated the voltage domain to be powered；
The area of isolation is connected in series between the power supply and the ground；
Power supply compensating unit is connected between the voltage domain to be powered and the area of isolation, is used for the electricity to be powered
Domain is pressed to provide power supply compensation；
It wherein, further include voltage regulation unit, the voltage regulation unit is connected in each area of isolation both ends in parallel.
2. cascade electric power system in piece as described in claim 1, it is characterised in that: the power supply compensating unit is existed by work
Saturation state provides power supply compensation to the voltage domain to be powered.
3. cascade electric power system in piece as claimed in claim 2, it is characterised in that: formed at each area of isolation both ends
First power end and the first ground terminal, first power end and/or first ground terminal to the power supply compensating unit for mentioning
Supply reference voltage.
4. cascade electric power system in piece as claimed in claim 3, it is characterised in that: at each voltage domain both ends to be powered
It forms second source end and the second ground terminal, the power supply compensating unit is mentioned to the second source end and/or second ground terminal
Power supply source compensation.
5. cascade electric power system in piece as claimed in claim 4, it is characterised in that: on the basis of the reference voltage, work as institute
It is described when stating the voltage change range of second source end and/or second ground terminal and being more than the threshold value of the power supply compensating unit
Power supply compensating unit works in the saturation state.
6. cascade electric power system in piece as claimed in claim 5, it is characterised in that: the power supply compensating unit is switch crystal
Pipe.
7. cascade electric power system in piece as claimed in claim 6, it is characterised in that: the switching transistor is that PMOS switch is brilliant
Body pipe and/or NMOS switch transistor.
8. cascade electric power system in piece as claimed in claim 7, it is characterised in that: the PMOS switch transistor and/or institute
NMOS switch transistor is stated as one or more.
9. cascade electric power system in piece as claimed in claim 8, it is characterised in that: be formed with one in the voltage domain to be powered
A or multiple semiconductor devices, first power end and/or first ground terminal are inclined to semiconductor devices offer substrate
Pressure.
10. cascade electric power system in piece as claimed in claim 9, it is characterised in that: the semiconductor devices includes PMOS crystalline substance
Body pipe and/or NMOS transistor, first power end to the PMOS transistor provide substrate bias, first ground terminal to
The NMOS transistor provides substrate bias.
11. cascade electric power system in piece as claimed in claim 4, it is characterised in that: the voltage regulation unit is for described in pressure stabilizing
The voltage of first power end and/or first ground terminal.
12. cascade electric power system in piece as claimed in claim 11, it is characterised in that: the voltage regulation unit includes resistance, electricity
Perhaps one of diode or a variety of.
13. cascade electric power system in piece as claimed in claim 12, it is characterised in that: the voltage regulation unit is connected directly between institute
It states between the first power end and first ground terminal, or first power end and institute is connected to by analog switch
It states between the first ground terminal.
14. cascade electric power system in piece as claimed in claim 13, it is characterised in that: in first ground terminal and described
One analog switch is set between two ground terminals.
15. a kind of Data Computation Unit, the control circuit connected including interconnection, computing circuit, storage circuit and one or more
Cascade electric power system in a piece, it is characterised in that: described interior cascade electric power system is any one institute in claim 1-14
Cascade electric power system in the piece stated.
16. a kind of chip, which is characterized in that including any one data operation list described at least one claim 15
Member.
17. a kind of for calculating the calculation power plate in equipment, which is characterized in that including any one described in multiple claims 16
The kind chip.
18. a kind of calculating equipment, including power panel, control panel, connecting plate, radiator and multiple calculation power plates, the control panel
It is connect by the connecting plate with the calculation power plate, the radiator is arranged in around the calculation power plate, and the power panel is used
In providing power supply to the connecting plate, the control panel, the radiator and the calculation power plate, wherein the calculation power plate is
Any one described calculation power plate described in claim 17.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821680948.6U CN209182771U (en) | 2018-10-16 | 2018-10-16 | On-chip series power supply system and arithmetic unit, chip, force computing board and computing equipment using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821680948.6U CN209182771U (en) | 2018-10-16 | 2018-10-16 | On-chip series power supply system and arithmetic unit, chip, force computing board and computing equipment using same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209182771U true CN209182771U (en) | 2019-07-30 |
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ID=67361489
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821680948.6U Active CN209182771U (en) | 2018-10-16 | 2018-10-16 | On-chip series power supply system and arithmetic unit, chip, force computing board and computing equipment using same |
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| Country | Link |
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| CN (1) | CN209182771U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020057180A1 (en) * | 2018-09-20 | 2020-03-26 | 北京嘉楠捷思信息技术有限公司 | On-chip passive power supply compensation circuit and operational unit applying same, and chip, hashboard and computing device |
| CN112256115A (en) * | 2020-09-21 | 2021-01-22 | 北京比特大陆科技有限公司 | Power supply circuit, chip and electronic equipment |
-
2018
- 2018-10-16 CN CN201821680948.6U patent/CN209182771U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020057180A1 (en) * | 2018-09-20 | 2020-03-26 | 北京嘉楠捷思信息技术有限公司 | On-chip passive power supply compensation circuit and operational unit applying same, and chip, hashboard and computing device |
| US11442517B2 (en) * | 2018-09-20 | 2022-09-13 | Canaan Creative Co., Ltd. | On-chip passive power supply compensation circuit and operation unit, chip, hash board and computing device using same |
| CN112256115A (en) * | 2020-09-21 | 2021-01-22 | 北京比特大陆科技有限公司 | Power supply circuit, chip and electronic equipment |
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