CN206195798U - Class lorenz chaotic circuit who contains two time -lag item - Google Patents

Abstract

The utility model provides a class lorenz chaotic circuit who contains two time -lag item, a channel circuit's output signal feeds back to a channel circuit's input, the preceding one -level signal of making channel circuit output signal skewing circuit module D1 and the skewing circuit module D2's among the 3rd channel circuit the incoming signal in as a channel circuit, this output signal still regards as the multiplier A2's among the 2nd channel circuit incoming signal and the multiplier A1's among the 3rd channel circuit incoming signal respectively, the 2nd channel circuit output signal's preceding one -level output signal is as a channel circuit's incoming signal, and as multiplier A1's among the 3rd channel circuit incoming signal, the 3rd channel circuit's output signal feeds back to the 3rd channel circuit's input, and the multiplier A2's among the 2nd channel circuit of conduct incoming signal. Circuit structure is simple, the modularization, and the circuit dependable performance is stable, has important reference value in fields such as chaos password, communication security and chaos anti -control.

Description

A kind of class Lorentz chaos circuit containing double time lag items

Technical field

The utility model belongs to chaos signal generator technical field, specifically a kind of class long-range navigation containing double time lag items Hereby chaos circuit.

Background technology

From 1963, since the famous scholar's Lorentz of Massachusetts Institute Technology proposes Lorentz chaotic system, people couple The structure of chaos attractor generates great interest.Then old pass honor, the expensive decile of Lv Jinhu, Liu Chongxin and Yang Qi be you can well imagine in succession Chen systems, LV systems, Liu systems, Yang-Chen systems etc. are gone out, then Guangdong University of Technology professor Yu Simin etc. is to mixed The construction method of ignorant circuit such as modularization, simplification, particularization are studied, and Xi'an Communications University professor Liu Chongxin etc. is to fraction The structure of rank chaos circuit has been also carried out researching and analysing, and the above is all based on chaos circuit for the discussion research of chaos circuit is The embodiment directly perceived of chaos system application practice.Chaotic signal has like spies such as random, the sensitiveness to initial value height, ergodics Property, therefore have and its be widely applied in the field such as secret communication and figure, word and video-encryption.In current research In chaos circuit, mainly based on classical chaos system of the integer rank without time lag item low-dimensional, but with the increasing of system complexity Plus so that chaos system type is more and more as added time lag item.The increase of time lag item further enriches chaos system type It is infinite dimension i.e. equivalent to system dimension, the chaotic characteristic of certain system is also just increasingly complex abundant, thus to containing time lag item Chaos system the fields such as chaos encryption, chaotic secret communication and anti-chaos controlling apply, it appears it is particularly important.

At present, the main application problem in Practical Project of research of chaos system, most straight in practical engineering application Connect the effective method i.e. design of chaos circuit and realize, design has the complicated chaotic circuit system containing time lag item, to close Key is one of important.If by the chaos system circuit containing time lag item be applied to teaching with communication in, on the one hand strengthen student To the intuitive of nonlinear chaotic system circuit design；On the other hand the secrecy in signals transmission is increased.

There is complicated time lag item circuit realiration and class Lorentz chaotic system and classical Lorentz system in above-mentioned prior art System, Chen systems etc. have the shortcomings that non-equivalence topology is difficult design and realizes.

The content of the invention

The utility model provides a kind of class Lorentz chaos circuit containing double time lag items, is used to solve of the prior art lacking Fall into.

The utility model is achieved by the following technical programs：

A kind of class Lorentz chaos circuit containing double time lag items, including first passage circuit, second channel circuit and the 3rd Channel circuit, the output signal of first passage circuit feeds back to the input of first passage circuit, as input signal all the way, the The previous stage signal of one channel circuit output signal is used as the time-lag network module D1 and third channel in first passage circuit The input signal of the time-lag network module D2 in circuit, the output signal is also respectively as the multiplier A2 in second channel circuit Input signal and third channel circuit in multiplier A1 input signal；The previous stage of second channel circuit output signal Output signal as first passage circuit input signal, and as the input signal of multiplier A1 in third channel circuit；The The output signal of triple channel circuit feeds back to the input of third channel circuit, and as the multiplier A2 in second channel circuit Input signal；

Described first passage circuit includes phase inverter U1, the 2 pin connecting resistance R11 of phase inverter U1, resistance R12, resistance The other end of R13 and circuit R14, resistance R11 connects the output signal of first passage, the other end connection second of resistance R12 The previous stage output signal of passage output, the output end of the other end connection time-lag network module D1 of resistance R13, resistance R14's 6 pins of other end connection phase inverter U1,6 pins of phase inverter U1 connect 2 pins of inverting integrator U3 by resistance R15； Electric capacity C1 one end connects 2 pins of inverting integrator U3, and 6 pins of the other end connection inverting integrator U3 of electric capacity C1 are anti-phase 6 pins of integrator U3 are connected to 2 pins of phase inverter U2 by resistance R16；The 2 pins connection resistance R17's of phase inverter U2 One end, 6 pins of the other end connection phase inverter U2 of resistance R17；3 pins of phase inverter U1,3 pins of the U2 of phase inverter with it is anti- The 3 pins ground connection of phase integral device U3；4 pins of 4 pins of phase inverter U1,4 pins of phase inverter U2 and inverting integrator U3 connect VDD（Negative voltage）, 7 pins of 7 pins of phase inverter U1,7 pins of phase inverter U2 and inverting integrator U3 meet VCC（Positive electricity Pressure）, the output end of the phase inverter U2 in first passage circuit is signal-x, and the inverting integrator U3's in first passage circuit is defeated It is signal x to go out end；

Described second channel circuit includes multiplier A2, and multiplier A2 output ends are by resistance R22 and phase inverter U4's Pin 2 is connected；One end of resistance R21 is connected with 2 pins of the U4 of phase inverter, the other end and the first passage circuit of resistance R21 The previous stage output signal connection of output, 2 pins of the U4 of phase inverter connect 6 pins of phase inverter U4 by resistance R23；It is anti-phase 6 pins of device U4 connect 2 pins of inverting integrator U6 by resistance R24, the 2 pins connection electric capacity C2's of inverting integrator U6 One end, 6 pins of the other end connection inverting integrator U6 of electric capacity C2；6 pins of inverting integrator U6 are connected by resistance R25 To 2 pins of phase inverter U5；2 pins connection resistance R26 one end of phase inverter U5, the 6 of resistance R26 other ends connection phase inverter U5 Pin, the 3 pins ground connection of 3 pins of phase inverter U4,3 pins of phase inverter U5 and inverting integrator U6；Draw the 4 of phase inverter U4 4 pins of pin, 4 pins of phase inverter U5 and inverting integrator U6 meet VDD（Negative voltage）, 7 pins of phase inverter U4, phase inverter U5 7 pins of 7 pins and inverting integrator U6 meet VCC（Positive voltage）, the output end letter of the phase inverter U5 in second channel circuit Number it is-y, the output end of the inverting integrator U6 in second channel circuit is signal y；

Described third channel circuit includes multiplier A1, and multiplier A1 output ends are by resistance R34 and the 2 of phase inverter U7 Pin, resistance R35 one end and resistance R40 connection, the resistance R35 other ends are connected with the output signal of third channel, resistance R40 Other end connection time-lag network module D2 output end, 2 pins of phase inverter U7 connect the 6 of phase inverter U7 by resistance R36 Pin；6 pins of phase inverter U7 connect 2 pins of inverting integrator U9 by resistance R37, and 2 pins of inverting integrator U9 connect Connect one end of electric capacity C3,6 pins of the other end connection inverting integrator U9 of electric capacity C3；6 pins of inverting integrator U9 pass through Resistance R38 is connected to 2 pins of phase inverter U8；2 pins connection resistance R39 one end of phase inverter U8, the connection of the resistance R39 other ends 6 pins of phase inverter U8；The 3 pins ground connection of 3 pins of phase inverter U7,3 pins of phase inverter U8 and inverting integrator U9；It is anti-phase 4 pins of 4 pins of device U7,4 pins of phase inverter U8 and inverting integrator U9 meet VDD（Negative voltage）, the 7 of phase inverter U7 draws 7 pins of pin, 7 pins of phase inverter U8 and inverting integrator U9 meet VCC（Positive voltage）, the phase inverter U8 in third channel circuit Output end signal be-z, the output end of inverting integrator U9 is signal z in third channel circuit；

Described time-lag network module D1 includes phase inverter U10, the 2 pin connecting resistance R1 of phase inverter U10, resistance R2, electricity The other end for hindering R1 is the input of time-lag network module D1, and 6 pins of the other end connection phase inverter U10 of resistance R2 are anti-phase 6 pins of device U10 connect one end of the first T-shaped LCL filter group by resistance R3, and the first T-shaped LCL filter group is by five T Type LCL filter is composed in series, other end connection resistance R4 and the resistance R5, the resistance R4 other ends of the first T-shaped LCL filter group Ground connection, 2 pins of the other end connection phase inverter U11 of resistance R5,2 pins of phase inverter U11 are connected to anti-phase by resistance R6 6 pins of device U11,6 pins of phase inverter U11 are also connected with resistance R7, and the other end of resistance R7 is the defeated of time-lag network module D1 Go out end, 3 pins of phase inverter U10 are grounded with 3 pins of phase inverter U11；4 pins of phase inverter U10 draw with the 4 of phase inverter U11 Pin meets VDD（Negative voltage）, 7 pins of phase inverter U10 and 7 pins of phase inverter U11 meet VCC（Positive voltage）；First T-shaped LCL filters Ripple device group is respectively the first T-shaped LCL filter, the second T-shaped LCL filter, the 3rd T-shaped LCL filter, the 4th T-shaped LCL filtering Device, the 5th T-shaped LCL filter, the first T-shaped LCL filter are made up of inductance L1, inductance L9 and electric capacity C7, the second T-shaped LCL filters Ripple device is made up of inductance L2, inductance L3 and electric capacity C8, and the 3rd T-shaped LCL filter is made up of inductance L4, inductance L5 and electric capacity C9, 4th T-shaped LCL filter is made up of inductance L6, inductance L7 and electric capacity C4, and the 5th T-shaped LCL filter is by inductance L8, inductance L10 Constituted with electric capacity C5, one end of resistance R3 inductance L9, one end, one end of electric capacity C7 of the other end connection inductance L1 of inductance L9, One end of the other end connection inductance L2 of inductance L1, one end, one end of electric capacity C8 of the other end connection inductance L3 of inductance L2, electricity Feel one end of the other end connection inductance L4 of L3, one end, one end of electric capacity C9, inductance of the other end connection inductance L5 of inductance L4 One end of the other end connection inductance L6 of L5, one end, one end of electric capacity C4 of the other end connection inductance L7 of inductance L6, inductance L7 Other end connection inductance L8 one end, one end, one end of electric capacity C5 of the other end connection inductance L10 of inductance L8, inductance L10 Other end connection connection resistance R4 and resistance R5, the other end of electric capacity C7, the other end of electric capacity C8, the other end of electric capacity C9, The other end of electric capacity C4 and the other end of electric capacity C5 are grounded；

Described time-lag network module D2 includes phase inverter U12, the 2 pin connecting resistance R41 of phase inverter U12, resistance R42, The other end of resistance R41 is the input of time-lag network module D2, and the other end of resistance R42 connects 6 pins of phase inverter U12, 6 pins of phase inverter U12 connect one end of the second T-shaped LCL filter group by resistance R43, the second T-shaped LCL filter group Other end connection connection resistance R44 and resistance R45, resistance R44 other ends ground connection, the other end connection phase inverter U13 of resistance R45 2 pins, 2 pins of phase inverter U13 are connected to 6 pins of phase inverter U13 by resistance R46, and 6 pins of phase inverter U13 are also The other end of connection resistance R47, resistance R47 is the output end of time-lag network module D2,3 pins and phase inverter of phase inverter U12 The 3 pins ground connection of U13；4 pins of phase inverter U12 meet VDD with 4 pins of phase inverter U13（Negative voltage）, the 7 of phase inverter U12 draws Pin meets VCC with 7 pins of phase inverter U13（Positive voltage）；Second T-shaped LCL filter group is respectively the 6th T-shaped LCL filter, Seven T-shaped LCL filters, the 8th T-shaped LCL filter, the 9th T-shaped LCL filter, the tenth T-shaped LCL filter, the 6th T-shaped LCL Wave filter is made up of inductance L11, inductance L19 and electric capacity C11, and the 7th T-shaped LCL filter is by inductance L12, inductance L13 and electric capacity C12 is constituted, and the 8th T-shaped LCL filter is made up of inductance L14, inductance L15 and electric capacity C19, and the 9th T-shaped LCL filter is by inductance L16, inductance L17 and electric capacity C14 are constituted, and the tenth T-shaped LCL filter is made up of inductance L18, inductance L20 and electric capacity C15, resistance One end of R443 inductance L19, one end, one end of electric capacity C11 of the other end connection inductance L11 of inductance L19, inductance L11's is another One end connects one end of inductance L12, one end, one end of electric capacity C12 of the other end connection inductance L13 of inductance L12, inductance L13 Other end connection inductance L14 one end, one end, one end of electric capacity C19, inductance of the other end connection inductance L15 of inductance L14 One end of the other end connection inductance L16 of L15, one end, one end of electric capacity C14 of the other end connection inductance L17 of inductance L16, One end of the other end connection inductance L18 of inductance L17, one end, the one of electric capacity C15 of the other end connection inductance L20 of inductance L18 End, other end connection connection resistance R44 and the resistance R45, the other end of electric capacity C11, the other end of electric capacity C12, electricity of inductance L20 The other end for holding the other end, the other end of electric capacity C14 and electric capacity C15 of C19 is grounded.

A kind of class Lorentz chaos circuit containing double time lag items as described above, it is described phase inverter U1, phase inverter U2, anti- It is phase integral device U3, phase inverter U4, phase inverter U5, inverting integrator U6, phase inverter U7, phase inverter U8, inverting integrator U9, anti-phase Device U10, phase inverter U11, phase inverter U12 and phase inverter U11 use transport and placing device LM741.

A kind of class Lorentz chaos circuit containing double time lag items as described above, described multiplier A1, multiplier A2 is adopted Use multiplier AD633.

A kind of class Lorentz chaos circuit containing double time lag items as described above, resistance in described first passage circuit R11=R12=33k Ω, R13=R14=R16=R17=10K Ω, R15=1K Ω, electric capacity C1=100nF；Resistance in second channel circuit R21=23K Ω, R22=5.1K Ω, R23=R25=R26=10K Ω, R24=10K Ω, electric capacity C2=100nF；In third channel circuit Resistance R34=R36==R37=R38=R39=10KR37=1K Ω, R37=1K Ω, electric capacity C3=100nF, VCC=15, VDD=-15V.

A kind of class Lorentz chaos circuit containing double time lag items as described above, resistance in described time-lag network module D1 R1=R2=R3=R4=R5=R6=R7=10K Ω, electric capacity C6=C7=C8=C4=C5=4 μ F, inductance L1=L2=L3=L4=L5=L6=20mF, Inductance L7=L8=L9=L10=20mF, VCC=15, VDD=-15V.

A kind of class Lorentz chaos circuit containing double time lag items as described above, D2 resistance in described time-lag network module R41=R42=R3=R44=R45=R46=R47=10K Ω, electric capacity C11=C12=C13=C14=C15=4 μ F, inductance L11=L12=L13= L14=L15=10mF, L16=10mF, inductance L7=L8=L9=L10=10mF, VCC=15, VDD=-15V.

The utility model has the advantages that：It is of the present utility model that in oscillograph X-Y patterns, just observable goes out x-y, x-z, y-z phase Figure, circuit performance is reliable and stable, and circuit structure is simple and easily realizes, it is adaptable to university's nonlinear circuit experimental teaching and demonstration Realize etc., there is important construction value in the fields such as chaos encryption, secret communication and chaos applications.

Brief description of the drawings

In order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art, below will be to embodiment Or the accompanying drawing to be used needed for description of the prior art is briefly described, it should be apparent that, drawings in the following description are Some embodiments of the present utility model, for those of ordinary skill in the art, are not paying the premise of creative labor Under, other accompanying drawings can also be obtained according to these accompanying drawings.

Fig. 1 is circuit diagram of the present utility model；Fig. 2 is time-lag network module D1 circuit diagrams；Fig. 3 is time-lag network module D2 Circuit diagram；Fig. 4 is the x output waveform figures of Fig. 1；Fig. 5 is the y output waveform figures of Fig. 1；Fig. 6 is the z output waveform figures of Fig. 1；Fig. 7 It is the x-y output phasors of Fig. 1；Fig. 8 is the x-z output phasors of Fig. 1；Fig. 9 is the y-z output phasors of Fig. 1.

Specific embodiment

It is new below in conjunction with this practicality to make the purpose, technical scheme and advantage of the utility model embodiment clearer Accompanying drawing in type embodiment, is clearly and completely described, it is clear that retouched to the technical scheme in the utility model embodiment The embodiment stated is a part of embodiment of the utility model, rather than whole embodiments.Based on the implementation in the utility model Example, the every other embodiment that those of ordinary skill in the art are obtained under the premise of creative work is not made is belonged to The scope of the utility model protection.

A kind of class Lorentz chaos circuit containing double time lag items, includes first passage circuit, second channel electricity as shown in Figure 1 Road and third channel circuit, the output signal of first passage circuit feeds back to the input of first passage circuit, used as defeated all the way Enter signal, the previous stage signal of first passage circuit output signal as the time-lag network module D1 in first passage circuit and The input signal of the time-lag network module D2 in third channel circuit, the output signal is also respectively as in second channel circuit The input signal of the multiplier A1 in the input signal and third channel circuit of multiplier A2；Second channel circuit output signal Previous stage output signal as first passage circuit input signal, and as the input of multiplier A1 in third channel circuit Signal；The output signal of third channel circuit feeds back to the input of third channel circuit, and as in second channel circuit The input signal of multiplier A2；

Described first passage circuit includes phase inverter U1, the 2 pin connecting resistance R11 of phase inverter U1, resistance R12, resistance The other end of R13 and circuit R14, resistance R11 connects the output signal of first passage, the other end connection second of resistance R12 The previous stage output signal of passage output, the output end of the other end connection time-lag network module D1 of resistance R13, resistance R14's 6 pins of other end connection phase inverter U1,6 pins of phase inverter U1 connect 2 pins of inverting integrator U3 by resistance R15； Electric capacity C1 one end connects 2 pins of inverting integrator U3, and 6 pins of the other end connection inverting integrator U3 of electric capacity C1 are anti-phase 6 pins of integrator U3 are connected to 2 pins of phase inverter U2 by resistance R16；The 2 pins connection resistance R17's of phase inverter U2 One end, 6 pins of the other end connection phase inverter U2 of resistance R17；3 pins of phase inverter U1,3 pins of the U2 of phase inverter with it is anti- The 3 pins ground connection of phase integral device U3；4 pins of 4 pins of phase inverter U1,4 pins of phase inverter U2 and inverting integrator U3 connect VDD（Negative voltage）, 7 pins of 7 pins of phase inverter U1,7 pins of phase inverter U2 and inverting integrator U3 meet VCC（Positive electricity Pressure）, the output end of the phase inverter U2 in first passage circuit is signal-x, and the inverting integrator U3's in first passage circuit is defeated It is signal x to go out end；

Described second channel circuit includes multiplier A2, and multiplier A2 output ends are by resistance R22 and phase inverter U4's Pin 2 is connected；One end of resistance R21 is connected with 2 pins of the U4 of phase inverter, the other end and the first passage circuit of resistance R21 The previous stage output signal connection of output, 2 pins of the U4 of phase inverter connect 6 pins of phase inverter U4 by resistance R23；It is anti-phase 6 pins of device U4 connect 2 pins of inverting integrator U6 by resistance R24, the 2 pins connection electric capacity C2's of inverting integrator U6 One end, 6 pins of the other end connection inverting integrator U6 of electric capacity C2；6 pins of inverting integrator U6 are connected by resistance R25 To 2 pins of phase inverter U5；2 pins connection resistance R26 one end of phase inverter U5, the 6 of resistance R26 other ends connection phase inverter U5 Pin, the 3 pins ground connection of 3 pins of phase inverter U4,3 pins of phase inverter U5 and inverting integrator U6；Draw the 4 of phase inverter U4 4 pins of pin, 4 pins of phase inverter U5 and inverting integrator U6 meet VDD（Negative voltage）, 7 pins of phase inverter U4, phase inverter U5 7 pins of 7 pins and inverting integrator U6 meet VCC（Positive voltage）, the output end letter of the phase inverter U5 in second channel circuit Number it is-y, the output end of the inverting integrator U6 in second channel circuit is signal y；

Described third channel circuit includes multiplier A1, and multiplier A1 output ends are by resistance R34 and the 2 of phase inverter U7 Pin, resistance R35 one end and resistance R40 connection, the resistance R35 other ends are connected with the output signal of third channel, resistance R40 Other end connection time-lag network module D2 output end, 2 pins of phase inverter U7 connect the 6 of phase inverter U7 by resistance R36 Pin；6 pins of phase inverter U7 connect 2 pins of inverting integrator U9 by resistance R37, and 2 pins of inverting integrator U9 connect Connect one end of electric capacity C3,6 pins of the other end connection inverting integrator U9 of electric capacity C3；6 pins of inverting integrator U9 pass through Resistance R38 is connected to 2 pins of phase inverter U8；2 pins connection resistance R39 one end of phase inverter U8, the connection of the resistance R39 other ends 6 pins of phase inverter U8；The 3 pins ground connection of 3 pins of phase inverter U7,3 pins of phase inverter U8 and inverting integrator U9；It is anti-phase 4 pins of 4 pins of device U7,4 pins of phase inverter U8 and inverting integrator U9 meet VDD（Negative voltage）, the 7 of phase inverter U7 draws 7 pins of pin, 7 pins of phase inverter U8 and inverting integrator U9 meet VCC（Positive voltage）, the phase inverter U8 in third channel circuit Output end signal be-z, the output end of inverting integrator U9 is signal z in third channel circuit；

As shown in figure 3, described time-lag network module D1 include phase inverter U10, the 2 pin connecting resistance R1 of phase inverter U10, The other end of resistance R2, resistance R1 is the input of time-lag network module D1, the 6 of the other end connection phase inverter U10 of resistance R2 Pin, 6 pins of phase inverter U10 connect one end of the first T-shaped LCL filter group, the first T-shaped LCL filter by resistance R3 Group is composed in series by five T-shaped LCL filters, the other end connection resistance R4 and resistance R5 of the first T-shaped LCL filter group, electricity Resistance R4 other end ground connection, 2 pins of the other end connection phase inverter U11 of resistance R5,2 pins of phase inverter U11 pass through resistance R6 6 pins of phase inverter U11 are connected to, 6 pins of phase inverter U11 are also connected with resistance R7, and the other end of resistance R7 is time-lag network The output end of module D1,3 pins of phase inverter U10 are grounded with 3 pins of phase inverter U11；4 pins of phase inverter U10 with it is anti-phase 4 pins of device U11 meet VDD（Negative voltage）, 7 pins of phase inverter U10 and 7 pins of phase inverter U11 meet VCC（Positive voltage）；The One T-shaped LCL filter group is respectively the first T-shaped LCL filter, the second T-shaped LCL filter, the 3rd T-shaped LCL filter, the 4th T-shaped LCL filter, the 5th T-shaped LCL filter, the first T-shaped LCL filter are made up of inductance L1, inductance L9 and electric capacity C7, the Two T-shaped LCL filters are made up of inductance L2, inductance L3 and electric capacity C8, and the 3rd T-shaped LCL filter is by inductance L4, inductance L5 and electricity Hold C9 compositions, the 4th T-shaped LCL filter is made up of inductance L6, inductance L7 and electric capacity C4, and the 5th T-shaped LCL filter is by inductance L8, inductance L10 and electric capacity C5 are constituted, one end of resistance R3 inductance L9, one end, the electric capacity of the other end connection inductance L1 of inductance L9 One end of C7, one end of the other end connection inductance L2 of inductance L1, one end, the electric capacity C8 of the other end connection inductance L3 of inductance L2 One end, one end of the other end connection inductance L4 of inductance L3, one end of the other end connection inductance L5 of inductance L4, electric capacity C9 One end, one end of the other end connection inductance L6 of inductance L5, one end, the one of electric capacity C4 of the other end connection inductance L7 of inductance L6 End, one end of the other end connection inductance L8 of inductance L7, one end, the one of electric capacity C5 of the other end connection inductance L10 of inductance L8 End, other end connection connection resistance R4 and the resistance R5, the other end of electric capacity C7, the other end of electric capacity C8, electric capacity C9 of inductance L10 The other end of the other end, the other end of electric capacity C4 and electric capacity C5 be grounded；

As shown in figure 3, described time-lag network module D2 includes phase inverter U12, the 2 pin connecting resistances of phase inverter U12 R41, resistance R42, the other end of resistance R41 is the input of time-lag network module D2, the other end connection phase inverter of resistance R42 6 pins of U12,6 pins of phase inverter U12 connect one end of the second T-shaped LCL filter group, the second T-shaped LCL by resistance R43 The other end connection connection resistance R44 and resistance R45 of wave filter group, resistance R44 other ends ground connection, the other end of resistance R45 connects 2 pins of phase inverter U13 are connect, 2 pins of phase inverter U13 are connected to 6 pins of phase inverter U13, phase inverter by resistance R46 6 pins of U13 are also connected with resistance R47, and the other end of resistance R47 is the output end of time-lag network module D2, the 3 of phase inverter U12 Pin is grounded with 3 pins of phase inverter U13；4 pins of phase inverter U12 meet VDD with 4 pins of phase inverter U13（Negative voltage）, instead 7 pins of phase device U12 meet VCC with 7 pins of phase inverter U13（Positive voltage）；It is T-shaped that second T-shaped LCL filter group is respectively the 6th LCL filter, the 7th T-shaped LCL filter, the 8th T-shaped LCL filter, the 9th T-shaped LCL filter, the tenth T-shaped LCL filtering Device, the 6th T-shaped LCL filter is made up of inductance L11, inductance L19 and electric capacity C11, the 7th T-shaped LCL filter by inductance L12, Inductance L13 and electric capacity C12 is constituted, and the 8th T-shaped LCL filter is made up of inductance L14, inductance L15 and electric capacity C19, and the 9th is T-shaped LCL filter is made up of inductance L16, inductance L17 and electric capacity C14, and the tenth T-shaped LCL filter is by inductance L18, inductance L20 and electricity Hold C15 compositions, one end of resistance R443 inductance L19, one end, the one of electric capacity C11 of the other end connection inductance L11 of inductance L19 End, one end of the other end connection inductance L12 of inductance L11, one end, the electric capacity C12 of the other end connection inductance L13 of inductance L12 One end, one end of the other end connection inductance L14 of inductance L13, one end, the electric capacity of the other end connection inductance L15 of inductance L14 One end of C19, one end of the other end connection inductance L16 of inductance L15, one end of the other end connection inductance L17 of inductance L16, One end of electric capacity C14, one end of the other end connection inductance L18 of inductance L17, the one of the other end connection inductance L20 of inductance L18 End, one end of electric capacity C15, other end connection connection resistance R44 and the resistance R45, the other end of electric capacity C11, electric capacity of inductance L20 The other end of the other end of C12, the other end of electric capacity C19, the other end of electric capacity C14 and electric capacity C15 is grounded.

Described phase inverter U1, phase inverter U2, inverting integrator U3, phase inverter U4, phase inverter U5, inverting integrator U6, Phase inverter U7, phase inverter U8, inverting integrator U9, phase inverter U10, phase inverter U11, phase inverter U12 and phase inverter U11 are used Transport and placing device LM741.

Described multiplier A1, multiplier A2 uses multiplier AD633.

Resistance R11=R12=33k Ω, R13=R14=R16=R17=10K Ω, R15=1K Ω in described first passage circuit, Electric capacity C1=100nF；Resistance R21=23K Ω, R22=5.1K Ω, R23=R25=R26=10K Ω, R24=10K in second channel circuit Ω, electric capacity C2=100nF；Resistance R34=R36==R37=R38=R39=10KR37=1K Ω, R37=1K Ω in third channel circuit, Electric capacity C3=100nF, VCC=15, VDD=-15V.

Resistance R1=R2=R3=R4=R5=R6=R7=10K Ω, electric capacity C6=C7=C8=C4=in described time-lag network module D1 C5=4 μ F, inductance L1=L2=L3=L4=L5=L6=20mF, inductance L7=L8=L9=L10=20mF, VCC=15, VDD=-15V.

D2 resistance R41=R42=R3=R44=R45=R46=R47=10K Ω, electric capacity C11=in described time-lag network module C12=C13=C14=C15=4 μ F, inductance L11=L12=L13=L14=L15=10mF, L16=10mF, inductance L7=L8=L9=L10= 10mF, VCC=15, VDD=-15V.

Operation principle of the present utility model is：The chaotic characteristic of the nonlinear circuit enriches complexity very much, if this is exported Signal is modulated as carrier signal with echo signal by related algorithm, can reach surely secret communication, it is anti-crack, image, word And the purpose such as video-encryption.Involved dimensionless Mathematical Modeling is as follows：

（1）

Formula（1）In, x, y, z are state variable, and a, b, c, τ are the parameter of equation, choose a=3, b=1, c=9, τ 1=2, τ 2=1 When, system（1）I.e. containing the class Lorentz chaotic system of double time lag items, now the equation of oscillating circuit of the present utility model is：

（2）

Circuit involved by the utility model includes first, second, third channel circuit, first, second, third passage electricity Road timesharing realizes formula（2）In first, second, third function, analog multiplier use AD633 when, the output waveform of circuit Figure is shown in Fig. 4, Fig. 5, Fig. 6, and the phasor of circuit output is shown in Fig. 7, Fig. 8, Fig. 9, and the long-range navigation containing double time lag item classes has been reflected on figure The hereby chaotic characteristic of circuit, the chaos attractor for being drawn has good ergodic and enriches the type of chaos, is that chaos should Sound assurance is provided for image encryption, mechanical-electric coupling control system and the anti-solution that cracks.

Finally it should be noted that：Above example is only used to illustrate the technical solution of the utility model, rather than its limitations； Although being described in detail to the utility model with reference to the foregoing embodiments, it will be understood by those within the art that： It can still modify to the technical scheme described in foregoing embodiments, or which part technical characteristic is carried out etc. With replacement；And these modifications or replacement, the essence of appropriate technical solution is departed from each embodiment technology of the utility model The spirit and scope of scheme.

Claims (6)

1. a kind of class Lorentz chaos circuit containing double time lag items, it is characterised in that：Including first passage circuit, second channel electricity Road and third channel circuit, the output signal of first passage circuit feeds back to the input of first passage circuit, used as defeated all the way Enter signal, the previous stage signal of first passage circuit output signal as the time-lag network module D1 in first passage circuit and The input signal of the time-lag network module D2 in third channel circuit, the output signal is also respectively as in second channel circuit The input signal of the multiplier A1 in the input signal and third channel circuit of multiplier A2；Second channel circuit output signal Previous stage output signal as first passage circuit input signal, and as the input of multiplier A1 in third channel circuit Signal；The output signal of third channel circuit feeds back to the input of third channel circuit, and as in second channel circuit The input signal of multiplier A2；Described first passage circuit include phase inverter U1, the 2 pin connecting resistance R11 of phase inverter U1, Resistance R12, resistance R13 and circuit R14, the other end of resistance R11 connect the output signal of first passage, and resistance R12's is another The previous stage output signal of one end connection second channel output, the output of the other end connection time-lag network module D1 of resistance R13 End, 6 pins of the other end connection phase inverter U1 of resistance R14,6 pins of phase inverter U1 connect anti-phase integration by resistance R15 2 pins of device U3；Electric capacity C1 one end connects 2 pins of inverting integrator U3, the other end connection inverting integrator U3 of electric capacity C1 6 pins, 6 pins of inverting integrator U3 are connected to 2 pins of phase inverter U2 by resistance R16；2 pins of phase inverter U2 connect One end of connecting resistance R17,6 pins of the other end connection phase inverter U2 of resistance R17；3 pins of phase inverter U1, the U2 of phase inverter 3 pins of 3 pins and inverting integrator U3 be grounded；4 pins of phase inverter U1,4 pins of phase inverter U2 and inverting integrator 4 pins of U3 meet VDD（Negative voltage）, 7 pins of 7 pins of phase inverter U1,7 pins of phase inverter U2 and inverting integrator U3 connect VCC（Positive voltage）, the output end of the phase inverter U2 in first passage circuit is signal-x, the anti-phase integration in first passage circuit The output end of device U3 is signal x；Described second channel circuit includes multiplier A2, and multiplier A2 output ends pass through resistance R22 It is connected with the pin 2 of phase inverter U4；One end of resistance R21 is connected with 2 pins of the U4 of phase inverter, the other end of resistance R21 with The previous stage output signal connection of first passage circuit output, 2 pins of the U4 of phase inverter connect phase inverter U4 by resistance R23 6 pins；6 pins of phase inverter U4 connect 2 pins of inverting integrator U6,2 pins of inverting integrator U6 by resistance R24 One end of connection electric capacity C2,6 pins of the other end connection inverting integrator U6 of electric capacity C2；6 pins of inverting integrator U6 lead to Cross 2 pins that resistance R25 is connected to phase inverter U5；2 pins connection resistance R26 one end of phase inverter U5, the resistance R26 other ends connect Connect 6 pins of phase inverter U5, the 3 pins ground connection of 3 pins of phase inverter U4,3 pins of phase inverter U5 and inverting integrator U6；Instead 4 pins of 4 pins of phase device U4,4 pins of phase inverter U5 and inverting integrator U6 meet VDD（Negative voltage）, the 7 of phase inverter U4 draws 7 pins of pin, 7 pins of phase inverter U5 and inverting integrator U6 meet VCC（Positive voltage）, the phase inverter U5 in second channel circuit Output end signal be-y, the output end of the inverting integrator U6 in second channel circuit is signal y；Described third channel Circuit includes multiplier A1, and multiplier A1 output ends pass through 2 pins, resistance R35 one end and the electricity of resistance R34 and phase inverter U7 Resistance R40 connections, the resistance R35 other ends are connected with the output signal of third channel, the other end connection time-lag network mould of resistance R40 The output end of block D2,2 pins of phase inverter U7 connect 6 pins of phase inverter U7 by resistance R36；6 pins of phase inverter U7 lead to 2 pins of resistance R37 connection inverting integrators U9 are crossed, 2 pins of inverting integrator U9 connect one end of electric capacity C3, electric capacity C3's 6 pins of other end connection inverting integrator U9；6 pins of inverting integrator U9 are connected to the 2 of phase inverter U8 by resistance R38 Pin；2 pins connection resistance R39 one end of phase inverter U8,6 pins of resistance R39 other ends connection phase inverter U8；Phase inverter U7 3 pins, 3 pins of phase inverter U8 and inverting integrator U9 3 pins ground connection；4 pins of phase inverter U7, the 4 of phase inverter U8 Pin meets VDD with 4 pins of inverting integrator U9（Negative voltage）, 7 pins of phase inverter U7,7 pins of phase inverter U8 with it is anti-phase 7 pins of integrator U9 meet VCC（Positive voltage）, the output end signal of the phase inverter U8 in third channel circuit is-z, threeway The output end of inverting integrator U9 is signal z in road circuit；Described time-lag network module D1 includes phase inverter U10, phase inverter The 2 pin connecting resistance R1 of U10, resistance R2, the other end of resistance R1 is the input of time-lag network module D1, and resistance R2's is another End connects 6 pins of phase inverter U10, and 6 pins of phase inverter U10 connect the one of the first T-shaped LCL filter group by resistance R3 End, the first T-shaped LCL filter group is composed in series by five T-shaped LCL filters, and the other end of the first T-shaped LCL filter group connects Connecting resistance R4 and resistance R5, resistance R4 other ends ground connection, 2 pins of the other end connection phase inverter U11 of resistance R5, phase inverter 2 pins of U11 are connected to 6 pins of phase inverter U11 by resistance R6, and 6 pins of phase inverter U11 are also connected with resistance R7, resistance The other end of R7 is the output end of time-lag network module D1, and 3 pins of phase inverter U10 are grounded with 3 pins of phase inverter U11；Instead 4 pins of phase device U10 meet VDD with 4 pins of phase inverter U11（Negative voltage）, 7 pins of phase inverter U10 and the 7 of phase inverter U11 Pin meets VCC（Positive voltage）；First T-shaped LCL filter group be respectively the first T-shaped LCL filter, the second T-shaped LCL filter, 3rd T-shaped LCL filter, the 4th T-shaped LCL filter, the 5th T-shaped LCL filter, the first T-shaped LCL filter by inductance L1, Inductance L9 and electric capacity C7 is constituted, and the second T-shaped LCL filter is made up of inductance L2, inductance L3 and electric capacity C8, the 3rd T-shaped LCL filtering Device is made up of inductance L4, inductance L5 and electric capacity C9, and the 4th T-shaped LCL filter is made up of inductance L6, inductance L7 and electric capacity C4, the Five T-shaped LCL filters are made up of inductance L8, inductance L10 and electric capacity C5, one end of resistance R3 inductance L9, the other end of inductance L9 One end, one end of electric capacity C7 of connection inductance L1, one end of the other end connection inductance L2 of inductance L1, the other end of inductance L2 connects Connect one end, one end of electric capacity C8 of inductance L3, one end of the other end connection inductance L4 of inductance L3, the other end connection of inductance L4 One end of inductance L5, one end of electric capacity C9, one end of the other end connection inductance L6 of inductance L5, the other end connection electricity of inductance L6 Feel one end, one end of electric capacity C4 of L7, one end of the other end connection inductance L8 of inductance L7, the other end connection inductance of inductance L8 One end of L10, one end of electric capacity C5, the other end connection connection resistance R4 and resistance R5 of inductance L10, the other end of electric capacity C7, The other end of the other end of electric capacity C8, the other end of electric capacity C9, the other end of electric capacity C4 and electric capacity C5 is grounded；When described Stagnant circuit module D2 includes phase inverter U12, the 2 pin connecting resistance R41 of phase inverter U12, resistance R42, and the other end of resistance R41 is The input of time-lag network module D2,6 pins of the other end connection phase inverter U12 of resistance R42,6 pins of phase inverter U12 lead to Cross one end that resistance R43 connects the second T-shaped LCL filter group, the other end connection connection resistance of the second T-shaped LCL filter group R44 and resistance R45, resistance R44 other ends ground connection, 2 pins of the other end connection phase inverter U13 of resistance R45, phase inverter U13 2 pins 6 pins of phase inverter U13 are connected to by resistance R46,6 pins of phase inverter U13 are also connected with resistance R47, resistance The other end of R47 is the output end of time-lag network module D2, and 3 pins of phase inverter U12 are grounded with 3 pins of phase inverter U13；Instead 4 pins of phase device U12 meet VDD with 4 pins of phase inverter U13（Negative voltage）, 7 pins of phase inverter U12 and the 7 of phase inverter U13 Pin meets VCC（Positive voltage）；Second T-shaped LCL filter group be respectively the 6th T-shaped LCL filter, the 7th T-shaped LCL filter, 8th T-shaped LCL filter, the 9th T-shaped LCL filter, the tenth T-shaped LCL filter, the 6th T-shaped LCL filter by inductance L11, Inductance L19 and electric capacity C11 is constituted, and the 7th T-shaped LCL filter is made up of inductance L12, inductance L13 and electric capacity C12, and the 8th is T-shaped LCL filter is made up of inductance L14, inductance L15 and electric capacity C19, and the 9th T-shaped LCL filter is by inductance L16, inductance L17 and electricity Hold C14 compositions, the tenth T-shaped LCL filter is made up of inductance L18, inductance L20 and electric capacity C15, the one of resistance R443 inductance L19 End, one end, one end of electric capacity C11 of the other end connection inductance L11 of inductance L19, the other end connection inductance L12 of inductance L11 One end, one end, one end of electric capacity C12 of the other end connection inductance L13 of inductance L12, the other end connection inductance of inductance L13 One end of L14, one end, one end of electric capacity C19 of the other end connection inductance L15 of inductance L14, the other end connection of inductance L15 One end of inductance L16, one end, one end of electric capacity C14 of the other end connection inductance L17 of inductance L16, the other end of inductance L17 One end of connection inductance L18, one end, one end of electric capacity C15 of the other end connection inductance L20 of inductance L18, inductance L20's is another The other end of one end connection connection resistance R44 and resistance R45, electric capacity C11, the other end of electric capacity C12, the other end of electric capacity C19, The other end of electric capacity C14 and the other end of electric capacity C15 are grounded.

2. a kind of class Lorentz chaos circuit containing double time lag items according to claim 1, it is characterised in that：Described is anti- Phase device U1, phase inverter U2, inverting integrator U3, phase inverter U4, phase inverter U5, inverting integrator U6, phase inverter U7, phase inverter U8, inverting integrator U9, phase inverter U10, phase inverter U11, phase inverter U12 and phase inverter U11 use transport and placing device LM741.

3. a kind of class Lorentz chaos circuit containing double time lag items according to claim 1, it is characterised in that：Described multiplies Musical instruments used in a Buddhist or Taoist mass A1, multiplier A2 use multiplier AD633.

4. a kind of class Lorentz chaos circuit containing double time lag items according to claim 1, it is characterised in that：Described Resistance R11=R12=33k Ω, R13=R14=R16=R17=10K Ω, R15=1K Ω, electric capacity C1=100nF in one channel circuit；The Resistance R21=23K Ω, R22=5.1K Ω, R23=R25=R26=10K Ω, R24=10K Ω, electric capacity C2=in two channel circuits 100nF；Resistance R34=R36==R37=R38=R39=10KR37=1K Ω, R37=1K Ω, electric capacity C3=in third channel circuit 100nF, VCC=15, VDD=-15V.

5. a kind of class Lorentz chaos circuit containing double time lag items according to claim 1, it is characterised in that：When described Resistance R1=R2=R3=R4=R5=R6=R7=10K Ω in stagnant circuit module D1, electric capacity C6=C7=C8=C4=C5=4 μ F, inductance L1=L2 =L3=L4=L5=L6=20mF, inductance L7=L8=L9=L10=20mF, VCC=15, VDD=-15V.

6. a kind of class Lorentz chaos circuit containing double time lag items according to claim 1, it is characterised in that：When described D2 resistance R41=R42=R3=R44=R45=R46=R47=10K Ω in stagnant circuit module, electric capacity C11=C12=C13=C14=C15=4 μ F, inductance L11=L12=L13=L14=L15=10mF, L16=10mF, inductance L7=L8=L9=L10=10mF, VCC=15, VDD=- 15V。