CN204537190U - The high smart card being highly resistant to DPA and attacking of security performance - Google Patents
The high smart card being highly resistant to DPA and attacking of security performance Download PDFInfo
- Publication number
- CN204537190U CN204537190U CN201520081844.3U CN201520081844U CN204537190U CN 204537190 U CN204537190 U CN 204537190U CN 201520081844 U CN201520081844 U CN 201520081844U CN 204537190 U CN204537190 U CN 204537190U
- Authority
- CN
- China
- Prior art keywords
- input end
- output terminal
- type flip
- flip flop
- dpa
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Storage Device Security (AREA)
Abstract
The utility model discloses the high smart card being highly resistant to DPA and attacking of a kind of security performance, it comprises embedded microprocessor, tandom number generator and the random number between microprocessor and tandom number generator consume circuit, the output terminal that random number consumes the amplifier of circuit connects the input end of comparer and the input end of voltage controlled oscillator simultaneously, the output terminal of comparer is connected with the input end of shift register with the second d type flip flop simultaneously, the output terminal of shift register is connected with the input end of code translator, the output terminal of code translator is connected with the input end of voltage controlled oscillator, the output terminal of voltage controlled oscillator is connected with the input end of frequency divider, output terminal one end of frequency divider is connected with the input end of the first d type flip flop, and the other end is connected with the trigger end of first, second d type flip flop simultaneously, the output terminal of first, second d type flip flop is connected with the input end of XOR gate.The utility model can resist the attack of DPA, and security performance is high.
Description
Technical field
The utility model relates to a kind of smart card, is specifically related to the high smart card being highly resistant to DPA and attacking of a kind of security performance.
Background technology
Smart card has characteristic that is light and safety, and the applications such as the safety control that the Secure Payments on network, network connect and Electronic Signature are played an important role.China has the secret information that many information security application systems are come needed for memory system running by smart card, and the computing power elevator system safety utilizing smart card to have, smart card just progressively replaces magnetic card and is widely used in finance and other related industries.Along with the development of the attack method to smart card, particularly deliver along with many novel attack smart card techniques are in recent years disclosed, the safety of smart card faces huge challenge.Wherein, differential power consumption analysis (Differential Power Analysis, DPA) be exactly a kind of effectively Attacks method, it mainly extracts the information relevant with key by statistical method, implementation procedure more complicated, DPA to the successful attack of inline cryptographic algorithm relevant in smart card by wide coverage.Smart card be a kind of can the open platform architecture of down load application program after hair fastener, so in order to prevent pseudo-card and protection holder, smart card must have high security and high reliability.
Utility model content
The utility model overcomes the deficiencies in the prior art, provides a kind of security performance the high smart card being highly resistant to DPA and attacking, the high attack being highly resistant to DPA of the security performance of this smart card.
For solving above-mentioned technical matters, the utility model by the following technical solutions:
The high smart card being highly resistant to DPA and attacking of a kind of security performance, the tandom number generator that it comprises embedded microprocessor and is connected with embedded microprocessor, it is characterized in that: be connected with random number between described microprocessor and tandom number generator and consume circuit, described random number consumes circuit and comprises amplifier, comparer, shift register, code translator, voltage controlled oscillator, frequency divider and first, second d type flip flop, wherein the output terminal of amplifier connects the input end of comparer and the input end of voltage controlled oscillator simultaneously, the output terminal of comparer is connected with the input end of shift register with the second d type flip flop simultaneously, the output terminal of shift register is connected with the input end of code translator, the output terminal of code translator is connected with the input end of voltage controlled oscillator, the output terminal of voltage controlled oscillator is connected with the input end of frequency divider, output terminal one end of frequency divider is connected with the input end of the first d type flip flop, and the other end is connected with the trigger end of first, second d type flip flop simultaneously, the output terminal of first, second d type flip flop is connected with the input end of XOR gate.
Further technical scheme is:
The input end of described amplifier connects between the resistances, the other end ground connection of a resistance.
DPA for smart card attacks, when mainly to utilize on card embedded microprocessor running, the execution of certain specific instruction or data access institute consumed power, on supply-voltage source show the useful information that specific current spectrum provides.Therefore can cause extra current drain by additional extra circuit, thus change current spectrum is attacked to reach anti-DPA.Simultaneously extra current consuming circuit by the mode adopting random number random, must produce random number current sinking, to reach the unpredictable property of chip power consumption, makes it can not be analyzed with statistics.Consume in circuit in this random number, when the noise voltage of resistance noise generation is after amplifier, comparer, produce " 1 " or " 0 " digital signal, stored in shift register, value in such register is the random number that produces of similar chaos formula RNG, this random number, after code translator coding, controls the discharge and recharge number of tri-state discharge and recharge impact damper, finally reaches the object controlling current drain with random number.
Compared with prior art, the beneficial effects of the utility model are: circuit of the present utility model adds a random number and consumes circuit, reaches the object controlling current drain with random number, effectively can resist the attack of DPA, improve its security.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
Fig. 1 is the structural representation of smart card of the present utility model.
Fig. 2 is the circuit diagram that random number of the present utility model consumes circuit.
Embodiment
Below in conjunction with accompanying drawing, the utility model is further described.Embodiment of the present utility model includes but not limited to the following example.
Embodiment
The high smart card being highly resistant to DPA and attacking of a kind of security performance as shown in Figure 1, the tandom number generator that it comprises embedded microprocessor and is connected with embedded microprocessor, be connected with random number between microprocessor and tandom number generator and consume circuit, random number consumes circuit and comprises amplifier, comparer, shift register, code translator, voltage controlled oscillator, frequency divider and first, second d type flip flop, wherein the output terminal of amplifier connects the input end of comparer and the input end of voltage controlled oscillator simultaneously, the output terminal of comparer is connected with the input end of shift register with the second d type flip flop simultaneously, the output terminal of shift register is connected with the input end of code translator, the output terminal of code translator is connected with the input end of voltage controlled oscillator, the output terminal of voltage controlled oscillator is connected with the input end of frequency divider, output terminal one end of frequency divider is connected with the input end of the first d type flip flop, and the other end is connected with the trigger end of first, second d type flip flop simultaneously, the output terminal of first, second d type flip flop is connected with the input end of XOR gate.The input end of amplifier connects between the resistances, the other end ground connection of a resistance.
Whole random number consumes circuit and comprises amplifier, comparer, shift register, code translator, voltage controlled oscillator, frequency divider and first, second d type flip flop, when the noise voltage of resistance noise generation is after amplifier, comparer, produce " 1 " or " 0 " digital signal, stored in shift register, value in such register is the random number that produces of similar chaos formula RNG, this random number is after code translator coding, control the discharge and recharge number of tri-state discharge and recharge impact damper, finally reach the object controlling current drain with random number.
According to the above embodiments, well the utility model can be completed.
Be embodiment of the present utility model as mentioned above.The utility model is not limited to above-mentioned embodiment, and anyone should learn the structure change made under enlightenment of the present utility model, and every have identical or close technical scheme with the utility model, all falls within protection domain of the present utility model.
Claims (2)
1. the high smart card being highly resistant to DPA and attacking of security performance, the tandom number generator that it comprises embedded microprocessor and is connected with embedded microprocessor, it is characterized in that: be connected with random number between described microprocessor and tandom number generator and consume circuit, described random number consumes circuit and comprises amplifier, comparer, shift register, code translator, voltage controlled oscillator, frequency divider and first, second d type flip flop, wherein the output terminal of amplifier connects the input end of comparer and the input end of voltage controlled oscillator simultaneously, the output terminal of comparer is connected with the input end of shift register with the second d type flip flop simultaneously, the output terminal of shift register is connected with the input end of code translator, the output terminal of code translator is connected with the input end of voltage controlled oscillator, the output terminal of voltage controlled oscillator is connected with the input end of frequency divider, output terminal one end of frequency divider is connected with the input end of the first d type flip flop, and the other end is connected with the trigger end of first, second d type flip flop simultaneously, the output terminal of first, second d type flip flop is connected with the input end of XOR gate.
2. the high smart card being highly resistant to DPA and attacking of security performance according to claim 1, is characterized in that: the input end of described amplifier connects between the resistances, the other end ground connection of a resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520081844.3U CN204537190U (en) | 2015-02-05 | 2015-02-05 | The high smart card being highly resistant to DPA and attacking of security performance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520081844.3U CN204537190U (en) | 2015-02-05 | 2015-02-05 | The high smart card being highly resistant to DPA and attacking of security performance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204537190U true CN204537190U (en) | 2015-08-05 |
Family
ID=53751163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520081844.3U Expired - Fee Related CN204537190U (en) | 2015-02-05 | 2015-02-05 | The high smart card being highly resistant to DPA and attacking of security performance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204537190U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104616054A (en) * | 2015-02-05 | 2015-05-13 | 成都市宏山科技有限公司 | Intelligent card with high security |
-
2015
- 2015-02-05 CN CN201520081844.3U patent/CN204537190U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104616054A (en) * | 2015-02-05 | 2015-05-13 | 成都市宏山科技有限公司 | Intelligent card with high security |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Bi et al. | Tunnel FET current mode logic for DPA-resilient circuit designs | |
| CN105227176B (en) | A kind of mixed type PUF circuits | |
| Choi et al. | Symmetric adiabatic logic circuits against differential power analysis | |
| CN104168264A (en) | Low-cost high-security physical unclonable function | |
| CN102880840A (en) | Current type physical unclonable function circuit for defending attack | |
| Liu et al. | Sequence triggered hardware trojan in neural network accelerator | |
| CN106385316B (en) | PUF is fuzzy to extract circuit and method | |
| CN104459519A (en) | Chip safety testing method and device | |
| CN204537190U (en) | The high smart card being highly resistant to DPA and attacking of security performance | |
| CN104616054A (en) | Intelligent card with high security | |
| CN107994980A (en) | It is a kind of using the out of order technology of clock and the anti-DPA attack methods of chaos trigger | |
| CN102110206B (en) | Method for defending attack and device with attack defending function | |
| Nguyen et al. | Extraction of device fingerprints using built-in erase-suspend operation of flash memory devices | |
| Gao et al. | A novel approximate computing based security primitive for the Internet of Things | |
| KR101332376B1 (en) | logic circuit for prevention DPA using of Hamming Weight Model, and smart card included it | |
| WO2023035689A1 (en) | True random number generator based on digital feedback self-calibration system on chip | |
| Yu et al. | ResNet‐based Trojan detection methodology for protected ICs | |
| Yu | Hardware trojan attacks on voltage scaling‐based side‐channel attack countermeasure | |
| Cao et al. | An authentication strategy based on spatiotemporal chaos for software copyright protection | |
| Meshram et al. | Security in embedded systems: Vulnerabilities pigeonholing of attacks and countermeasures | |
| CN101436929B (en) | Dot computation method capable of resisting simple current drain aggression | |
| CN105513641B (en) | A kind of safety protective circuit | |
| CN104657680A (en) | In-chip template attack resisting data transmission method | |
| CN105656629A (en) | Secure non-adjacent form realization method in chip | |
| Li et al. | FPGA implementation of AES algorithm resistant power analysis attacks |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150805 Termination date: 20160205 |