CN204029815U - Lateral symmetry DMOS pipe - Google Patents
Lateral symmetry DMOS pipe Download PDFInfo
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- CN204029815U CN204029815U CN201420455558.4U CN201420455558U CN204029815U CN 204029815 U CN204029815 U CN 204029815U CN 201420455558 U CN201420455558 U CN 201420455558U CN 204029815 U CN204029815 U CN 204029815U
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Abstract
Lateral symmetry DMOS pipe, comprises and possesses the epitaxial loayer of the first doping type and be positioned at two active areas that possess the second doping type on epitaxial loayer, and top, active area is provided with the active area metal electrode with active area ohmic contact; It between two active areas, is the drift region with the second doping type, middle part, drift region is for having the channel region of the first doping type, described drift region and top, channel region are insulating barrier and cover, on insulating barrier, be distributed with grid and secondary grid, lay respectively at channel region and top, drift region, on described secondary grid, there is lead-in wire connecting hole.Lateral symmetry DMOS pipe described in the utility model, can attract electric charge transoid below secondary grid by apply positive voltage at assistant grid, reduce the conducting resistance of DMOS pipe, when using as electrostatic protection device, secondary grid can be connected to increase gate leakage capacitance with grid, improve gate charge coupling speed, help device fast open to open.
Description
Technical field
The utility model belongs to field of semiconductor manufacture, relates to the Design and manufacture of high pressure DMOS pipe, particularly relates to a kind of lateral symmetry DMOS pipe.
Background technology
DMOS is dual diffusion MOSFET(double-Diffused MOSFET) abbreviation, because DMOS adopts the drift region of shallow injection, bear high pressure, so the withstand voltage properties of DMOS source between leaking is increased dramatically; DMOS mainly contains two types, vertical double-diffusion metal-oxide-semiconductor field effect transistor VDMOSFET(vertical double-diffused MOSFET) and lateral double diffusion metal oxide semiconductor field effect transistor LDMOSFET(lateral double-dif fused MOSFET).
DMOS break-over of device resistance refers to when device is worked, from draining to the resistance in source.For LDMOS device, should reduce as far as possible conducting resistance.When conducting resistance is very little, device will provide a good switching characteristic, because little conducting resistance between drain-source has larger output current, thereby can have stronger driving force.
Simultaneously, the existing electrostatic discharge protection circuit at chip pin place adopts power device conventionally, diode for example, triode, CMOS and SCR device form, wherein adopt the exemplary embodiment of CMOS or triode as shown in Figure 1, the grid of P or NMOS pipe, source electrode and substrate link together and electrostatic leakage line, normally in integrated circuit (IC) chip, the power line of main use or ground wire connect, drain electrode is connected with guarded pin, when static comes interim, due to electrostatic pulse hf and hv pulse normally, by the parasitic capacitance CGD between metal-oxide-semiconductor grid and drain electrode, high-voltage pulse is coupled to metal-oxide-semiconductor grid, metal-oxide-semiconductor gate voltage is changed, metal-oxide-semiconductor conducting, thereby by static from the drain terminal source of releasing.
For the DMOS in high-pressure process, withstand voltage due between need to adopting drift region to design to leak with increase source, the polysilicon lead pitch of grid is increased from drain electrode distance, parasitic capacitance CGD capacitance is very little, in above-mentioned electrostatic defending process, drain electrode ESD voltage is difficult to be coupled to grid, electrostatic protection effect variation.
Utility model content
For improving conduction property and the high frequency characteristics of lateral DMOS pipe, the utility model discloses a kind of lateral symmetry DMOS pipe.
Lateral symmetry DMOS pipe described in the utility model, comprises and possesses the epitaxial loayer of the first doping type and be positioned at two active areas that possess the second doping type on epitaxial loayer, top, active area is provided with the active area metal electrode with active area ohmic contact; It between two active areas, is the drift region with the second doping type, middle part, drift region is for having the channel region of the first doping type, described drift region and top, channel region are insulating barrier and cover, on insulating barrier, be distributed with grid and secondary grid, lay respectively at channel region and top, drift region, on described secondary grid, there is lead-in wire connecting hole.
Preferably, secondary grid and grid on described two active areas are arranged in parallel, and secondary grid are positioned at grid both sides, and the termination of two secondary grid connects so that metal connecting line is corresponding.
Preferably, top, described active area is provided with metal silicide layer near drift region one side.
Preferably, described grid is the polysilicon that type is identical with thickness with secondary grid.
Preferably, described secondary grid are the metal electrode identical with active area metal electrode.
Preferably, also comprise that the described active area of next-door neighbour is away from the substrate electric potential district that possesses the first doping type of drift region.
Concrete, described the first doping type and the second doping type are respectively P type and N-type.
Concrete, described the first doping type and the second doping type are respectively N-type and P type.
Lateral symmetry DMOS pipe described in the utility model, can attract electric charge transoid below secondary grid by apply positive voltage at assistant grid, reduce the conducting resistance of DMOS pipe, when using as electrostatic protection device, secondary grid can be connected to increase gate leakage capacitance with grid, improve gate charge coupling speed, help device fast open to open.
Accompanying drawing explanation
Fig. 1 is a kind of embodiment structural representation of lateral symmetry DMOS pipe described in the utility model;
Fig. 2 is a kind of embodiment schematic diagram of the utility model grid and secondary grid distribution form;
In figure, Reference numeral name is called: 3-substrate electric potential district, 1-epitaxial loayer 2-active area 5-active area, 4-channel region metal electrode, the secondary grid of 6-, 7-grid 8-insulating barrier 9-metal connecting line 10-metal silicide layer.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described in further detail.
As shown in Figure 1, lateral symmetry DMOS pipe described in the utility model, comprise and possess the epitaxial loayer 1 of the first doping type and be positioned at two active areas 2 that possess the second doping type on epitaxial loayer, top, active area is provided with the active area metal electrode 5 with active area ohmic contact; It between two active areas, is the drift region with the second doping type, middle part, drift region is for having the channel region 4 of the first doping type, described drift region and top, channel region are insulating barrier 8 and cover, on insulating barrier, be distributed with grid 7 and secondary grid 6, lay respectively at channel region and top, drift region, on described secondary grid, there is lead-in wire connecting hole.
Described the first doping type and the second doping type be P and N or N and P type semiconductor respectively, as lateral symmetry DMOS, manage, during normal work, at grid and two active areas, apply operating voltage, one of two active area is as source electrode, another is as drain electrode, when grid applies grid voltage, the channel region charge carrier transoid of grid below, form inversion-layer channel, the epitaxial loayer between channel region and active area due to doping content low and above there is no grid voltage, resistivity is larger, but charge carrier still can get over from channel region to active area 2, make conducting between the leakage of source.
Epitaxial loayer between channel region and active area is drift region, and secondary grid are positioned at top, drift region, by apply positive voltage on secondary grid, can attract electronics on surface, drift region by positive voltage, increase electron concentration, reduce drift zone resistance rate, thereby reduce conducting resistance.When as ESD electrostatic protection device, secondary grid are connected by metal with grid, increase the area between grid, dwindle active area and gate distance, thereby gate leakage capacitance is increased, drain electrode electrostatic charge is more easily coupled to grid, impels device to trigger sooner or opens more thoroughly, reaches the object of bleed off electrostatic induced current.Be close to described active area away from possessing of the drift region substrate electric potential district identical with epitaxial loayer doping type, consistent with substrate electric potential during use, next-door neighbour active area arranges and is beneficial to the anti-breech lock performance that improves device.
For further increasing gate leakage capacitance, can also above surfaces of active regions, near drift region one side, by deposit or other modes, generate metal silicide layer 10, such as tungsten silicide etc., because the resistivity of metal silicide is extremely low, at 10E-7 Europe/rice, relatively original doped semiconductor surface, has improved drain surface Electric Field Distribution, has improved grid to the parasitic capacitance CGD between drain electrode.
Secondary grid can be the polycrystalline silicon material identical with grid or the metal electrode identical with active area metal electrode, can synchronously once generate and need not add extra step with corresponding structure during fabrication.
Provided as shown in Figure 2 a kind of embodiment of grid and secondary grid distribution form, secondary grid 6 on two active areas are arranged in parallel with grid 7, secondary grid are positioned at grid both sides, the termination of two secondary grid connects so that metal connecting line 9 is corresponding, and secondary grid form an integral body, and two secondary grid current potentials are identical, being beneficial to drift zone resistance rate equates, improve the CURRENT DISTRIBUTION uniformity of device, when as ESD or the use of relatively high power device, improved the electric force lines distribution of device.
Previously described is each preferred embodiment of the present utility model, preferred implementation in each preferred embodiment is if not obviously contradictory or take a certain preferred implementation as prerequisite, each preferred implementation arbitrarily stack combinations is used, design parameter in described embodiment and embodiment is only the utility model proof procedure for clear statement utility model people, not in order to limit scope of patent protection of the present utility model, scope of patent protection of the present utility model is still as the criterion with its claims, the equivalent structure that every utilization specification of the present utility model and accompanying drawing content are done changes, in like manner all should be included in protection range of the present utility model.
Claims (8)
1. lateral symmetry DMOS manages, it is characterized in that, comprise and possess the epitaxial loayer (1) of the first doping type and be positioned at two active areas (2) that possess the second doping type on epitaxial loayer, top, active area is provided with the active area metal electrode (5) with active area ohmic contact; It between two active areas, is the drift region with the second doping type, middle part, drift region is for having the channel region (4) of the first doping type, described drift region and top, channel region are insulating barrier (8) and cover, on insulating barrier (8), be distributed with grid (7) and secondary grid (6), lay respectively at channel region and top, drift region, on described secondary grid, there is lead-in wire connecting hole.
2. lateral symmetry DMOS pipe as claimed in claim 1, is characterized in that, the secondary grid (6) on described two active areas are arranged in parallel with grid (7), and secondary grid (6) are positioned at grid (7) both sides, and the termination of two secondary grid connects so that metal connecting line (9) is corresponding.
3. lateral symmetry DMOS pipe as claimed in claim 1, is characterized in that, described active area (2) top is provided with metal silicide layer (10) near drift region one side.
4. lateral symmetry DMOS pipe as claimed in claim 1, is characterized in that, described grid is the polysilicon that type is identical with thickness with secondary grid.
5. lateral symmetry DMOS pipe as claimed in claim 1, is characterized in that, described secondary grid are the metal electrode identical with active area metal electrode.
6. lateral symmetry DMOS pipe as claimed in claim 1, is characterized in that, also comprises that the described active area of next-door neighbour (2) is away from the substrate electric potential district (3) that possesses the first doping type of drift region.
7. lateral symmetry DMOS pipe as claimed in claim 1, is characterized in that, described the first doping type and the second doping type are respectively P type and N-type.
8. lateral symmetry DMOS pipe as claimed in claim 1, is characterized in that, described the first doping type and the second doping type are respectively N-type and P type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420455558.4U CN204029815U (en) | 2014-08-13 | 2014-08-13 | Lateral symmetry DMOS pipe |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420455558.4U CN204029815U (en) | 2014-08-13 | 2014-08-13 | Lateral symmetry DMOS pipe |
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| CN204029815U true CN204029815U (en) | 2014-12-17 |
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| CN201420455558.4U Active CN204029815U (en) | 2014-08-13 | 2014-08-13 | Lateral symmetry DMOS pipe |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104201204A (en) * | 2014-08-13 | 2014-12-10 | 四川广义微电子股份有限公司 | Transverse symmetrical DMOS (double diffusion metal-oxide-semiconductor) pipe and manufacture method thereof |
-
2014
- 2014-08-13 CN CN201420455558.4U patent/CN204029815U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104201204A (en) * | 2014-08-13 | 2014-12-10 | 四川广义微电子股份有限公司 | Transverse symmetrical DMOS (double diffusion metal-oxide-semiconductor) pipe and manufacture method thereof |
| CN104201204B (en) * | 2014-08-13 | 2015-06-17 | 四川广义微电子股份有限公司 | Manufacture method for transverse symmetrical DMOS (double diffusion metal-oxide-semiconductor) pipe |
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