CN208422922U - A kind of groove grid super node semiconductor devices optimizing switching speed - Google Patents
A kind of groove grid super node semiconductor devices optimizing switching speed Download PDFInfo
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- CN208422922U CN208422922U CN201820448797.5U CN201820448797U CN208422922U CN 208422922 U CN208422922 U CN 208422922U CN 201820448797 U CN201820448797 U CN 201820448797U CN 208422922 U CN208422922 U CN 208422922U
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Abstract
The utility model relates to a kind of groove grid super node semiconductor devices for optimizing switching speed, it is characterized by: being equipped with gate oxide in the gate groove, Gate Electrode Conductive polysilicon layer is covered in the groove that the gate oxide is formed, insulating oxide is covered on the Gate Electrode Conductive polysilicon layer, source conductive polysilicon, the source conductive polysilicon and the source metal Ohmic contact being covered on the first interarea of semiconductor substrate are filled in the groove that insulating oxide is formed；The Gate Electrode Conductive polysilicon and source conductive polysilicon that the utility model is isolated by the way that mutually insulated is arranged in gate groove, it is effectively increased device input capacitance Ciss, thereby reduce the switching speed dV/dt of device, improve the EMI performance of system, while the device making method and existing semiconductor technology compatibility.
Description
Technical field
The utility model relates to a kind of groove grid super node semiconductor devices, especially a kind of trench gate for optimizing switching speed
Super-junction semiconductor device belongs to field of semiconductor manufacture.
Background technique
In mesohigh power semiconductor field, super-junction structure (Super Junction) has been widely adopted, right
Than conventional power MOSFET element, super-junction structure MOSFET element can obtain the folding of more excellent device pressure resistance and conducting resistance
Middle relationship.
As shown in Figure 1, being existing groove grid super node structure MOSFET element, super-junction structure is formed in semiconductor devices
In epitaxial layer, the super-junction structure being formed in the epitaxial layer includes N conductivity type columns (N column) and P conductivity type columns (P column), N
Column replaces with P column be provided adjacent to made of multiple P-N columns to formed super-junction structure.N column has N conductive type impurity, and P column has
P conductive type impurity, and the impurity level of N column and the impurity level of P column are consistent.When the MOSFET element with super-junction structure is cut
When only, N column and P column in super-junction structure are depleted respectively, and depletion layer extends from the P-N junction interface of each N column and P intercolumniation, by
It is equal in the impurity level in the impurity level and P column in N column, therefore depletion layer extension and completely depleted N column and P column, to prop up
Holder part pressure resistance；When break-over of device, since the resistivity of superjunction devices epitaxial layer is lower, so the conducting resistance of superjunction devices
It can be greatly lowered compared with commonplace components.
During devices switch, due in super-junction structure P column and N column only need lower drain voltage (Vds) just
It can exhaust respectively, cause the more common VDMOS of dV/dt during devices switch obviously bigger than normal.Further, since super node MOSFET chip
Area is small by 50% or so compared with the common VDMOS of same specification, has been further exacerbated by the increase of dV/dt in switching process, that is, has increased device
The switching speed of part.In practical applications, the increase of dV/dt will lead to higher due to voltage spikes, and it is dry to increase system electromagnetic radiation
Disturb EMI.
In the practical application of super node MOSFET, for the size of dV/dt during reduction devices switch, devices switch is reduced
Speed generally can increase the modes such as discrete resistance, capacitor, but the increasing of these peripheral devices using on super node MOSFET periphery
Add, will lead to the rising of entire cost of manufacture, while can also reduce system reliability.
Summary of the invention
The purpose of the utility model is to overcome the deficiencies in the prior art, provide a kind of groove for optimizing switching speed
Grid super-junction semiconductor device, the device by gate groove be provided with mutually insulated Gate Electrode Conductive polysilicon and source conductive
Polysilicon is effectively increased device input capacitance Ciss, thereby reduces the switching speed dV/dt of device, improves system
EMI performance.
To realize the above technical purpose, the technical solution of the utility model is: a kind of trench gate optimizing switching speed is super
Junction-semiconductor device, including cellular region and terminal protection area, the cellular region are located at the center of device, the terminal protection area
It is looped around around the cellular region, the cellular region includes semiconductor substrate, and the semiconductor substrate includes the first conductive-type
Type substrate and in the first conductivity type substrate and the first adjacent conductive type epitaxial layer, the first conduction type extension
The upper surface of layer is the first interarea of semiconductor substrate, and the lower surface of first conductivity type substrate is the of semiconductor substrate
Two interareas；
Several super-junction structures are provided in first conductive type epitaxial layer, the super-junction structure is by the first conduction type
Column and the second conductivity type columns are arranged alternately, and first conductivity type columns and the second conductivity type columns are along the first interarea
Extend to the direction of the second interarea；
The second conductivity type body region is equipped in the second conductivity type columns in the first conductive type epitaxial layer, and second leads
Electric type body region is set in the first conductive type epitaxial layer, and the first conduction type source is equipped in second conductivity type body region
Area, gate groove is equipped between second conductivity type body region, and the first conduction type source region is arranged in the second conduction type
The two sides in body area, and it is adjacent with gate groove, insulating medium layer is covered on the gate groove, it is characterised in that: the gate groove
It is interior to be equipped with gate oxide, it is covered with Gate Electrode Conductive polysilicon layer in the groove that the gate oxide is formed, the Gate Electrode Conductive is more
It is covered with insulating oxide on crystal silicon layer, is filled with source conductive polysilicon, the source electrode in the groove that insulating oxide is formed
Conductive polycrystalline silicon and the source metal Ohmic contact being covered on the first interarea of semiconductor substrate.
Further, for N-type super-junction semiconductor device, first conduction type is that N-type is conductive, and described second is conductive
Type is P-type conduction；For p-type super-junction semiconductor device, first conduction type is P-type conduction, second conductive-type
Type is that N-type is conductive.
Further, the Gate Electrode Conductive polysilicon layer with a thickness of 0.5 μm ~ 1 μm.
Further, the insulating oxide with a thickness of 500A ~ 1000A.
Further, it is isolated between the Gate Electrode Conductive polysilicon and source metal by insulating medium layer, the grid
It is isolated between conductive polycrystalline silicon and source conductive polysilicon by insulating oxide.
Further, the source metal and the second conductivity type body region, the first conduction type source region Ohmic contact, partly lead
Drain metal, the drain metal and the first conductivity type substrate Ohmic contact are provided on second interarea of structure base board.
Further, the super-junction semiconductor device is MOS device or IGBT device.
From the above, it can be seen that the utility model has the beneficial effects that:
1) the Gate Electrode Conductive polycrystalline being isolated in Superjunction semiconductor device structure by the way that mutually insulated is arranged in gate groove
Silicon and source conductive polysilicon, and make source conductive polysilicon and source metal Ohmic contact, device can be effectively increased in this way
Input capacitance Ciss, thereby reduce the dV/dt of devices switch process, reduce influence of the device to system EMI；
2) formation process of the utility model device and the manufacturing process of existing semiconductor devices are completely compatible.
Detailed description of the invention
Attached drawing 1 is the schematic cross-sectional view of prior art groove grid super node device cellular region.
Attached drawing 2 is the schematic diagram of the section structure of the utility model groove grid super node device cellular region.
Description of symbols: the 001-the first interarea；002-the second interarea；01-the first conductivity type substrate；02-the
One conductive type epitaxial layer；03-the first conductivity type columns；04-the second conduction type type column；05-the second conduction type body
Area；06-the first conduction type source region；07-gate groove；08-gate oxide；09-Gate Electrode Conductive polysilicon；10-insulation are situated between
Matter layer；11-source metals；12-source conductive polysilicons；13-insulating oxides；14-drain metals.
Specific embodiment
Below with reference to specific drawings and examples, the utility model is described in further detail.
As shown in Fig. 2, by taking N-type trench gate super-junction semiconductor device as an example, first conduction type is led for N-type
Electricity, second conduction type are P-type conduction；A kind of groove grid super node semiconductor devices optimizing switching speed, including cellular
Area and terminal protection area, the cellular region are located at the center of device, and the terminal protection area is looped around the week of the cellular region
It encloses, the cellular region includes semiconductor substrate, and the semiconductor substrate includes the first conductivity type substrate 01 and leads positioned at first
In electric type substrates 01 and the first adjacent conductive type epitaxial layer 02, the upper surface of first conductive type epitaxial layer 02 is
First interarea 001 of semiconductor substrate, the lower surface of first conductivity type substrate 01 are the second interarea of semiconductor substrate
002；
Several super-junction structures are provided in first conductive type epitaxial layer 02, the super-junction structure is by the first conductive-type
Type column 03 and the second conductivity type columns 04 are arranged alternately, 04 edge of first conductivity type columns 03 and the second conductivity type columns
The first interarea 001 to the direction of the second interarea 002 extend；
The second conductivity type body region 05 is equipped in the second conductivity type columns 04 in the first conductive type epitaxial layer 02, and
Second conductivity type body region 05 is set in the first conductive type epitaxial layer 02, is equipped with first in second conductivity type body region 05
Conduction type source region 06 is equipped with gate groove 07, the first conduction type source region 06 between second conductivity type body region 05
The two sides of second conductivity type body region 05 are set, and adjacent with gate groove 07, are covered with dielectric on the gate groove 07
Layer 10, it is characterised in that: be equipped with gate oxide 08 in the gate groove 07, be covered in the groove that the gate oxide 08 is formed
Gate Electrode Conductive polysilicon layer 09 is covered with insulating oxide 13,13 shape of insulating oxide on the Gate Electrode Conductive polysilicon layer 09
At groove in be filled with source conductive polysilicon 12, the source conductive polysilicon 12 with to be covered on semiconductor substrate first main
11 Ohmic contact of source metal on face 001.
The Gate Electrode Conductive polysilicon layer 09 with a thickness of 0.5 μm ~ 1 μm.
The insulating oxide 13 with a thickness of 500A ~ 1000A.
It is isolated between the Gate Electrode Conductive polysilicon 09 and source metal 11 by insulating medium layer 10, the Gate Electrode Conductive
It is isolated between polysilicon 09 and source conductive polysilicon 12 by insulating oxide 13.
The source metal 11 and the second conductivity type body region 05,06 Ohmic contact of the first conduction type source region, semiconductor
Drain metal 14 is provided on second interarea 002 of substrate, the drain metal 14 connects for 01 ohm with the first conductivity type substrate
Touching.
The groove grid super node semiconductor devices of the utility model is suitable for MOS device or IGBT device.
The characteristics of the utility model is, input capacitance Ciss=Cgd+Cgs of super-junction semiconductor device, the utility model
The source conductive polysilicon 12 of introducing increases the area between Gate Electrode Conductive polysilicon 09 and source conductive polysilicon 12, i.e.,
Cgs is increased, therefore input capacitance Ciss will increase, and then reduce switching speed, improves the EMI performance of system.
The utility model and embodiments thereof are described above, description is not limiting, shown in the drawings
It also is one of the embodiments of the present invention, actual structure is not limited to this.All in all if this field it is general
Logical technical staff is enlightened by it, without deviating from the purpose of the present invention, is not inventively designed and is somebody's turn to do
The similar frame mode of technical solution and embodiment, all should belong to the protection range of the utility model.
Claims (7)
1. a kind of groove grid super node semiconductor devices for optimizing switching speed, including cellular region and terminal protection area, the cellular
Area is located at the center of device, and the terminal protection area is looped around around the cellular region, and the cellular region includes semiconductor
Substrate, the semiconductor substrate include the first conductivity type substrate (01) and are located on the first conductivity type substrate (01) and adjacent
The first conductive type epitaxial layer (02), the upper surface of first conductive type epitaxial layer (02) is the first of semiconductor substrate
Interarea (001), the lower surface of first conductivity type substrate (01) are the second interarea (002) of semiconductor substrate；
Several super-junction structures are provided in first conductive type epitaxial layer (02), the super-junction structure is by the first conduction type
Column (03) and the second conductivity type columns (04) are arranged alternately, first conductivity type columns (03) and the second conductivity type columns
(04) extend along the first interarea (001) to the direction of the second interarea (002)；
It is equipped with the second conductivity type body region (05) in the second conductivity type columns (04) in the first conductive type epitaxial layer (02),
And second conductivity type body region (05) be set in the first conductive type epitaxial layer (02), in second conductivity type body region (05)
Equipped with the first conduction type source region (06), it is equipped with gate groove (07) between second conductivity type body region (05), described first
Conduction type source region (06) is arranged in the two sides of the second conductivity type body region (05), and adjacent with gate groove (07), the grid ditch
Insulating medium layer (10) are covered on slot (07), it is characterised in that: gate oxide (08) is equipped in the gate groove (07), in institute
It states and is covered with Gate Electrode Conductive polysilicon layer (09) in the groove of gate oxide (08) formation, on the Gate Electrode Conductive polysilicon (09)
It is covered with insulating oxide (13), is filled with source conductive polysilicon (12) in the groove that insulating oxide (13) is formed, it is described
Source conductive polysilicon (12) and source metal (11) Ohmic contact being covered on the first interarea of semiconductor substrate (001).
2. a kind of groove grid super node semiconductor devices for optimizing switching speed according to claim 1, it is characterised in that: right
In N-type super-junction semiconductor device, first conduction type is that N-type is conductive, and second conduction type is P-type conduction；For P
Type super-junction semiconductor device, first conduction type are P-type conduction, and second conduction type is that N-type is conductive.
3. a kind of groove grid super node semiconductor devices for optimizing switching speed according to claim 1, it is characterised in that: institute
State Gate Electrode Conductive polysilicon layer (09) with a thickness of 0.5 μm ~ 1 μm.
4. a kind of groove grid super node semiconductor devices for optimizing switching speed according to claim 1, it is characterised in that: institute
State insulating oxide (13) with a thickness of 500A ~ 1000A.
5. a kind of groove grid super node semiconductor devices for optimizing switching speed according to claim 1, it is characterised in that: institute
It states and is isolated between Gate Electrode Conductive polysilicon (09) and source metal (11) by insulating medium layer (10), the Gate Electrode Conductive polycrystalline
It is isolated between silicon (09) and source conductive polysilicon (12) by insulating oxide (13).
6. a kind of groove grid super node semiconductor devices for optimizing switching speed according to claim 1, it is characterised in that: institute
State source metal (11) and the second conductivity type body region (05), first conduction type source region (06) Ohmic contact, semiconductor substrate
The second interarea (002) on be provided with drain metal (14), the drain metal (14) and the first conductivity type substrate (01) Europe
Nurse contact.
7. a kind of groove grid super node semiconductor devices for optimizing switching speed according to claim 1, it is characterised in that: institute
Stating super-junction semiconductor device is MOS device or IGBT device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820448797.5U CN208422922U (en) | 2018-03-30 | 2018-03-30 | A kind of groove grid super node semiconductor devices optimizing switching speed |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820448797.5U CN208422922U (en) | 2018-03-30 | 2018-03-30 | A kind of groove grid super node semiconductor devices optimizing switching speed |
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| CN208422922U true CN208422922U (en) | 2019-01-22 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111883515A (en) * | 2020-07-16 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Trench gate device and manufacturing method thereof |
| CN113327984A (en) * | 2021-05-26 | 2021-08-31 | 深圳市威兆半导体有限公司 | Groove-gate super-junction VDMOS device, chip and terminal equipment |
-
2018
- 2018-03-30 CN CN201820448797.5U patent/CN208422922U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111883515A (en) * | 2020-07-16 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Trench gate device and manufacturing method thereof |
| US11527633B2 (en) | 2020-07-16 | 2022-12-13 | Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Trench gate device and method for making the same |
| CN113327984A (en) * | 2021-05-26 | 2021-08-31 | 深圳市威兆半导体有限公司 | Groove-gate super-junction VDMOS device, chip and terminal equipment |
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