CN203133839U - Multi-bus embedded processing device - Google Patents
Multi-bus embedded processing device Download PDFInfo
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- CN203133839U CN203133839U CN 201320162352 CN201320162352U CN203133839U CN 203133839 U CN203133839 U CN 203133839U CN 201320162352 CN201320162352 CN 201320162352 CN 201320162352 U CN201320162352 U CN 201320162352U CN 203133839 U CN203133839 U CN 203133839U
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Abstract
The utility model discloses a multi-bus embedded processing device which comprises an extensible processor configured on a mother board, and a programmable logic part of the processor comprises a main program unit. A data collection daughter card interface is further arranged on the mother board. The main program unit comprises a data collection module connected with the data collection daughter card interface and trains the data collection daughter card interface in rotation. The data collection module operates programs in a data collection daughter card if the data collection module is connected with the data collection daughter card. The multi-bus embedded processing device solves problems of system operation speed limitation and system reconfigurability shortage. Therefore, system reconfiguration requirements are met, and simultaneously device use cost is reduced and system reusable performance is improved due to the fact that cost of the daughter card is far smaller than that of the mother board.
Description
Technical field
The utility model relates to the industrial computer field, particularly multibus embedded processing device.
Background technology
High speed development along with computing machine and infotech, the embedded computer that it is associated and industrial computer have also obtained significant progress according to different application demands, embedded computer and industrial computer technology success in recent years be applied to each industrial control field such as communication, radar, image processing.Current embedded industrial computer generally adopts the cpci bus structure, but the cpci bus structure is owing to exist the restriction of transfer rate, and therefore, can't be applied in needs under the higher occasion of high-speed computation and transfer rate.Simultaneously, realize that its Scalable Performance is restricted because the processing core of traditional embedded industrial computer is single CPU, can't realize the expansion of local function and adjustment flexibly.
Hence one can see that, in realizing process of the present invention, the inventor finds to have following shortcoming in the prior art: the processing power of embedded industrial computer mainly depends on the core processor of FPGA inside in the prior art, its technical capability and speed are limited, simultaneously, in case system architecture and internal compute unit are determined, can't structure and the performance of internal element be promoted, cause whole embedded industrial computer not have reconfigurability, thereby make the controllability variation of system, use cost improves, and can't satisfy the demand of existing application.
The utility model content
At defective of the prior art, the utility model provides multibus embedded processing device, and the resolution system travelling speed is limited, system does not have the problem of reconfigurability.
Thus, multibus embedded processing device comprises: dispose scalable processors at motherboard, comprise in the FPGA (Field Programmable Gate Array) part of this processor: the master routine unit wherein, also comprises on described motherboard: the data acquisition daughtercard interface; Described master routine unit comprises: data acquisition module, described data acquisition module is connected with described data acquisition daughtercard interface, the described data acquisition daughtercard interface of described master routine unit training in rotation, if be connected with the data acquisition subcard, then described data acquisition module moves the program in the described data acquisition subcard.
As a kind of embodiment, also comprise on the described motherboard: data storage daughtercard interface; Described master routine also comprises in the unit: data memory module, described data memory module is connected with described data storage daughtercard interface, the described data storage of described master routine unit training in rotation daughtercard interface, if be connected with data storage subcard, then described data memory module expands to the local datastore module with described data storage subcard.
As a kind of embodiment, on described motherboard, also comprise: the data communication daughtercard interface; Described master routine also comprises in the unit: data communication module, described data communication module is connected with described data communication daughtercard interface, the described data communication daughtercard interface of described master routine unit training in rotation, if be connected with other isomorphism motherboards, then described data communication module is set up with the data communication module of described isomorphism motherboard and is communicated by letter.
As a kind of embodiment, sign, the data communication module sign of the local a plurality of motherboards that prestore in the data communication module of described different motherboards.
As a kind of embodiment,, described processor system partly comprises: USB-OTG interface, 10M, 100M or 1000M RJ45 interface and DVI interface, described USB-OTG interface, 10M, 100M or 1000M RJ45 interface and DVI interface are connected with the connector of respective type respectively.
As a kind of embodiment, comprise that also cabinet comprises on the panel of described cabinet: the USB-OTG interface slot; 10M, 100M and/or 1000M RJ45 interface slot; DVI interface slot, the connector of described USB-OTG interface are connected in the described USB-OTG interface slot; The connector of the interface of described 10M, 100M and/or 1000M RJ45 is connected in the interface slot of described 10M, 100M and/or 1000M RJ45; The connector of described DVI interface is connected in the described DVI interface slot.
As a kind of embodiment, the digital interface that also comprises in the described FPGA (Field Programmable Gate Array) part is: CPCI communication interface, CPCIE communication interface, SRIO communication interface.
As a kind of embodiment, also comprise: the CPCI communications interface control module, one end of described CPCI communications interface control module is connected with described CPCI communication interface, the other end and a plurality of CPCI plug receptacle of communicating by letter is connected, according to the setting weight of described a plurality of CPCI communication plug receptacles, control described a plurality of CPCI communication plug receptacle and be connected with described CPCI communication interface.
As a kind of embodiment, also comprise: communicate by letter with one or more CPCI plug receptacle serial connection of PCIE and PCI X-over, this joint.
Compared with prior art, have the following advantages according to multibus embedded processing device of the present utility model: by a plurality of function subcard connectors are set at motherboard, the master routine unit of external function subcard with inside is connected, the master routine unit is in the time can realizing basic function, can also be by the function of difference in functionality subcard, realize multiple subcard function, make system have reconfigurability flexibly, therefore, satisfied the demand of system reconfiguration, simultaneously since the required expense of subcard far below motherboard, thereby reduced the use cost of equipment, improved the reusable performance of system.
Description of drawings
Fig. 1 is the composition synoptic diagram of the utility model multibus embedded processing device;
Fig. 2 is the connection diagram of data communication module between multiple masters in the utility model multibus embedded processing device;
Fig. 3 is casing structure synoptic diagram in the utility model multibus embedded processing device;
Fig. 4 is many interfaces connection diagram of FPGA (Field Programmable Gate Array) part in the utility model multibus embedded processing device.
Embodiment
Below in conjunction with accompanying drawing the utility model is described in further detail.
Be the composition synoptic diagram of the utility model multibus embedded processing device as Fig. 1, the utility model multibus embedded processing device comprises: at motherboard 11 configuration scalable processors 12 and data acquisition daughtercard interfaces 15, comprise in this scalable processors 12: processor system part 13 and FPGA (Field Programmable Gate Array) part 14.In this FPGA (Field Programmable Gate Array) part 14, comprise: master routine unit 16, in master routine unit 16, comprise: data acquisition module 21, data acquisition module 21 is connected with above-mentioned data acquisition daughtercard interface 15, the power-up state of master routine unit 16 training in rotation data acquisition daughtercard interfaces 15, namely whether there is outside subcard to contact, specifically a pin in the data acquisition daughtercard interface 15 can be set at long-term power pin is the noble potential pin, after external data is gathered subcard 15a and 15 grafting of data acquisition daughtercard interface, this noble potential pin status is electronegative potential from the noble potential upset, thereby the data acquisition module 21 that is connected with data acquisition daughtercard interface 15 is learnt, having external data to gather subcard connects, data acquisition module 21 just can be realized reading to the data message of gathering in the outside data acquisition subcard by the setting of variable in the internal processes afterwards.In above-mentioned master routine unit 16 in the specific implementation for being solidificated in hardware capability module in the FPGA (Field Programmable Gate Array) part 14, be FPGA as FPGA (Field Programmable Gate Array) part 14, then be the hardware capability module among the FPGA, this functional module can realize by the development scheme of FPGA.Above-mentioned data acquisition subcard can adopt data collecting card commonly used, and the interface type of subcard can be forms such as PCI, USB and PCIe.
But scalable processors 12 parts can adopt the ZYNQ7000 extension process platform (EPP) of match SEL to realize in the above-described embodiment, ZYNQ7000 is the framework specification of 6U standard, compatible cpci bus, the CPCIE bus, SRIO HSSI High-Speed Serial Interface bus and self-defined bus, therefore, when using, ZYNQ7000 can pass through cpci bus, a certain in CPCIE bus or the SRIO HSSI High-Speed Serial Interface bus links to each other with motherboard, the processor system part 13 of ZYNQ7000 is built-in double-core arm processor, FPGA (Field Programmable Gate Array) part 14 is FPGA(Field-Programmable Gate Array, be field programmable gate array) the logic function integrated chip, therefore, make ZYNQ7000 when having high calculation function, also possess the high performance parallel computation ability of FPGA, but and the function of FPGA hardware capability module flexible configuration, thereby can satisfy processing and the transmission demand of high-speed digital signal substantially.Above-mentioned processor system part 13 also comprises: USB-OTG interface 31,10M, 100M or 1000M RJ45 interface 32 and DVI interface 33, USB-OTG interface 31,10M, 100M or 1000M RJ45 interface 32 and DVI interface 33 can be connected with the outside connector 34,35,36 of respective type respectively.
For above-mentioned multibus embedded processing device be can be applicable in the application that needs big capacity internal memory or storage, as the improvement to above-mentioned treating apparatus, on motherboard 11, also comprise: data storage daughtercard interface 17; Also comprise in the master routine unit 16: data memory module 22, data memory module 22 is connected with data storage daughtercard interface 17, master routine unit 16 training in rotation data storage daughtercard interface 17, if 17a is connected with data storage subcard, then data memory module 22 is stored the part that subcard expands to the local datastore module with data, can realize the utilization to external storage resources.Above-mentioned data storage subcard can adopt storage cards such as data storage card commonly used such as CF card, SD card, MS card, mmc card.
For above-mentioned multibus embedded processing device be can be applicable in the application that needs the multiple masters collaborative work, as the improvement to above-mentioned treating apparatus, on a plurality of motherboards 11, also comprise: data communication daughtercard interface 18; Also comprise in the master routine unit 16: data communication module 23, data communication module 23 is connected with data communication daughtercard interface 18, master routine unit 16 training in rotation data communication daughtercard interfaces 18, if be connected with the data communication module 23a of other isomorphism motherboards, then data communication module 23 is set up with the data communication module 23 of isomorphism motherboard 11 and is communicated by letter.In order to realize the communication of above-mentioned different motherboard 11, in the data communication module 23 of different motherboards 11, comprise: unique mailing address sign, data communication module 23 signs of the local a plurality of motherboard 11 that prestores in the data communication module 23 of different motherboards 11.As shown in Figure 2, as in the multibus embedded processing device of this locality, comprising altogether: three motherboard 11a, 11b and 11c, in each motherboard, respectively comprise data communication module 23-1,23-2 and 23-3, data communication module 23-1,23-2 and 23-3 comprise mailing address sign #23-01 respectively, #23-02 and #23-03, and with #23-01, #23-02 and #23-03 deposit data communication module 23-1 simultaneously in, among 23-2 and the 23-3, as data communication module 23-1 among the motherboard 11a after data communication module 23-2 connects by data communication daughtercard interface 18 in the motherboard 11b, data communication module 23-1 receives the mailing address sign 23-2 of data communication module 23-2 among the motherboard 11a, after the checking by the mailing address sign that prestores with this locality, communicate by letter with data communication module 23-2 foundation among the motherboard 11b, it is to be noted between two motherboards, set up and interconnectedly also can adopt multiple mode, adopt the above-mentioned benefit of setting up mutual contact mode to be, owing between different isomorphism motherboards, there is common communication interface standard, therefore, set up when interconnected at different isomorphism motherboards, can save the identification to dissimilar motherboards, improved the interconnect speeds between different isomorphism motherboards, the local verification process of each motherboard also can prevent because of the harm that total system is brought of using with between the different motherboards simultaneously.
As shown in Figure 3, this bus embedded type treating apparatus in the specific implementation, but integral installation be assigned in the outside cabinet 41, comprise on the panel 42 of cabinet 41: USB-OTG interface slot 43; 10M, 100M and/or 1000M RJ45 interface slot 44; DVI interface slot 45, the connector 33 of USB-OTG interface is connected in the USB-OTG interface slot 43; The connector 34 of the interface of 10M, 100M and/or 1000M RJ45 is connected in the interface slot 33 of 10M, 100M and/or 1000M RJ45; The connector 35 of DVI interface is connected in the DVI interface slot 45.
As shown in Figure 4, also can comprise in the FPGA (Field Programmable Gate Array) part 14 in the scalable processors 12 of this bus embedded type treating apparatus: CPCI communication interface 19(is middle 19a-1,19a-2 and 19a-3 as shown), CPCIE communication interface 110, SRIO communication interface 111.Above-mentioned interface respectively with outside CPCI communication interface connector 19a, CPCIE communication interface connector 110a, SRIO communication interface connector 111a, as CPCI communication interface 19 (19a-1 as shown when being a plurality of, 19a-2 and 19a-3), for realizing that a plurality of CPCI communication interfaces 19 are controlled, in said apparatus, also comprise: CPCI communications interface control module 112, one end of CPCI communications interface control module 112 and CPCI communication interface 19(be middle 19a-1 as shown, 19a-2 and 19a-3) connect, the other end and a plurality of CPCI plug receptacle of communicating by letter is connected, according to the setting weight of a plurality of CPCI communication plug receptacles, control a plurality of CPCI communication plug receptacles and be connected with CPCI communication interface 19.Said method is equally when being a plurality of when CPCIE communication interface 110 and SRIO communication interface 111.Simultaneously, have interchangeability preferably for making interface, 19 places also comprise in the CPCI communication interface: communicate by letter with one or more CPCI plug receptacle serial connection of PCIE and PCI X-over 113, this joint 113.
Above-described only is embodiments more of the present utility model.For the person of ordinary skill of the art, under the prerequisite that does not break away from the utility model creation design, can also make some distortion and improvement, these all belong to the protection domain of utility model.
Claims (9)
1. multibus embedded processing device comprises: dispose scalable processors at motherboard, comprise in the FPGA (Field Programmable Gate Array) part of this processor: the master routine unit, it is characterized in that, and on described motherboard, also comprise: the data acquisition daughtercard interface; Described master routine unit comprises: data acquisition module, described data acquisition module is connected with described data acquisition daughtercard interface, the described data acquisition daughtercard interface of described master routine unit training in rotation, if be connected with the data acquisition subcard, then described data acquisition module moves the program in the described data acquisition subcard.
2. treating apparatus as claimed in claim 1 is characterized in that, also comprises on described motherboard: data storage daughtercard interface; Described master routine also comprises in the unit: data memory module, described data memory module is connected with described data storage daughtercard interface, the described data storage of described master routine unit training in rotation daughtercard interface, if be connected with data storage subcard, then described data memory module expands to the local datastore module with described data storage subcard.
3. treating apparatus as claimed in claim 1 or 2 is characterized in that, also comprises on described motherboard: the data communication daughtercard interface; Described master routine also comprises in the unit: data communication module, described data communication module is connected with described data communication daughtercard interface, the described data communication daughtercard interface of described master routine unit training in rotation, if be connected with other isomorphism motherboards, then described data communication module is set up with the data communication module of described isomorphism motherboard and is communicated by letter.
4. treating apparatus as claimed in claim 3, it is characterized in that, described motherboard is a plurality of, comprises in the data communication module of described different motherboards: unique mailing address sign, the data communication module sign of the local a plurality of motherboards that prestore in the data communication module of described different motherboards.
5. treating apparatus as claimed in claim 1, it is characterized in that, described processor system partly comprises: the USB-OTG interface, 10M, 100M or 1000M RJ45 interface and DVI interface, described USB-OTG interface, 10M, 100M or 1000M RJ45 interface and DVI interface are connected with the connector of respective type respectively.
6. treating apparatus as claimed in claim 5 is characterized in that, comprises that also cabinet comprises on the panel of described cabinet: the USB-OTG interface slot; 10M, 100M and/or 1000M RJ45 interface slot; DVI interface slot, the connector of described USB-OTG interface are connected in the described USB-OTG interface slot; The connector of the interface of described 10M, 100M and/or 1000M RJ45 is connected in the interface slot of described 10M, 100M and/or 1000M RJ45; The connector of described DVI interface is connected in the described DVI interface slot.
7. treating apparatus as claimed in claim 1 is characterized in that, the digital interface that also comprises in the described FPGA (Field Programmable Gate Array) part is: CPCI communication interface, CPCIE communication interface, SRIO communication interface.
8. treating apparatus as claimed in claim 7, it is characterized in that, also comprise: the CPCI communications interface control module, one end of described CPCI communications interface control module is connected with described CPCI communication interface, the other end and a plurality of CPCI plug receptacle of communicating by letter is connected, according to the setting weight of described a plurality of CPCI communication plug receptacles, control described a plurality of CPCI communication plug receptacle and be connected with described CPCI communication interface.
9. as claim 7 or 8 described treating apparatus, it is characterized in that, also comprise: communicate by letter with one or more CPCI plug receptacle serial connection of PCIE and PCI X-over, this joint.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320162352 CN203133839U (en) | 2013-04-03 | 2013-04-03 | Multi-bus embedded processing device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320162352 CN203133839U (en) | 2013-04-03 | 2013-04-03 | Multi-bus embedded processing device |
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| CN203133839U true CN203133839U (en) | 2013-08-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201320162352 Withdrawn - After Issue CN203133839U (en) | 2013-04-03 | 2013-04-03 | Multi-bus embedded processing device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103207852A (en) * | 2013-04-03 | 2013-07-17 | 北京华清瑞达科技有限公司 | Multi-bus embedded processing device |
| CN113760817A (en) * | 2017-03-28 | 2021-12-07 | 上海山里智能科技有限公司 | Integrated computing system |
-
2013
- 2013-04-03 CN CN 201320162352 patent/CN203133839U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103207852A (en) * | 2013-04-03 | 2013-07-17 | 北京华清瑞达科技有限公司 | Multi-bus embedded processing device |
| CN103207852B (en) * | 2013-04-03 | 2016-03-02 | 北京华清瑞达科技有限公司 | Multibus embedded processing device |
| CN113760817A (en) * | 2017-03-28 | 2021-12-07 | 上海山里智能科技有限公司 | Integrated computing system |
| CN113760817B (en) * | 2017-03-28 | 2024-05-24 | 上海山里智能科技有限公司 | Comprehensive computing system |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20130814 Effective date of abandoning: 20160302 |
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| C25 | Abandonment of patent right or utility model to avoid double patenting |