CN202896517U

CN202896517U - Wireless in-vehicle network intelligent anti-theft system

Info

Publication number: CN202896517U
Application number: CN 201220598355
Authority: CN
Inventors: 赵伟杰; 林凌鹏
Original assignee: Hangzhou Dianzi University
Current assignee: Hangzhou Dianzi University
Priority date: 2012-11-13
Filing date: 2012-11-13
Publication date: 2013-04-24
Anticipated expiration: 2022-11-13

Abstract

The utility model discloses a wireless in-vehicle network intelligent anti-theft system. A product in the prior art gives an alarm only when a motor vehicle is stolen, cannot track a moving path of the motor vehicle in real time, and cannot track and accurately position the stolen motor vehicle. The wireless in-vehicle network intelligent anti-theft system comprises a power management module, a global system for mobile communication / general packet radio service (GSM/GPRS) module, a global positioning system (GPS) module, a liquid crystal module, a controller and a peripheral equipment module. The wireless in-vehicle network intelligent anti-theft system has GPS and GSM functions of like products, and the motor vehicle is prevented from being directly stolen; and functions of preventing a storage battery from being stolen and querying the geographic position of the motor vehicle by real-time positioning through Google Earth software are added, the like products do not have the functions, and the motor vehicle can be prevented from being stolen to a great extent.

Description

The wireless automotive networks intelligent anti-theft system

Technical field

The utility model product belongs to the embedded system technology field, is specifically related to a kind of wireless automotive networks intelligent anti-theft system.

Background technology

Along with the raising of socioeconomic development, living standards of the people, private car has entered into people's life.Annual upper trillion dollars automobile industry is one of backbone industry of world economy, can be penetrated into the every aspect of society life as automobile without any a kind of industrial goods.It thoroughly changes and has improved people's life style and quality of life with the continuous renewal of its technology and product.A new social concern has produced simultaneously: use the number of self-propelled vehicle constantly to increase, and self-propelled vehicle is stolen the case cumulative year after year.By visiting Zhejiang Province's traffic office, we recognize that there is more than 350 ten thousand self-propelled vehiclees stolen (containing Electrical Bicycle) every year in Zhejiang Province.Through consulting related data and literature search and investigation on the spot, we find that anti-theft device for motor vehicle has in the market " GPS+GSM+GPRS storage battery car steady arm ", " motor bike, storage battery car, the special-purpose GPSONE steady arm of power car " etc., but the function of these products all is to send alarm when self-propelled vehicle goes adrift, can not real-time tracking vehicle mobile path, more can not follow the tracks of and accurately locate stolen self-propelled vehicle.And the said goods price also has a kind of fingerprint recognition system price more up to 2000 yuan in 700-800 unit even higher.By contrast, this series products price is obviously higher, is difficult to be accepted by popular.Design vehicle-mounted wireless network intelligent anti-theft system, like product GPS, GSM function have been inherited, prevent that self-propelled vehicle is directly stolen, novelty has increased the anti-storage battery pilferage that like product does not have, the function in the real-time locating query self-propelled vehicle of Google Earth geographic position again, can prevent to a great extent that self-propelled vehicle is stolen.The anti-joyride device that this project is developed is promoted, reduced self-propelled vehicle and steal the case generation, realized the benign cycle of society.

Summary of the invention

The utility model has proposed a kind of wireless automotive networks intelligent anti-theft system for the deficiencies in the prior art.

A kind of wireless automotive networks intelligent anti-theft system comprises power management module, GSM/GPRS module, GPS module, Liquid Crystal Module, controller and peripheral module thereof.

Described power management module comprises that LM317 is mu balanced circuit and the mu balanced circuit take LM1117 as core of core.

Mu balanced circuit take LM317 as core comprises LM317 power supply chip U2, potential device R10, the first Chip-R R8, the first magnetic bead B1, the second magnetic bead B2, diode D1, the first polar capacitor C14, the first filter capacitor C13, the second filter capacitor C15, the 3rd filter capacitor C16; The 1st pin of LM317 power supply chip U2 is connected with the sliding end of the end of potential device R10, potential device R10, the end of the first Chip-R R8; The 2nd pin of LM317 power supply chip U2 is connected with the end of the other end of the first Chip-R R8, the first magnetic bead B1, the anode of diode D1, the end of the first polar capacitor C14, the end of the second filter capacitor C15, the end of the 3rd filter capacitor C16; The other end of the first magnetic bead B1 links to each other with power interface VBAT, the negative electrode of diode D1 is connected with the end of the second magnetic bead B2, the other end of the second magnetic bead B2 links to each other with power interface VEXT, the other end ground connection of the other end of the other end of the first polar capacitor C14, the second filter capacitor C15, the 3rd filter capacitor C16; The 3rd pin of LM317 power supply chip U2 is connected the other end and the grounding connection of the other end of the first filter capacitor C13 and potential device R10 with an end, the power interface VIN of the first filter capacitor C13.

Mu balanced circuit take LM1117 as core comprises LM1117 voltage stabilizing chip L3 and the second polar capacitor C18; The 1st pin of LM1117 voltage stabilizing chip L3 is connected with power interface VIN, the 2nd pin of LM1117 voltage stabilizing chip L3 and an end and the grounding connection of the second polar capacitor C18, the 3rd pin of LM1117 voltage stabilizing chip L3 is connected with the other end of power interface VCC-3.3, the second polar capacitor C18.

Described GSM/GPRS module comprises SIM900A circuit, microphone interface circuit, audio power amplifier circuit, earphone interface circuit, LED indicating circuit, esd protection circuit, SIM circuit.

The SIM900A circuit comprises SIM900A module SM1, SMA antennal interface RF2, the first matched resistance R15, the second matched resistance R16, the 3rd matched resistance R21, the second Chip-R R27, the first matching capacitance C25, the 4th filter capacitor C22, the 5th filter capacitor C23, the 6th filter capacitor C36, the 3rd polar capacitor C21; The 1st pin of SIM900A module SM1 is connected with the end of the 3rd matched resistance R21, the other end of the 3rd matched resistance R21 is connected with POWER_KEY, the 15th pin of SIM900A module SM1 links to each other with power interface VDD_EXT, the 17th of SIM900A module SM1,18,29,39,45,46,53,54,58,59,61,62,63,64,65 pin ground connection, the 19th pin meets MIC_N, the 20th pin meets MIC_P, the 21st pin meets SPK_P, the 22nd pin meets SPK_N, the 27th pin meets DBG_TXD, the 28th pin meets DBG_RXD, the 26th pin links to each other with power interface VCC-3.3, the 34th pin and SIM_PRECENCE, the end of the second Chip-R R27 links to each other, the other end of the second Chip-R R27 links to each other with power interface SIM_VDD, the 33rd pin meets SIM_RST, the 32nd pin meets SIM_CLK, the 31st pin meets SIM_DATA, No. 30 pin and SIM_VDD power supply, the end of the 6th filter capacitor C36 connects, the other end grounding connection of the 6th filter capacitor C36, the 52nd pin links to each other with NETLIGHT, the 55th pin and the 56th pin, the 57th pin, power interface VBAT, the end of the 3rd polar capacitor C21, the end of the 4th filter capacitor C22, the end of the 5th filter capacitor C23 connects, the other end of the 3rd polar capacitor C21, the other end of the 4th filter capacitor C22, the other end grounding connection of the 5th filter capacitor C23, the 60th pin links to each other with the end of the second matched resistance R16, the end of the other end of the second matched resistance R16 and the first matching capacitance C25, the end of the first matched resistance R15 links to each other, the other end of the first matched resistance R15 links to each other with SMA antennal interface RF2 the 5th pin, the other end of the first matching capacitance C25 and SMA antennal interface RF2 the 1st, 2,3,4 pin and grounding connection, the 66th pin meets STATUS.

Microphone interface circuit comprises miaow head M2, the 7th filter capacitor C26, the 8th filter capacitor C27, the 9th filter capacitor C28, the tenth filter capacitor C29, the 11 filter capacitor C30, the 12 filter capacitor C31; An end and the grounding connection of the end of the 7th filter capacitor C26 and the 8th filter capacitor C27, the end of the other end of the 7th filter capacitor C26 and the 9th filter capacitor C28, the end of miaow head M2, the other end of the 8th filter capacitor C27, the end of the tenth filter capacitor C29, MIC_N connects, the end of the other end of the 9th filter capacitor C28 and the 11 filter capacitor C30, the other end of miaow head M2, the other end of the tenth filter capacitor C29, the end of the 12 filter capacitor C31, MIC_P links to each other, and the other end of the 11 filter capacitor C30 is connected with the other end of the 12 filter capacitor C31 and grounding connection.Audio power amplifier circuit comprises LM4890 chip LM1, the 3rd Chip-R R28, the 4th matched resistance R31, the 5th matched resistance R33, the 6th matched resistance R34, the second matching capacitance C40, the 3rd matching capacitance C42, the 4th matching capacitance C43, the 13 filter capacitor C41, loudspeaker BUZZER1.The 1st pin of LM4890 chip LM1 is connected with SHUTDOWN, the end of the 2nd pin and the 3rd Chip-R R28, the end of the second matching capacitance C40 links to each other, the other end ground connection of the second matching capacitance C40, the 3rd pin of LM4890 chip LM1 and the other end of the 3rd Chip-R R28, the end of the 4th matched resistance R31 links to each other, the other end of the 4th matched resistance R31 links to each other with the end of the 3rd matching capacitance C42, the other end of the 3rd matching capacitance C42 links to each other with SPK_P, the end of the 4th pin of LM4890 chip LM1 and the 5th matched resistance R33, the end of the 6th matched resistance R34 links to each other, the other end of the 5th matched resistance R33 links to each other with the end of the 4th matching capacitance C43, the other end of the 4th matching capacitance C43 links to each other with SPK_N, the other end of the 5th pin and the 6th matched resistance R34, SPK_N_A, the 2nd pin of loudspeaker BUZZER1 links to each other, the 6th pin and power interface VIN, the end of the 13 filter capacitor C41 links to each other, the 7th pin of LM4890 chip LM1 and the other end and the grounding connection of the 13 filter capacitor C41, the 8th pin and the SPK_P_A of LM4890 chip LM1, the 1st pin of loudspeaker BUZZER1 links to each other.

Earphone interface circuit comprises the 14 filter capacitor C32, the 15 filter capacitor C33, the 16 filter capacitor C34, the 17 filter capacitor C35, the 18 filter capacitor C37, the 19 filter capacitor C38, earphone inserter P1; The end of the 14 filter capacitor C32 and an end and the grounding connection of the 15 filter capacitor C33, the end of the other end of the 14 filter capacitor C32 and the 16 filter capacitor C43, the 4th pin of earphone inserter P1, the other end of the 15 filter capacitor C33, the end of the 17 filter capacitor C35, SPK_P connects, the end of the other end of the 16 filter capacitor C43 and the 18 filter capacitor C37, the 3rd pin of earphone inserter P1, the other end of the 17 filter capacitor C35, the end of the 19 filter capacitor C38, SPK_N connects, the 2nd pin of the other end of the 18 filter capacitor C37 and earphone inserter P1, the other end of the 19 filter capacitor C38 connects and grounding connection, and the 1st foot rest of earphone inserter P1 is empty.

The LED indicating circuit comprises the first aerotron Q1, the second aerotron Q3, the 3rd aerotron Q4, the first light-emitting diode DS2, the second light-emitting diode DS3, the 4th Chip-R R13, the 5th Chip-R R17, the 6th Chip-R R19, the 7th Chip-R R22, the 8th Chip-R R24, the 9th Chip-R R20, the tenth Chip-R R23, the 11 Chip-R R25, the first button S2; The first aerotron Q1 collecting electrode meets POWER_KEY, base stage links to each other with the end of the 4th Chip-R R13, the end of the 5th Chip-R R17, the other end of the 4th Chip-R R13 links to each other with the end of the first button S2, the other end of the first button S2 links to each other with power interface VEXT, and the emitter of the first aerotron Q1 is connected with the other end of the 5th Chip-R R17 and ground connection;

The collecting electrode of the second aerotron Q3 links to each other with the negative electrode of the first light-emitting diode DS2, and the anode of the first light-emitting diode DS2 links to each other with the end of the 6th Chip-R R19, and the other end of the 6th Chip-R R19 links to each other with power interface VEXT; The base stage of the second aerotron Q3 links to each other with the end of the 7th Chip-R R22, the end of the 8th Chip-R R24, the other end of the 7th Chip-R R22 links to each other with STATUS, and the emitter of the second aerotron Q3 is connected with the other end of the 8th Chip-R R24 and ground connection;

The collecting electrode of the 3rd aerotron Q4 links to each other with the negative electrode of the second light-emitting diode DS3, the anode of the second light-emitting diode DS3 links to each other with the end of the 9th Chip-R R20, the other end of the 9th Chip-R R20 links to each other with power interface VEXT, the base stage of the second aerotron Q3 links to each other with the end of the tenth Chip-R R23, the end of the 11 Chip-R R25, and the other end of the tenth Chip-R R23 links to each other with NETLIGHT; The emitter of the 3rd aerotron Q3 is connected with the other end of the 11 Chip-R R25 and ground connection.

Esd protection circuit comprises PESD3V3L5UV chip P2; The 1st, 3 pin of PESD3V3L5UV chip P2 are unsettled, the 2nd pin ground connection, and the 4th pin meets SIM_CLK_ESD, and the 5th pin meets SIM_RST_ESD, and the 6th pin meets SIM_DATA_ESD.

The SIM circuit comprises SIM deck SIM2, the 7th matched resistance R29, the 8th matched resistance R30, the 9th matched resistance R32, the 20 filter capacitor C44.SIM deck SIM2 the 1st pin meets SIM_VDD, the 2nd pin connects the end of the 7th matched resistance R29, another termination SIM_RST of the 7th matched resistance R29, the 3rd pin connects the end of the 8th matched resistance R30, and the other end of the 8th matched resistance R30 links to each other with SIM_CLK, the 4th pin ground connection, the 6th pin connects the end of the 9th matched resistance R32, the end of the 20 filter capacitor C44, another termination SIM_DATA of the 9th matched resistance R32, the other end ground connection of the 20 filter capacitor C44, the 5th foot rest is empty.

Described GPS module is made of the circuit take the NEO-6M module as core.

Circuit take the NEO-6M module as core comprises UBLOX_NEO_6M module U1, antenna SMA interface RF1, the tenth matched resistance R1, the first inductance L 1; The 24th, 13,12,10, the 7 pin ground connection of UBLOX_NEO_6M module U1,3 pin of the 20th pin connector JP1, the 21st pin connects 1 pin of connector JP1, and the 22nd, 23 pin meet VCC-3.3, and the 11st pin links to each other with the 5th pin of antenna SMA interface RF1, an end of the first inductance L 1; UBLOX_NEO_6M module U1 the 8th, 9 pin link to each other, and link to each other with the end of the tenth matched resistance R1, and the other end of the tenth matched resistance R1 links to each other with the other end of the first inductance L 1; The 1st, 2,3,4 of antenna SMA interface RF1 links to each other and ground connection; 1,2,3,4,5,6,14,15,16,17,18,19 foot rests of UBLOX_NEO_6M module U1 are empty.

Described Liquid Crystal Module is made of TFT color screen liquid crystal circuit.

TFT color screen liquid crystal circuit is by TFT2.8 cun liquid crystal T1, the 21 filter capacitor C17, the 22 filter capacitor C20, the 5th matching capacitance C19, the 12 Chip-R R11, the 13 Chip-R R12; TFT2.8 cun liquid crystal T1 the 1st pin links to each other with the 40th pin of STM32F103RBT6 chip STM1, the 2nd pin links to each other with the 39th pin of STM32F103RBT6 chip STM1, the 3rd pin links to each other with the 38th pin of STM32F103RBT6 chip STM1, the 4th pin links to each other with the 37th pin of STM32F103RBT6 chip STM1, the 5th pin links to each other with the 7th pin of STM32F103RBT6 chip STM1, the 6th, 7,8,9,10,11,12,13,14,15,16,17,18,19,20,21 pins respectively with the 26th of STM32F103RBT6 chip STM1,27,28,55,56,57,58,59,61,62,29,30,33,34,35,36 pin link to each other, the 22nd, 26 pin grounding connections, the 23rd pin links to each other with the 53rd pin of STM32F103RBT6 chip STM1, the 24th pin is connected with power interface VCC-3.3, and connect the end of the 21 filter capacitor C17, the other end ground connection of the 21 filter capacitor C17; The 25th pin is connected with VCC-3.3, the 27th pin ground connection also links to each other with the end of the 5th matching capacitance C19, the other end of the 5th matching capacitance C19 links to each other with the end of the 12 Chip-R R11, the end of the 13 Chip-R R12, and the other end of the 12 Chip-R R11 links to each other with the 9th pin of STM32F103RBT6 chip STM1.The 28th pin links to each other with power supply VCC-5.0 and connects the end of the 22 filter capacitor C20, the other end ground connection of the 22 filter capacitor C20.The 29th pin links to each other with the 10th pin of STM32F103RBT6 chip STM1, the 30th pin links to each other with the 11st pin of STM32F103RBT6 chip STM1, the 31st pin links to each other with the other end of the 13 Chip-R R12, the 32nd pin is unsettled, the 2nd pin that the 33rd pin meets STM32F103RBT6 chip STM1 links to each other, and the 34th pin connects the 8th pin of STM32F103RBT6 chip STM1.

Described controller and peripheral module thereof are made of STM32F103RBT6 minimum system circuit, W25X16 Flash circuit, Mini SD card circuit, debug i/f circuit.

STM32F103RBT6 minimum system circuit comprises STM32F103RBT6 chip STM1, the first shunt capacitance C3, the second shunt capacitance C4, the 3rd shunt capacitance C5, the 4th shunt capacitance C6, quadripolarity capacitor C 7, the 23 filter capacitor C1, the 24 filter capacitor C8, the 25 filter capacitor C11, the 26 filter capacitor C12, the 27 filter capacitor C2, the 28 filter capacitor C10, the first crystal oscillator X2, the second crystal oscillator X1, the 14 Chip-R R2, the 15 Chip-R R6, the 16 Chip-R R9, the second button S1, the second inductance L 2, the 3rd light-emitting diode DS1, connector JP2; The 3rd pin connects the end of the first shunt capacitance C3 and the end of the first crystal oscillator X2, and the other end of the first shunt capacitance C3 is connected and ground connection with the end of the second shunt capacitance C4, the end of the 3rd shunt capacitance C5, the end of the 4th shunt capacitance C6, the negative pole of quadripolarity capacitor C 7, the end of the 24 filter capacitor C8, the 12nd pin of STM32F103RBT6 chip STM1; The 4th pin connects the other end of the second shunt capacitance C4 and the other end of the first crystal oscillator X2; The 5th pin connects the other end of the 3rd shunt capacitance C5, the end of the 15 Chip-R R6, the end of the second crystal oscillator X1; The 6th pin connects the other end of the 4th shunt capacitance C6, the other end of the 15 Chip-R R6, the other end of the second crystal oscillator X1; The 7th pin connects the end of the 14 Chip-R R2, the end of the second button S1, the end of the 23 filter capacitor C1, another termination power interface VCC-3.3 of the 14 Chip-R R2, the other end of the second button S1 are connected with the other end of the 23 filter capacitor C1 and ground connection; The 13rd pin links to each other with the positive pole of quadripolarity capacitor C 7, the other end of the 24 filter capacitor C8, an end of the second inductance L 2, and the other end of the second inductance L 2 links to each other with the VCC-3.3 power interface; The 14th pin links to each other with PA0; The 15th pin links to each other with PA1; The 16th pin links to each other with 1 pin of W25X16 chips W 1; The 17th pin links to each other with SD_CS.The 18th pin is connected with the end of the 25 filter capacitor C11 and ground connection; The 19th pin links to each other with power supply VCC-3.3 and links to each other with the other end of the 25 filter capacitor C11; The 20th pin is connected with RESET_GSM; 21st, 22,23 pins are connected with 6,2,5 pin of W25X16 chips W 1 respectively; The 24th pin meets PC4; The 25th pin meets SHUTDOWN, and the 31st pin is connected with the end of the 26 filter capacitor C12 and ground connection; The 32nd pin links to each other with the other end of the 26 filter capacitor C12; The 41st pin connects the negative electrode of the 3rd light-emitting diode DS1, and the anode of the 3rd light-emitting diode DS1 connects the end of the 16 Chip-R R9, another termination power interface VCC-3.3 of the 16 Chip-R R9; 42nd, 43 pin are connected with 2,4 pin of connector JP1; The 48th pin meets an end and the power interface VCC-3.3 of the 28 filter capacitor C10, and the other end of the 28 filter capacitor C10 is connected with the 47th pin and ground connection; 51st, 52 are connected with 8,6 pin of connector JP1; The 64th pin links to each other with the end of power interface VCC-3.3, the 27 filter capacitor C2, the other end of the 27 filter capacitor C2 is connected with the 63rd pin and ground connection, the 1st pin is unsettled, the 44th pin meets PA11, and the 45th pin meets PA12, and the 46th pin meets PA13, the 49th pin meets PA14, the 50th pin meets PA15, and the 54th pin meets PD2, and the 60th pin meets BOOT0.

1 pin and 2 pin of connector JP2 meet power interface VCC-3.3, and 3 pin connect 28 pin of STM32F103RBT6 chip STM1, and 4 pin connect 60 pin of STM32F103RBT6 chip STM1,5 pin and 6 pin ground connection.

W25X16 Flash circuit is comprised of W25X16 chips W 1 and the 29 filter capacitor C9.The 3rd pin meets VCC-3.3, the 4th pin ground connection, and the 7th, 8 pins connect the end of VCC-3.3 power interface, the 29 filter capacitor C9, the other end ground connection of the 29 filter capacitor C9.

Mini SD card circuit is comprised of Mini SD card deck SD1, the first pull-up resistor R3, the second pull-up resistor R4, the 3rd pull-up resistor R5, four pull-up resistors of the 4th pull-up resistor R7.Mini SD card deck SD1 the 1st, 9 pins are unsettled, the 6th, 8,10,11,12,13 ground connection, the 2nd pin links to each other with SD_CS and connects the end of the first pull-up resistor R3, the 3rd pin links to each other with SPI1_MOSI and connects the end of the second pull-up resistor R4, the 5th pin links to each other with SPI1_SCK and connects the end of the 3rd pull-up resistor R5, the 7th pin links to each other with SPI1_MISO and connects the end of the 4th pull-up resistor R7, the 4th pin and VCC-3.3 power interface, the other end of the first pull-up resistor R3, the other end of the second pull-up resistor R4, the other end of the 3rd pull-up resistor R5, the other end of the 4th pull-up resistor R7 connects.

Debug i/f circuit is comprised of 2 * 4 row's pin JP1, and the 5th pin links to each other with TTL_RXD, and the 7th pin links to each other with TTL_TXD.

The beneficial effects of the utility model: design vehicle-mounted wireless network intelligent anti-theft system, like product GPS, GSM function have been inherited, prevent that self-propelled vehicle is directly stolen, increased the anti-storage battery pilferage that like product does not have, the function in the real-time locating query self-propelled vehicle of Google Earth geographic position, can prevent to a great extent that self-propelled vehicle is stolen.

Description of drawings:

Fig. 1 is the entire block diagram of the utility model patent;

Fig. 2 is the mu balanced circuit schematic diagram of the MIC29502WU of the utility model patent;

Fig. 3 is the LM1117 mu balanced circuit schematic diagram of the utility model patent;

Fig. 4 is the SIM900A schematic circuit diagram of the utility model patent;

Fig. 5 is the microphone interface circuit schematic diagram of the utility model patent;

Fig. 6 is the audio power amplifier circuit schematic diagram of the utility model patent;

Fig. 7 is the earphone interface circuit schematic diagram of the utility model patent;

Fig. 8 is the LED indicating circuit schematic diagram of the utility model patent;

Fig. 9 is the esd protection circuit schematic diagram of the utility model patent;

Figure 10 is the SIM schematic circuit diagram of the utility model patent;

Figure 11 is the NEO-6M modular circuit schematic diagram of the utility model patent;

Figure 12 is the TFT color screen liquid crystal schematic circuit diagram of the utility model patent;

Figure 13 is the STM32F103RBT6 minimum system schematic circuit diagram of the utility model patent;

Figure 14 is the W25X16 Flash schematic circuit diagram of the utility model patent;

Figure 15 is the Mini SD card schematic circuit diagram of the utility model patent;

Figure 16 is the debug i/f circuit schematic diagram of the utility model patent.

The specific embodiment

Below in conjunction with accompanying drawing modules in the utility model is done specific description.

As shown in Figure 1, a kind of wireless automotive networks intelligent anti-theft system comprises power management module 1, GSM/GPRS module 2, GPS module 3, Liquid Crystal Module 4, controller and peripheral module 5 thereof.Described power management module 1 comprises mu balanced circuit 1-1 take LM317 as core and the mu balanced circuit 1-2 take LM1117 as core, and described GSM/GPRS module 2 comprises SIM900A circuit 2-1, microphone interface circuit 2-2, audio power amplifier circuit 2-3, earphone interface circuit 2-4, LED indicating circuit 2-5, esd protection circuit 2-6 and SIM circuit 2-7; Described controller and peripheral module 5 thereof comprise STM32F103RBT6 minimum system circuit 5-1, W25X16 Flash circuit 5-2, Mini SD card circuit 5-3 and debug i/f circuit 5-4.

As shown in Figure 2, the mu balanced circuit take LM317 as core comprises LM317 power supply chip U2, potential device R10, the first Chip-R R8, the first magnetic bead B1, the second magnetic bead B2, diode D1, the first polar capacitor C14, the first filter capacitor C13, the second filter capacitor C15, the 3rd filter capacitor C16; The 1st pin of LM317 power supply chip U2 is connected with the sliding end of the end of potential device R10, potential device R10, the end of the first Chip-R R8; The 2nd pin of LM317 power supply chip U2 is connected with the end of the other end of the first Chip-R R8, the first magnetic bead B1, the anode of diode D1, the end of the first polar capacitor C14, the end of the second filter capacitor C15, the end of the 3rd filter capacitor C16; The other end of the first magnetic bead B1 links to each other with power interface VBAT, the negative electrode of diode D1 is connected with the end of the second magnetic bead B2, the other end of the second magnetic bead B2 links to each other with power interface VEXT, the other end ground connection of the other end of the other end of the first polar capacitor C14, the second filter capacitor C15, the 3rd filter capacitor C16; The 3rd pin of LM317 power supply chip U2 is connected the other end and the grounding connection of the other end of the first filter capacitor C13 and potential device R10 with an end, the power interface VIN of the first filter capacitor C13.

As shown in Figure 3, the mu balanced circuit take LM1117 as core comprises LM1117 voltage stabilizing chip L3 and the second polar capacitor C18; The 1st pin of LM1117 voltage stabilizing chip L3 is connected with power interface VIN, the 2nd pin of LM1117 voltage stabilizing chip L3 and an end and the grounding connection of the second polar capacitor C18, the 3rd pin of LM1117 voltage stabilizing chip L3 is connected with the other end of power interface VCC-3.3, the second polar capacitor C18.

As shown in Figure 4, the SIM900A circuit comprises SIM900A module SM1, SMA antennal interface RF2, the first matched resistance R15, the second matched resistance R16, the 3rd matched resistance R21, the second Chip-R R27, the first matching capacitance C25, the 4th filter capacitor C22, the 5th filter capacitor C23, the 6th filter capacitor C36, the 3rd polar capacitor C21; The 1st pin of SIM900A module SM1 is connected with the end of the 3rd matched resistance R21, the other end of the 3rd matched resistance R21 is connected with POWER_KEY, the 15th pin of SIM900A module SM1 links to each other with power interface VDD_EXT, the 17th of SIM900A module SM1,18,29,39,45,46,53,54,58,59,61,62,63,64,65 pin ground connection, the 19th pin meets MIC_N, the 20th pin meets MIC_P, the 21st pin meets SPK_P, the 22nd pin meets SPK_N, the 27th pin meets DBG_TXD, the 28th pin meets DBG_RXD, the 26th pin links to each other with power interface VCC-3.3, the 34th pin and SIM_PRECENCE, the end of the second Chip-R R27 links to each other, the other end of the second Chip-R R27 links to each other with power interface SIM_VDD, the 33rd pin meets SIM_RST, the 32nd pin meets SIM_CLK, the 31st pin meets SIM_DATA, No. 30 pin and SIM_VDD power supply, the end of the 6th filter capacitor C36 connects, the other end grounding connection of the 6th filter capacitor C36, the 52nd pin links to each other with NETLIGHT, the 55th pin and the 56th pin, the 57th pin, power interface VBAT, the end of the 3rd polar capacitor C21, the end of the 4th filter capacitor C22, the end of the 5th filter capacitor C23 connects, the other end of the 3rd polar capacitor C21, the other end of the 4th filter capacitor C22, the other end grounding connection of the 5th filter capacitor C23, the 60th pin links to each other with the end of the second matched resistance R16, the end of the other end of the second matched resistance R16 and the first matching capacitance C25, the end of the first matched resistance R15 links to each other, the other end of the first matched resistance R15 links to each other with SMA antennal interface RF2 the 5th pin, the other end of the first matching capacitance C25 and SMA antennal interface RF2 the 1st, 2,3,4 pin and grounding connection, the 66th pin meets STATUS.

As shown in Figure 5, microphone interface circuit comprises miaow head M2, the 7th filter capacitor C26, the 8th filter capacitor C27, the 9th filter capacitor C28, the tenth filter capacitor C29, the 11 filter capacitor C30, the 12 filter capacitor C31; An end and the grounding connection of the end of the 7th filter capacitor C26 and the 8th filter capacitor C27, the end of the other end of the 7th filter capacitor C26 and the 9th filter capacitor C28, the end of miaow head M2, the other end of the 8th filter capacitor C27, the end of the tenth filter capacitor C29, MIC_N connects, the end of the other end of the 9th filter capacitor C28 and the 11 filter capacitor C30, the other end of miaow head M2, the other end of the tenth filter capacitor C29, the end of the 12 filter capacitor C31, MIC_P links to each other, and the other end of the 11 filter capacitor C30 is connected with the other end of the 12 filter capacitor C31 and grounding connection.As shown in Figure 6, audio power amplifier circuit comprises LM4890 chip LM1, the 3rd Chip-R R28, the 4th matched resistance R31, the 5th matched resistance R33, the 6th matched resistance R34, the second matching capacitance C40, the 3rd matching capacitance C42, the 4th matching capacitance C43, the 13 filter capacitor C41, loudspeaker BUZZER1.The 1st pin of LM4890 chip LM1 is connected with SHUTDOWN, the end of the 2nd pin and the 3rd Chip-R R28, the end of the second matching capacitance C40 links to each other, the other end ground connection of the second matching capacitance C40, the 3rd pin of LM4890 chip LM1 and the other end of the 3rd Chip-R R28, the end of the 4th matched resistance R31 links to each other, the other end of the 4th matched resistance R31 links to each other with the end of the 3rd matching capacitance C42, the other end of the 3rd matching capacitance C42 links to each other with SPK_P, the end of the 4th pin of LM4890 chip LM1 and the 5th matched resistance R33, the end of the 6th matched resistance R34 links to each other, the other end of the 5th matched resistance R33 links to each other with the end of the 4th matching capacitance C43, the other end of the 4th matching capacitance C43 links to each other with SPK_N, the other end of the 5th pin and the 6th matched resistance R34, SPK_N_A, the 2nd pin of loudspeaker BUZZER1 links to each other, the 6th pin and power interface VIN, the end of the 13 filter capacitor C41 links to each other, the 7th pin of LM4890 chip LM1 and the other end and the grounding connection of the 13 filter capacitor C41, the 8th pin and the SPK_P_A of LM4890 chip LM1, the 1st pin of loudspeaker BUZZER1 links to each other.

As shown in Figure 7, earphone interface circuit comprises the 14 filter capacitor C32, the 15 filter capacitor C33, the 16 filter capacitor C34, the 17 filter capacitor C35, the 18 filter capacitor C37, the 19 filter capacitor C38, earphone inserter P1; The end of the 14 filter capacitor C32 and an end and the grounding connection of the 15 filter capacitor C33, the end of the other end of the 14 filter capacitor C32 and the 16 filter capacitor C43, the 4th pin of earphone inserter P1, the other end of the 15 filter capacitor C33, the end of the 17 filter capacitor C35, SPK_P connects, the end of the other end of the 16 filter capacitor C43 and the 18 filter capacitor C37, the 3rd pin of earphone inserter P1, the other end of the 17 filter capacitor C35, the end of the 19 filter capacitor C38, SPK_N connects, the 2nd pin of the other end of the 18 filter capacitor C37 and earphone inserter P1, the other end of the 19 filter capacitor C38 connects and grounding connection, and the 1st foot rest of earphone inserter P1 is empty.

As shown in Figure 8, the LED indicating circuit comprises the first aerotron Q1, the second aerotron Q3, the 3rd aerotron Q4, the first light-emitting diode DS2, the second light-emitting diode DS3, the 4th Chip-R R13, the 5th Chip-R R17, the 6th Chip-R R19, the 7th Chip-R R22, the 8th Chip-R R24, the 9th Chip-R R20, the tenth Chip-R R23, the 11 Chip-R R25, the first button S2; The first aerotron Q1 collecting electrode meets POWER_KEY, base stage links to each other with the end of the 4th Chip-R R13, the end of the 5th Chip-R R17, the other end of the 4th Chip-R R13 links to each other with the end of the first button S2, the other end of the first button S2 links to each other with power interface VEXT, and the emitter of the first aerotron Q1 is connected with the other end of the 5th Chip-R R17 and ground connection;

As shown in Figure 9, esd protection circuit comprises PESD3V3L5UV chip P2; The 1st, 3 pin of PESD3V3L5UV chip P2 are unsettled, the 2nd pin ground connection, and the 4th pin meets SIM_CLK_ESD, and the 5th pin meets SIM_RST_ESD, and the 6th pin meets SIM_DATA_ESD.

As shown in figure 10, the SIM circuit comprises SIM deck SIM2, the 7th matched resistance R29, the 8th matched resistance R30, the 9th matched resistance R32, the 20 filter capacitor C44.SIM deck SIM2 the 1st pin meets SIM_VDD, the 2nd pin connects the end of the 7th matched resistance R29, another termination SIM_RST of the 7th matched resistance R29, the 3rd pin connects the end of the 8th matched resistance R30, and the other end of the 8th matched resistance R30 links to each other with SIM_CLK, the 4th pin ground connection, the 6th pin connects the end of the 9th matched resistance R32, the end of the 20 filter capacitor C44, another termination SIM_DATA of the 9th matched resistance R32, the other end ground connection of the 20 filter capacitor C44, the 5th foot rest is empty.

Described GPS module is made of the circuit take the NEO-6M module as core.

As shown in figure 11, the circuit take the NEO-6M module as core comprises UBLOX_NEO_6M module U1, antenna SMA interface RF1, the tenth matched resistance R1, the first inductance L 1; The 24th, 13,12,10, the 7 pin ground connection of UBLOX_NEO_6M module U1,3 pin of the 20th pin connector JP1, the 21st pin connects 1 pin of connector JP1, and the 22nd, 23 pin meet VCC-3.3, and the 11st pin links to each other with the 5th pin of antenna SMA interface RF1, an end of the first inductance L 1; UBLOX_NEO_6M module U1 the 8th, 9 pin link to each other, and link to each other with the end of the tenth matched resistance R1, and the other end of the tenth matched resistance R1 links to each other with the other end of the first inductance L 1; The 1st, 2,3,4 of antenna SMA interface RF1 links to each other and ground connection; 1,2,3,4,5,6,14,15,16,17,18,19 foot rests of UBLOX_NEO_6M module U1 are empty.

As shown in figure 12, TFT color screen liquid crystal circuit is by TFT2.8 cun liquid crystal T1, the 21 filter capacitor C17, the 22 filter capacitor C20, the 5th matching capacitance C19, the 12 Chip-R R11, the 13 Chip-R R12; TFT2.8 cun liquid crystal T1 the 1st pin links to each other with the 40th pin of STM32F103RBT6 chip STM1, the 2nd pin links to each other with the 39th pin of STM32F103RBT6 chip STM1, the 3rd pin links to each other with the 38th pin of STM32F103RBT6 chip STM1, the 4th pin links to each other with the 37th pin of STM32F103RBT6 chip STM1, the 5th pin links to each other with the 7th pin of STM32F103RBT6 chip STM1, the 6th, 7,8,9,10,11,12,13,14,15,16,17,18,19,20,21 pins respectively with the 26th of STM32F103RBT6 chip STM1,27,28,55,56,57,58,59,61,62,29,30,33,34,35,36 pin link to each other, the 22nd, 26 pin grounding connections, the 23rd pin links to each other with the 53rd pin of STM32F103RBT6 chip STM1, the 24th pin is connected with power interface VCC-3.3, and connect the end of the 21 filter capacitor C17, the other end ground connection of the 21 filter capacitor C17; The 25th pin is connected with VCC-3.3, the 27th pin ground connection also links to each other with the end of the 5th matching capacitance C19, the other end of the 5th matching capacitance C19 links to each other with the end of the 12 Chip-R R11, the end of the 13 Chip-R R12, and the other end of the 12 Chip-R R11 links to each other with the 9th pin of STM32F103RBT6 chip STM1.The 28th pin links to each other with power supply VCC-5.0 and connects the end of the 22 filter capacitor C20, the other end ground connection of the 22 filter capacitor C20.The 29th pin links to each other with the 10th pin of STM32F103RBT6 chip STM1, the 30th pin links to each other with the 11st pin of STM32F103RBT6 chip STM1, the 31st pin links to each other with the other end of the 13 Chip-R R12, the 32nd pin is unsettled, the 2nd pin that the 33rd pin meets STM32F103RBT6 chip STM1 links to each other, and the 34th pin connects the 8th pin of STM32F103RBT6 chip STM1.

As shown in figure 13, STM32F103RBT6 minimum system circuit comprises STM32F103RBT6 chip STM1, the first shunt capacitance C3, the second shunt capacitance C4, the 3rd shunt capacitance C5, the 4th shunt capacitance C6, quadripolarity capacitor C 7, the 23 filter capacitor C1, the 24 filter capacitor C8, the 25 filter capacitor C11, the 26 filter capacitor C12, the 27 filter capacitor C2, the 28 filter capacitor C10, the first crystal oscillator X2, the second crystal oscillator X1, the 14 Chip-R R2, the 15 Chip-R R6, the 16 Chip-R R9, the second button S1, the second inductance L 2, the 3rd light-emitting diode DS1, connector JP2; The 3rd pin connects the end of the first shunt capacitance C3 and the end of the first crystal oscillator X2, and the other end of the first shunt capacitance C3 is connected and ground connection with the end of the second shunt capacitance C4, the end of the 3rd shunt capacitance C5, the end of the 4th shunt capacitance C6, the negative pole of quadripolarity capacitor C 7, the end of the 24 filter capacitor C8, the 12nd pin of STM32F103RBT6 chip STM1; The 4th pin connects the other end of the second shunt capacitance C4 and the other end of the first crystal oscillator X2; The 5th pin connects the other end of the 3rd shunt capacitance C5, the end of the 15 Chip-R R6, the end of the second crystal oscillator X1; The 6th pin connects the other end of the 4th shunt capacitance C6, the other end of the 15 Chip-R R6, the other end of the second crystal oscillator X1; The 7th pin connects the end of the 14 Chip-R R2, the end of the second button S1, the end of the 23 filter capacitor C1, another termination power interface VCC-3.3 of the 14 Chip-R R2, the other end of the second button S1 are connected with the other end of the 23 filter capacitor C1 and ground connection; The 13rd pin links to each other with the positive pole of quadripolarity capacitor C 7, the other end of the 24 filter capacitor C8, an end of the second inductance L 2, and the other end of the second inductance L 2 links to each other with the VCC-3.3 power interface; The 14th pin links to each other with PA0; The 15th pin links to each other with PA1; The 16th pin links to each other with 1 pin of W25X16 chips W 1; The 17th pin links to each other with SD_CS.The 18th pin is connected with the end of the 25 filter capacitor C11 and ground connection; The 19th pin links to each other with power supply VCC-3.3 and links to each other with the other end of the 25 filter capacitor C11; The 20th pin is connected with RESET_GSM; 21st, 22,23 pins are connected with 6,2,5 pin of W25X16 chips W 1 respectively; The 24th pin meets PC4; The 25th pin meets SHUTDOWN, and the 31st pin is connected with the end of the 26 filter capacitor C12 and ground connection; The 32nd pin links to each other with the other end of the 26 filter capacitor C12; The 41st pin connects the negative electrode of the 3rd light-emitting diode DS1, and the anode of the 3rd light-emitting diode DS1 connects the end of the 16 Chip-R R9, another termination power interface VCC-3.3 of the 16 Chip-R R9; 42nd, 43 pin are connected with 2,4 pin of connector JP1; The 48th pin meets an end and the power interface VCC-3.3 of the 28 filter capacitor C10, and the other end of the 28 filter capacitor C10 is connected with the 47th pin and ground connection; 51st, 52 are connected with 8,6 pin of connector JP1; The 64th pin links to each other with the end of power interface VCC-3.3, the 27 filter capacitor C2, the other end of the 27 filter capacitor C2 is connected with the 63rd pin and ground connection, the 1st pin is unsettled, the 44th pin meets PA11, and the 45th pin meets PA12, and the 46th pin meets PA13, the 49th pin meets PA14, the 50th pin meets PA15, and the 54th pin meets PD2, and the 60th pin meets BOOT0.

As shown in figure 14, W25X16 Flash circuit is comprised of W25X16 chips W 1 and the 29 filter capacitor C9.The 3rd pin meets VCC-3.3, the 4th pin ground connection, and the 7th, 8 pins connect the end of VCC-3.3 power interface, the 29 filter capacitor C9, the other end ground connection of the 29 filter capacitor C9.

As shown in figure 15, Mini SD card circuit is comprised of Mini SD card deck SD1, the first pull-up resistor R3, the second pull-up resistor R4, the 3rd pull-up resistor R5, four pull-up resistors of the 4th pull-up resistor R7.Mini SD card deck SD1 the 1st, 9 pins are unsettled, the 6th, 8,10,11,12,13 ground connection, the 2nd pin links to each other with SD_CS and connects the end of the first pull-up resistor R3, the 3rd pin links to each other with SPI1_MOSI and connects the end of the second pull-up resistor R4, the 5th pin links to each other with SPI1_SCK and connects the end of the 3rd pull-up resistor R5, the 7th pin links to each other with SPI1_MISO and connects the end of the 4th pull-up resistor R7, the 4th pin and VCC-3.3 power interface, the other end of the first pull-up resistor R3, the other end of the second pull-up resistor R4, the other end of the 3rd pull-up resistor R5, the other end of the 4th pull-up resistor R7 connects.

As shown in figure 16, debug i/f circuit is comprised of 2 * 4 row's pin JP1, and the 5th pin links to each other with TTL_RXD, and the 7th pin links to each other with TTL_TXD.

Onboard wireless network intelligence anti-theft system workflow is as follows: whole system is comprised of data center (upper computer) and self-propelled vehicle client.The system master chip is that kernel is the STM32F103 series monolithic of Cortex-M3, and external equipment comprises: the SIM900A(GSM/GPRS module), the NEO-6M(GPS module), Mini SD memory card.SIM900A, NEO-6M and micro controller system adopt serial communication, and GPS sends the locating data bag to micro controller system by the serial ports 1 of micro controller system, and micro controller system is crossed serial ports 3 with the actv. information exchange and sent to the SIM900A module through behind the Data Analysis; Mini SD memory card is used for storing in garage's process necessary data, carries out data exchange with form and the micro controller system of 4 line SPI.For guaranteeing commonality and the portability of software, system adopts the senior applicational language of MDK micro controller system to write.Software system comprise serial port drive layer, communication and application layer.The serial port drive layer at first carries out initialization according to the characteristic of SIM900A module to the RS232 serial port and comprises and serial ports mode of operation baud rate initializing variable parameter is set and zone bit this paper communication speed is made as 9600bps.Transmission of messages and application layer send AT instructions control SIM900A modules by serial ports 2 and finish setting and the telephone number on the network entry reading SIM card to the SIM900A module, send note, receive the functions such as note and note data management.Serial ports 1 receives the gps data bag, and carries out data packet according to the NMEA standard and resolve.Data center (upper computer) receives the Google Earth upper computer that data communication device is crossed secondary API exploitation, accurately shows geographical location information.

Onboard wireless network intelligence anti-theft system is achieved as follows function:

1. prevent directly stealing self-propelled vehicle.Be moved the distance of 50M because certain external factor causes self-propelled vehicle, realize the alarm of super scope note, the information of GPS location is sent to user's computer by GSM.

2. prevent malice cutoff die block power supply.Module is powered separately, keeps the system works ability.Avoided maliciously cutting off the storage battery car power supply this product module can't be worked, this is that like product does not have.

3. by using the Socket monitoring technique of C# exploitation, receive the GPRS data, and resolve, the geographic position is presented on the Google Earth of API secondary development, help the car owner in time to give self-propelled vehicle for change.

4. the user can arrange module parameter by mobile phone or computer upper computer.

Claims

1. the wireless automotive networks intelligent anti-theft system comprises power management module, GSM/GPRS module, GPS module, Liquid Crystal Module, controller and peripheral module thereof;

It is characterized in that: described power management module comprises that LM317 is mu balanced circuit and the mu balanced circuit take LM1117 as core of core;

Mu balanced circuit take LM317 as core comprises LM317 power supply chip U2, potential device R10, the first Chip-R R8, the first magnetic bead B1, the second magnetic bead B2, diode D1, the first polar capacitor C14, the first filter capacitor C13, the second filter capacitor C15, the 3rd filter capacitor C16; The 1st pin of LM317 power supply chip U2 is connected with the sliding end of the end of potential device R10, potential device R10, the end of the first Chip-R R8; The 2nd pin of LM317 power supply chip U2 is connected with the end of the other end of the first Chip-R R8, the first magnetic bead B1, the anode of diode D1, the end of the first polar capacitor C14, the end of the second filter capacitor C15, the end of the 3rd filter capacitor C16; The other end of the first magnetic bead B1 links to each other with power interface VBAT, the negative electrode of diode D1 is connected with the end of the second magnetic bead B2, the other end of the second magnetic bead B2 links to each other with power interface VEXT, the other end ground connection of the other end of the other end of the first polar capacitor C14, the second filter capacitor C15, the 3rd filter capacitor C16; The 3rd pin of LM317 power supply chip U2 is connected the other end and the grounding connection of the other end of the first filter capacitor C13 and potential device R10 with an end, the power interface VIN of the first filter capacitor C13;

Mu balanced circuit take LM1117 as core comprises LM1117 voltage stabilizing chip L3 and the second polar capacitor C18; The 1st pin of LM1117 voltage stabilizing chip L3 is connected with power interface VIN, the 2nd pin of LM1117 voltage stabilizing chip L3 and an end and the grounding connection of the second polar capacitor C18, the 3rd pin of LM1117 voltage stabilizing chip L3 is connected with the other end of power interface VCC-3.3, the second polar capacitor C18;

Described GSM/GPRS module comprises SIM900A circuit, microphone interface circuit, audio power amplifier circuit, earphone interface circuit, LED indicating circuit, esd protection circuit, SIM circuit;

The SIM900A circuit comprises SIM900A module SM1, SMA antennal interface RF2, the first matched resistance R15, the second matched resistance R16, the 3rd matched resistance R21, the second Chip-R R27, the first matching capacitance C25, the 4th filter capacitor C22, the 5th filter capacitor C23, the 6th filter capacitor C36, the 3rd polar capacitor C21; The 1st pin of SIM900A module SM1 is connected with the end of the 3rd matched resistance R21, the other end of the 3rd matched resistance R21 is connected with POWER_KEY, the 15th pin of SIM900A module SM1 links to each other with power interface VDD_EXT, the 17th of SIM900A module SM1,18,29,39,45,46,53,54,58,59,61,62,63,64,65 pin ground connection, the 19th pin meets MIC_N, the 20th pin meets MIC_P, the 21st pin meets SPK_P, the 22nd pin meets SPK_N, the 27th pin meets DBG_TXD, the 28th pin meets DBG_RXD, the 26th pin links to each other with power interface VCC-3.3, the 34th pin and SIM_PRECENCE, the end of the second Chip-R R27 links to each other, the other end of the second Chip-R R27 links to each other with power interface SIM_VDD, the 33rd pin meets SIM_RST, the 32nd pin meets SIM_CLK, the 31st pin meets SIM_DATA, No. 30 pin and SIM_VDD power supply, the end of the 6th filter capacitor C36 connects, the other end grounding connection of the 6th filter capacitor C36, the 52nd pin links to each other with NETLIGHT, the 55th pin and the 56th pin, the 57th pin, power interface VBAT, the end of the 3rd polar capacitor C21, the end of the 4th filter capacitor C22, the end of the 5th filter capacitor C23 connects, the other end of the 3rd polar capacitor C21, the other end of the 4th filter capacitor C22, the other end grounding connection of the 5th filter capacitor C23, the 60th pin links to each other with the end of the second matched resistance R16, the end of the other end of the second matched resistance R16 and the first matching capacitance C25, the end of the first matched resistance R15 links to each other, the other end of the first matched resistance R15 links to each other with SMA antennal interface RF2 the 5th pin, the other end of the first matching capacitance C25 and SMA antennal interface RF2 the 1st, 2,3,4 pin and grounding connection, the 66th pin meets STATUS;

Microphone interface circuit comprises miaow head M2, the 7th filter capacitor C26, the 8th filter capacitor C27, the 9th filter capacitor C28, the tenth filter capacitor C29, the 11 filter capacitor C30, the 12 filter capacitor C31; An end and the grounding connection of the end of the 7th filter capacitor C26 and the 8th filter capacitor C27, the end of the other end of the 7th filter capacitor C26 and the 9th filter capacitor C28, the end of miaow head M2, the other end of the 8th filter capacitor C27, the end of the tenth filter capacitor C29, MIC_N connects, the end of the other end of the 9th filter capacitor C28 and the 11 filter capacitor C30, the other end of miaow head M2, the other end of the tenth filter capacitor C29, the end of the 12 filter capacitor C31, MIC_P links to each other, and the other end of the 11 filter capacitor C30 is connected with the other end of the 12 filter capacitor C31 and grounding connection; Audio power amplifier circuit comprises LM4890 chip LM1, the 3rd Chip-R R28, the 4th matched resistance R31, the 5th matched resistance R33, the 6th matched resistance R34, the second matching capacitance C40, the 3rd matching capacitance C42, the 4th matching capacitance C43, the 13 filter capacitor C41, loudspeaker BUZZER1; The 1st pin of LM4890 chip LM1 is connected with SHUTDOWN, the end of the 2nd pin and the 3rd Chip-R R28, the end of the second matching capacitance C40 links to each other, the other end ground connection of the second matching capacitance C40, the 3rd pin of LM4890 chip LM1 and the other end of the 3rd Chip-R R28, the end of the 4th matched resistance R31 links to each other, the other end of the 4th matched resistance R31 links to each other with the end of the 3rd matching capacitance C42, the other end of the 3rd matching capacitance C42 links to each other with SPK_P, the end of the 4th pin of LM4890 chip LM1 and the 5th matched resistance R33, the end of the 6th matched resistance R34 links to each other, the other end of the 5th matched resistance R33 links to each other with the end of the 4th matching capacitance C43, the other end of the 4th matching capacitance C43 links to each other with SPK_N, the other end of the 5th pin and the 6th matched resistance R34, SPK_N_A, the 2nd pin of loudspeaker BUZZER1 links to each other, the 6th pin and power interface VIN, the end of the 13 filter capacitor C41 links to each other, the 7th pin of LM4890 chip LM1 and the other end and the grounding connection of the 13 filter capacitor C41, the 8th pin and the SPK_P_A of LM4890 chip LM1, the 1st pin of loudspeaker BUZZER1 links to each other;

Earphone interface circuit comprises the 14 filter capacitor C32, the 15 filter capacitor C33, the 16 filter capacitor C34, the 17 filter capacitor C35, the 18 filter capacitor C37, the 19 filter capacitor C38, earphone inserter P1; The end of the 14 filter capacitor C32 and an end and the grounding connection of the 15 filter capacitor C33, the end of the other end of the 14 filter capacitor C32 and the 16 filter capacitor C43, the 4th pin of earphone inserter P1, the other end of the 15 filter capacitor C33, the end of the 17 filter capacitor C35, SPK_P connects, the end of the other end of the 16 filter capacitor C43 and the 18 filter capacitor C37, the 3rd pin of earphone inserter P1, the other end of the 17 filter capacitor C35, the end of the 19 filter capacitor C38, SPK_N connects, the 2nd pin of the other end of the 18 filter capacitor C37 and earphone inserter P1, the other end of the 19 filter capacitor C38 connects and grounding connection, and the 1st foot rest of earphone inserter P1 is empty;

The collecting electrode of the 3rd aerotron Q4 links to each other with the negative electrode of the second light-emitting diode DS3, the anode of the second light-emitting diode DS3 links to each other with the end of the 9th Chip-R R20, the other end of the 9th Chip-R R20 links to each other with power interface VEXT, the base stage of the second aerotron Q3 links to each other with the end of the tenth Chip-R R23, the end of the 11 Chip-R R25, and the other end of the tenth Chip-R R23 links to each other with NETLIGHT; The emitter of the 3rd aerotron Q3 is connected with the other end of the 11 Chip-R R25 and ground connection;

Esd protection circuit comprises PESD3V3L5UV chip P2; The 1st, 3 pin of PESD3V3L5UV chip P2 are unsettled, the 2nd pin ground connection, and the 4th pin meets SIM_CLK_ESD, and the 5th pin meets SIM_RST_ESD, and the 6th pin meets SIM_DATA_ESD;

The SIM circuit comprises SIM deck SIM2, the 7th matched resistance R29, the 8th matched resistance R30, the 9th matched resistance R32, the 20 filter capacitor C44; SIM deck SIM2 the 1st pin meets SIM_VDD, the 2nd pin connects the end of the 7th matched resistance R29, another termination SIM_RST of the 7th matched resistance R29, the 3rd pin connects the end of the 8th matched resistance R30, and the other end of the 8th matched resistance R30 links to each other with SIM_CLK, the 4th pin ground connection, the 6th pin connects the end of the 9th matched resistance R32, the end of the 20 filter capacitor C44, another termination SIM_DATA of the 9th matched resistance R32, the other end ground connection of the 20 filter capacitor C44, the 5th foot rest is empty;

Described GPS module is made of the circuit take the NEO-6M module as core;

Circuit take the NEO-6M module as core comprises UBLOX_NEO_6M module U1, antenna SMA interface RF1, the tenth matched resistance R1, the first inductance L 1; The 24th, 13,12,10, the 7 pin ground connection of UBLOX_NEO_6M module U1,3 pin of the 20th pin connector JP1, the 21st pin connects 1 pin of connector JP1, and the 22nd, 23 pin meet VCC-3.3, and the 11st pin links to each other with the 5th pin of antenna SMA interface RF1, an end of the first inductance L 1; UBLOX_NEO_6M module U1 the 8th, 9 pin link to each other, and link to each other with the end of the tenth matched resistance R1, and the other end of the tenth matched resistance R1 links to each other with the other end of the first inductance L 1; The 1st, 2,3,4 of antenna SMA interface RF1 links to each other and ground connection; 1,2,3,4,5,6,14,15,16,17,18,19 foot rests of UBLOX_NEO_6M module U1 are empty;

Described Liquid Crystal Module is made of TFT color screen liquid crystal circuit;

TFT color screen liquid crystal circuit is by TFT2.8 cun liquid crystal T1, the 21 filter capacitor C17, the 22 filter capacitor C20, the 5th matching capacitance C19, the 12 Chip-R R11, the 13 Chip-R R12; TFT2.8 cun liquid crystal T1 the 1st pin links to each other with the 40th pin of STM32F103RBT6 chip STM1, the 2nd pin links to each other with the 39th pin of STM32F103RBT6 chip STM1, the 3rd pin links to each other with the 38th pin of STM32F103RBT6 chip STM1, the 4th pin links to each other with the 37th pin of STM32F103RBT6 chip STM1, the 5th pin links to each other with the 7th pin of STM32F103RBT6 chip STM1, the 6th, 7,8,9,10,11,12,13,14,15,16,17,18,19,20,21 pins respectively with the 26th of STM32F103RBT6 chip STM1,27,28,55,56,57,58,59,61,62,29,30,33,34,35,36 pin link to each other, the 22nd, 26 pin grounding connections, the 23rd pin links to each other with the 53rd pin of STM32F103RBT6 chip STM1, the 24th pin is connected with power interface VCC-3.3, and connect the end of the 21 filter capacitor C17, the other end ground connection of the 21 filter capacitor C17; The 25th pin is connected with VCC-3.3, the 27th pin ground connection also links to each other with the end of the 5th matching capacitance C19, the other end of the 5th matching capacitance C19 links to each other with the end of the 12 Chip-R R11, the end of the 13 Chip-R R12, and the other end of the 12 Chip-R R11 links to each other with the 9th pin of STM32F103RBT6 chip STM1; The 28th pin links to each other with power supply VCC-5.0 and connects the end of the 22 filter capacitor C20, the other end ground connection of the 22 filter capacitor C20; The 29th pin links to each other with the 10th pin of STM32F103RBT6 chip STM1, the 30th pin links to each other with the 11st pin of STM32F103RBT6 chip STM1, the 31st pin links to each other with the other end of the 13 Chip-R R12, the 32nd pin is unsettled, the 2nd pin that the 33rd pin meets STM32F103RBT6 chip STM1 links to each other, and the 34th pin connects the 8th pin of STM32F103RBT6 chip STM1;

Described controller and peripheral module thereof are made of STM32F103RBT6 minimum system circuit, W25X16 Flash circuit, Mini SD card circuit, debug i/f circuit;

STM32F103RBT6 minimum system circuit comprises STM32F103RBT6 chip STM1, the first shunt capacitance C3, the second shunt capacitance C4, the 3rd shunt capacitance C5, the 4th shunt capacitance C6, quadripolarity capacitor C 7, the 23 filter capacitor C1, the 24 filter capacitor C8, the 25 filter capacitor C11, the 26 filter capacitor C12, the 27 filter capacitor C2, the 28 filter capacitor C10, the first crystal oscillator X2, the second crystal oscillator X1, the 14 Chip-R R2, the 15 Chip-R R6, the 16 Chip-R R9, the second button S1, the second inductance L 2, the 3rd light-emitting diode DS1, connector JP2; The 3rd pin connects the end of the first shunt capacitance C3 and the end of the first crystal oscillator X2, and the other end of the first shunt capacitance C3 is connected and ground connection with the end of the second shunt capacitance C4, the end of the 3rd shunt capacitance C5, the end of the 4th shunt capacitance C6, the negative pole of quadripolarity capacitor C 7, the end of the 24 filter capacitor C8, the 12nd pin of STM32F103RBT6 chip STM1; The 4th pin connects the other end of the second shunt capacitance C4 and the other end of the first crystal oscillator X2; The 5th pin connects the other end of the 3rd shunt capacitance C5, the end of the 15 Chip-R R6, the end of the second crystal oscillator X1; The 6th pin connects the other end of the 4th shunt capacitance C6, the other end of the 15 Chip-R R6, the other end of the second crystal oscillator X1; The 7th pin connects the end of the 14 Chip-R R2, the end of the second button S1, the end of the 23 filter capacitor C1, another termination power interface VCC-3.3 of the 14 Chip-R R2, the other end of the second button S1 are connected with the other end of the 23 filter capacitor C1 and ground connection; The 13rd pin links to each other with the positive pole of quadripolarity capacitor C 7, the other end of the 24 filter capacitor C8, an end of the second inductance L 2, and the other end of the second inductance L 2 links to each other with the VCC-3.3 power interface; The 14th pin links to each other with PA0; The 15th pin links to each other with PA1; The 16th pin links to each other with 1 pin of W25X16 chips W 1; The 17th pin links to each other with SD_CS; The 18th pin is connected with the end of the 25 filter capacitor C11 and ground connection; The 19th pin links to each other with power supply VCC-3.3 and links to each other with the other end of the 25 filter capacitor C11; The 20th pin is connected with RESET_GSM; 21st, 22,23 pins are connected with 6,2,5 pin of W25X16 chips W 1 respectively; The 24th pin meets PC4; The 25th pin meets SHUTDOWN, and the 31st pin is connected with the end of the 26 filter capacitor C12 and ground connection; The 32nd pin links to each other with the other end of the 26 filter capacitor C12; The 41st pin connects the negative electrode of the 3rd light-emitting diode DS1, and the anode of the 3rd light-emitting diode DS1 connects the end of the 16 Chip-R R9, another termination power interface VCC-3.3 of the 16 Chip-R R9; 42nd, 43 pin are connected with 2,4 pin of connector JP1; The 48th pin meets an end and the power interface VCC-3.3 of the 28 filter capacitor C10, and the other end of the 28 filter capacitor C10 is connected with the 47th pin and ground connection; 51st, 52 are connected with 8,6 pin of connector JP1; The 64th pin links to each other with the end of power interface VCC-3.3, the 27 filter capacitor C2, the other end of the 27 filter capacitor C2 is connected with the 63rd pin and ground connection, the 1st pin is unsettled, the 44th pin meets PA11, and the 45th pin meets PA12, and the 46th pin meets PA13, the 49th pin meets PA14, the 50th pin meets PA15, and the 54th pin meets PD2, and the 60th pin meets BOOT0;

1 pin and 2 pin of connector JP2 meet power interface VCC-3.3, and 3 pin connect 28 pin of STM32F103RBT6 chip STM1, and 4 pin connect 60 pin of STM32F103RBT6 chip STM1,5 pin and 6 pin ground connection;

W25X16 Flash circuit is comprised of W25X16 chips W 1 and the 29 filter capacitor C9; The 3rd pin meets VCC-3.3, the 4th pin ground connection, and the 7th, 8 pins connect the end of VCC-3.3 power interface, the 29 filter capacitor C9, the other end ground connection of the 29 filter capacitor C9;

Mini SD card circuit is comprised of Mini SD card deck SD1, the first pull-up resistor R3, the second pull-up resistor R4, the 3rd pull-up resistor R5, four pull-up resistors of the 4th pull-up resistor R7; Mini SD card deck SD1 the 1st, 9 pins are unsettled, the 6th, 8,10,11,12,13 ground connection, the 2nd pin links to each other with SD_CS and connects the end of the first pull-up resistor R3, the 3rd pin links to each other with SPI1_MOSI and connects the end of the second pull-up resistor R4, the 5th pin links to each other with SPI1_SCK and connects the end of the 3rd pull-up resistor R5, the 7th pin links to each other with SPI1_MISO and connects the end of the 4th pull-up resistor R7, the 4th pin and VCC-3.3 power interface, the other end of the first pull-up resistor R3, the other end of the second pull-up resistor R4, the other end of the 3rd pull-up resistor R5, the other end of the 4th pull-up resistor R7 connects;