CN102975688B - Wireless vehicle-mounted network intelligent anti-theft system - Google Patents
Wireless vehicle-mounted network intelligent anti-theft system Download PDFInfo
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Abstract
The invention discloses a wireless vehicle-borne network intelligent anti-theft system. Functions of existing teleology products just can give out a warning when an automotive vehicle is stolen, real-time tracking vehicle moving path cannot be achieved, and the stolen automotive vehicle cannot even be tracked and located accurately. The wireless vehicle-borne network intelligent anti-theft system comprises a power supply management module, a global system for mobile communication (GSM)/general packet radio service (GPRS) module, a global position system (GPS) module, a liquid crystal module, a controller and a peripheral equipment module. The wireless vehicle-borne network intelligent anti-theft system inherits functions of like products of GPS and GSM, prevents the automotive vehicle from being stolen directly, adds functions of a storage battery prevented from being stolen and Google Earth real-time location inquiring automotive vehicle geographic position of the like products, and can prevent the automotive vehicle from being stolen to a great extent.
Description
Technical field
Product of the present invention belongs to embedded system technology field, is specifically related to a kind of wireless automotive networks intelligent anti-theft system.
Background technology
Along with the raising of socioeconomic development, living standards of the people, private car has entered into the life of people.The automobile industry of annual upper trillion dollars is one of backbone industry of world economy, can penetrate into the every aspect of society life without any a kind of industrial goods as automobile.It, with the continuous renewal of its technology and product, thoroughly changes and improves life style and the quality of life of people.Simultaneously a new social concern creates: use the number of self-propelled vehicle constantly to increase, and self-propelled vehicle steals case cumulative year after year.By visiting traffic office of Zhejiang Province, we recognize, Zhejiang Province has more than 350 ten thousand self-propelled vehiclees stolen (containing Electrical Bicycle) every year.Through consulting related data and literature search and investigating on the spot, we find that anti-theft device for motor vehicle has in the market " GPS+GSM+GPRS storage battery car steady arm ", " the special GPSONE steady arm of motor bike, storage battery car, power car " etc., but the function of these products is all send alarm when self-propelled vehicle goes adrift, can not real-time tracking vehicle mobile route, more can not follow the tracks of and the accurate stolen self-propelled vehicle in location.And the said goods price is even higher in 700-800 unit, also has a kind of fingerprint recognition system price more up to 2000 yuan.By contrast, this kind of product price is obviously higher, is difficult to by masses are accepted.Design vehicle-mounted wireless network intelligent anti-theft system, inherit like product GPS, GSM function, prevent self-propelled vehicle directly stolen, novelty adds that the anti-storage battery that like product do not have is stolen, the function in Google Earth real-time locating query self-propelled vehicle geographic position again, can self-propelled vehicle be prevented to a great extent stolen.The anti-joyride device this project developed is promoted, and reduce engine motor-car is stolen case and occurred, and realizes the benign cycle of society.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, propose a kind of wireless automotive networks intelligent anti-theft system.
A kind of wireless automotive networks intelligent anti-theft system comprises power management module, GSM/GPRS module, GPS module, Liquid Crystal Module, controller and peripheral module thereof.
Described power management module comprises mu balanced circuit that LM317 is core and take LM1117 as the mu balanced circuit of core.
Be that the mu balanced circuit of core comprises LM317 power supply chip U2, potential device R10, the first Chip-R R8, the first magnetic bead B1, the second magnetic bead B2, diode D1, the first polar capacitor C14, the first filter capacitor C13, the second filter capacitor C15, the 3rd filter capacitor C16 with LM317; 1st pin of LM317 power supply chip U2 is connected with the sliding end of one end of potential device R10, potential device R10, one end of the first Chip-R R8; One end of 2nd pin of LM317 power supply chip U2 and the other end of the first Chip-R R8, the first magnetic bead B1, the anode of diode D1, one end of the first polar capacitor C14, one end of the second filter capacitor C15, one end of the 3rd filter capacitor C16 are connected; The other end of the first magnetic bead B1 is connected with power interface VBAT, the negative electrode of diode D1 is connected with one end of the second magnetic bead B2, the other end of the second magnetic bead B2 is connected with power interface VEXT, the other end ground connection of the other end of the first polar capacitor C14, the other end of the second filter capacitor C15, the 3rd filter capacitor C16; 3rd pin of LM317 power supply chip U2 is connected with one end of the first filter capacitor C13, power interface VIN, the other end of the first filter capacitor C13 and the other end of potential device R10 grounding connection.
Be that the mu balanced circuit of core comprises LM1117 voltage stabilizing chip L3 and the second polar capacitor C18 with LM1117; 1st pin of LM1117 voltage stabilizing chip L3 is connected with power interface VIN, 2nd pin of LM1117 voltage stabilizing chip L3 and one end of the second polar capacitor C18 grounding connection, the 3rd pin of LM1117 voltage stabilizing chip L3 is connected with the other end of power interface VCC-3.3, the second polar capacitor C18.
Described GSM/GPRS module comprises SIM900A circuit, microphone interface circuit, audio power amplifier circuit, earphone interface circuit, LED indicating circuit, esd protection circuit, SIM circuit.
SIM900A circuit comprises SIM900A module SM1, SMA antennal interface RF2, the first matched resistance R15, the second matched resistance R16, the 3rd matched resistance R21, the second Chip-R R27, the first matching capacitance C25, the 4th filter capacitor C22, the 5th filter capacitor C23, the 6th filter capacitor C36, the 3rd polar capacitor C21, 1st pin of SIM900A module SM1 is connected with one end of the 3rd matched resistance R21, and the other end of the 3rd matched resistance R21 is connected with POWER_KEY, and the 15th pin of SIM900A module SM1 is connected with power interface VDD_EXT, the 17th of SIM900A module SM1, 18, 29, 39, 45, 46, 53, 54, 58, 59, 61, 62, 63, 64, 65 pin ground connection, the 19th pin meets MIC_N, and the 20th pin meets MIC_P, and the 21st pin meets SPK_P, and the 22nd pin meets SPK_N, and the 27th pin meets DBG_TXD, and the 28th pin meets DBG_RXD, and the 26th pin is connected with power interface VCC-3.3, the 34th pin and SIM_PRECENCE, one end of second Chip-R R27 is connected, and the other end of the second Chip-R R27 is connected with power interface SIM_VDD, and the 33rd pin meets SIM_RST, and the 32nd pin meets SIM_CLK, and the 31st pin meets SIM_DATA, No. 30 pin and SIM_VDD power supply, one end of 6th filter capacitor C36 connects, the other end grounding connection of the 6th filter capacitor C36, and the 52nd pin is connected with NETLIGHT, the 55th pin and the 56th pin, 57th pin, power interface VBAT, one end of 3rd polar capacitor C21, one end of 4th filter capacitor C22, one end of 5th filter capacitor C23 connects, the other end of the 3rd polar capacitor C21, the other end of the 4th filter capacitor C22, the other end grounding connection of the 5th filter capacitor C23, the 60th pin is connected with one end of the second matched resistance R16, the other end of the second matched resistance R16 and one end of the first matching capacitance C25, one end of first matched resistance R15 is connected, and the other end of the first matched resistance R15 is connected with SMA antennal interface RF2 the 5th pin, the other end of the first matching capacitance C25 and SMA antennal interface RF2 the 1st, 2, 3, 4 pin grounding connection, the 66th pin meets STATUS.
Microphone interface circuit comprises miaow head M2, the 7th filter capacitor C26, the 8th filter capacitor C27, the 9th filter capacitor C28, the tenth filter capacitor C29, the 11 filter capacitor C30, the 12 filter capacitor C31, one end of 7th filter capacitor C26 and one end of the 8th filter capacitor C27 grounding connection, the other end of the 7th filter capacitor C26 and one end of the 9th filter capacitor C28, one end of miaow head M2, the other end of the 8th filter capacitor C27, one end of tenth filter capacitor C29, MIC_N connects, the other end of the 9th filter capacitor C28 and one end of the 11 filter capacitor C30, the other end of miaow head M2, the other end of the tenth filter capacitor C29, one end of 12 filter capacitor C31, MIC_P is connected, the other end of the 11 filter capacitor C30 is connected with the other end of the 12 filter capacitor C31 and grounding connection.Audio power amplifier circuit comprises LM4890 chip LM1, the 3rd Chip-R R28, the 4th matched resistance R31, the 5th matched resistance R33, the 6th matched resistance R34, the second matching capacitance C40, the 3rd matching capacitance C42, the 4th matching capacitance C43, the 13 filter capacitor C41, loudspeaker BUZZER1.1st pin of LM4890 chip LM1 is connected with SHUTDOWN, one end of 2nd pin and the 3rd Chip-R R28, one end of second matching capacitance C40 is connected, the other end ground connection of the second matching capacitance C40, 3rd pin of LM4890 chip LM1 and the other end of the 3rd Chip-R R28, one end of 4th matched resistance R31 is connected, the other end of the 4th matched resistance R31 is connected with one end of the 3rd matching capacitance C42, the other end of the 3rd matching capacitance C42 is connected with SPK_P, 4th pin of LM4890 chip LM1 and one end of the 5th matched resistance R33, one end of 6th matched resistance R34 is connected, the other end of the 5th matched resistance R33 is connected with one end of the 4th matching capacitance C43, the other end of the 4th matching capacitance C43 is connected with SPK_N, the other end of the 5th pin and the 6th matched resistance R34, SPK_N_A, 2nd pin of loudspeaker BUZZER1 is connected, 6th pin and power interface VIN, one end of 13 filter capacitor C41 is connected, 7th pin of LM4890 chip LM1 and the other end of the 13 filter capacitor C41 grounding connection, 8th pin and the SPK_P_A of LM4890 chip LM1, 1st pin of loudspeaker BUZZER1 is connected.
Earphone interface circuit comprises the 14 filter capacitor C32, the 15 filter capacitor C33, the 16 filter capacitor C34, the 17 filter capacitor C35, the 18 filter capacitor C37, the 19 filter capacitor C38, earphone inserter P1, one end of 14 filter capacitor C32 and one end of the 15 filter capacitor C33 grounding connection, the other end of the 14 filter capacitor C32 and one end of the 16 filter capacitor C43, 4th pin of earphone inserter P1, the other end of the 15 filter capacitor C33, one end of 17 filter capacitor C35, SPK_P connects, the other end of the 16 filter capacitor C43 and one end of the 18 filter capacitor C37, 3rd pin of earphone inserter P1, the other end of the 17 filter capacitor C35, one end of 19 filter capacitor C38, SPK_N connects, the other end of the 18 filter capacitor C37 and the 2nd pin of earphone inserter P1, the other end of the 19 filter capacitor C38 connects and grounding connection, 1st foot rest of earphone inserter P1 is empty.
LED indicating circuit comprises the first aerotron Q1, the second aerotron Q3, the 3rd aerotron Q4, the first light-emitting diode DS2, the second light-emitting diode DS3, the 4th Chip-R R13, the 5th Chip-R R17, the 6th Chip-R R19, the 7th Chip-R R22, the 8th Chip-R R24, the 9th Chip-R R20, the tenth Chip-R R23, the 11 Chip-R R25, the first button S2; First aerotron Q1 collecting electrode meets POWER_KEY, base stage is connected with one end of the 4th Chip-R R13, one end of the 5th Chip-R R17, the other end of the 4th Chip-R R13 is connected with one end of the first button S2, the other end of the first button S2 is connected with power interface VEXT, and the emitter of the first aerotron Q1 is connected with the other end of the 5th Chip-R R17 and ground connection;
The collecting electrode of the second aerotron Q3 is connected with the negative electrode of the first light-emitting diode DS2, and the anode of the first light-emitting diode DS2 is connected with one end of the 6th Chip-R R19, and the other end of the 6th Chip-R R19 is connected with power interface VEXT; The base stage of the second aerotron Q3 is connected with one end of one end of the 7th Chip-R R22, the 8th Chip-R R24, the other end of the 7th Chip-R R22 is connected with STATUS, and the emitter of the second aerotron Q3 is connected with the other end of the 8th Chip-R R24 and ground connection;
The collecting electrode of the 3rd aerotron Q4 is connected with the negative electrode of the second light-emitting diode DS3, the anode of the second light-emitting diode DS3 is connected with one end of the 9th Chip-R R20, the other end of the 9th Chip-R R20 is connected with power interface VEXT, the base stage of the second aerotron Q3 is connected with one end of the tenth Chip-R R23, one end of the 11 Chip-R R25, and the other end of the tenth Chip-R R23 is connected with NETLIGHT; The emitter of the 3rd aerotron Q3 is connected with the other end of the 11 Chip-R R25 and ground connection.
Esd protection circuit comprises PESD3V3L5UV chip P2; PESD3V3L5UV chip P2 the 1st, 3 pin are unsettled, the 2nd pin ground connection, the 4th pin meets SIM_CLK_ESD, and the 5th pin meets SIM_RST_ESD, and the 6th pin meets SIM_DATA_ESD.
SIM circuit comprises SIM deck SIM2, the 7th matched resistance R29, the 8th matched resistance R30, the 9th matched resistance R32, the 20 filter capacitor C44.SIM deck SIM2 the 1st pin meets SIM_VDD, 2nd pin connects one end of the 7th matched resistance R29, another termination SIM_RST of 7th matched resistance R29,3rd pin connects one end of the 8th matched resistance R30, and the other end of the 8th matched resistance R30 is connected with SIM_CLK, the 4th pin ground connection, 6th pin connects one end of the 9th matched resistance R32, one end of the 20 filter capacitor C44, another termination SIM_DATA of 9th matched resistance R32, the other end ground connection of the 20 filter capacitor C44, the 5th foot rest is empty.
Described GPS module is made up of the circuit being core with NEO-6M module.
The circuit being core with NEO-6M module comprises UBLOX_NEO_6M module U1, antenna SMA interface RF1, the tenth matched resistance R1, the first inductance L 1; 24th, 13,12,10, the 7 pin ground connection of UBLOX_NEO_6M module U1,3 pin of the 20th pin connector JP1,21st pin connects 1 pin of connector JP1, and the 22nd, 23 pin meet VCC-3.3, the 11st pin is connected with the 5th pin of antenna SMA interface RF1, one end of the first inductance L 1; UBLOX_NEO_6M module U1 the 8th, 9 pin are connected, and are connected with one end of the tenth matched resistance R1, and the other end of the tenth matched resistance R1 is connected with the other end of the first inductance L 1; The 1st, 2,3,4 of antenna SMA interface RF1 is connected and ground connection; 1,2,3,4,5,6,14,15,16,17,18,19 foot rests of UBLOX_NEO_6M module U1 are empty.
Described Liquid Crystal Module is made up of TFT color screen liquid crystal circuit.
TFT color screen liquid crystal circuit is by TFT2.8 cun of liquid crystal T1, the 21 filter capacitor C17, the 22 filter capacitor C20, the 5th matching capacitance C19, the 12 Chip-R R11, the 13 Chip-R R12, TFT2.8 cun of liquid crystal T1 the 1st pin is connected with the 40th pin of STM32F103RBT6 chip STM1, 2nd pin is connected with the 39th pin of STM32F103RBT6 chip STM1, 3rd pin is connected with the 38th pin of STM32F103RBT6 chip STM1, 4th pin is connected with the 37th pin of STM32F103RBT6 chip STM1, 5th pin is connected with the 7th pin of STM32F103RBT6 chip STM1, 6th, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 pins respectively with the 26th of STM32F103RBT6 chip STM1, 27, 28, 55, 56, 57, 58, 59, 61, 62, 29, 30, 33, 34, 35, 36 pin are connected, 22nd, 26 pin grounding connections, 23rd pin is connected with the 53rd pin of STM32F103RBT6 chip STM1, 24th pin is connected with power interface VCC-3.3, and connect one end of the 21 filter capacitor C17, the other end ground connection of the 21 filter capacitor C17, 25th pin is connected with VCC-3.3,27th pin ground connection is also connected with one end of the 5th matching capacitance C19, the other end of the 5th matching capacitance C19 is connected with one end of the 12 Chip-R R11, one end of the 13 Chip-R R12, and the other end of the 12 Chip-R R11 is connected with the 9th pin of STM32F103RBT6 chip STM1.28th pin is connected with power supply VCC-5.0 and connects one end of the 22 filter capacitor C20, the other end ground connection of the 22 filter capacitor C20.29th pin is connected with the 10th pin of STM32F103RBT6 chip STM1,30th pin is connected with the 11st pin of STM32F103RBT6 chip STM1,31st pin is connected with the other end of the 13 Chip-R R12,32nd pin is unsettled, the 2nd pin that 33rd pin meets STM32F103RBT6 chip STM1 is connected, and the 34th pin connects the 8th pin of STM32F103RBT6 chip STM1.
Described controller and peripheral module thereof are made up of STM32F103RBT6 minimum system circuit, W25X16 Flash circuit, Mini SD card circuit, debug i/f circuit.
STM32F103RBT6 minimum system circuit comprises STM32F103RBT6 chip STM1, first shunt capacitance C3, second shunt capacitance C4, 3rd shunt capacitance C5, 4th shunt capacitance C6, quadripolarity electric capacity C7, 23 filter capacitor C1, 24 filter capacitor C8, 25 filter capacitor C11, 26 filter capacitor C12, 27 filter capacitor C2, 28 filter capacitor C10, first crystal oscillator X2, second crystal oscillator X1, 14 Chip-R R2, 15 Chip-R R6, 16 Chip-R R9, second button S1, second inductance L 2, 3rd light-emitting diode DS1, connector JP2, 3rd pin connects one end of the first shunt capacitance C3 and one end of the first crystal oscillator X2, and one end of the other end of the first shunt capacitance C3 and one end of the second shunt capacitance C4, the 3rd shunt capacitance C5, one end of the 4th shunt capacitance C6, the negative pole of quadripolarity electric capacity C7, one end of the 24 filter capacitor C8, the 12nd pin of STM32F103RBT6 chip STM1 are connected and ground connection, 4th pin connects the other end of the second shunt capacitance C4 and the other end of the first crystal oscillator X2, 5th pin connects the other end of the 3rd shunt capacitance C5, one end of the 15 Chip-R R6, one end of the second crystal oscillator X1, 6th pin connects the other end, the other end of the 15 Chip-R R6, the other end of the second crystal oscillator X1 of the 4th shunt capacitance C6, 7th pin connects one end of the 14 Chip-R R2, one end of the second button S1, one end of the 23 filter capacitor C1, the other end of another termination power interface VCC-3.3 of the 14 Chip-R R2, the second button S1 is connected with the other end of the 23 filter capacitor C1 and ground connection, the positive pole of the 13rd pin and quadripolarity electric capacity C7, the other end of the 24 filter capacitor C8, one end of the second inductance L 2 are connected, and the other end of the second inductance L 2 is connected with VCC-3.3 power interface, 14th pin is connected with PA0, 15th pin is connected with PA1, 16th pin is connected with 1 pin of W25X16 chips W 1, 17th pin is connected with SD_CS.18th pin is connected with one end of the 25 filter capacitor C11 and ground connection; 19th pin is connected with power supply VCC-3.3 and is connected with the other end of the 25 filter capacitor C11; 20th pin is connected with RESET_GSM; 21st, 22,23 pins are connected with 6,2,5 pin of W25X16 chips W 1 respectively; 24th pin meets PC4; 25th pin meets SHUTDOWN, and the 31st pin is connected with one end of the 26 filter capacitor C12 and ground connection; 32nd pin is connected with the other end of the 26 filter capacitor C12; 41st pin connects the negative electrode of the 3rd light-emitting diode DS1, and the anode of the 3rd light-emitting diode DS1 connects one end of the 16 Chip-R R9, another termination power interface VCC-3.3 of the 16 Chip-R R9; 42nd, 43 pin are connected with 2,4 pin of connector JP1; 48th pin meets one end and the power interface VCC-3.3 of the 28 filter capacitor C10, and the other end of the 28 filter capacitor C10 is connected with the 47th pin and ground connection; 51st, 52 are connected with 8,6 pin of connector JP1; 64th pin is connected with one end of power interface VCC-3.3, the 27 filter capacitor C2, the other end of the 27 filter capacitor C2 is connected with the 63rd pin and ground connection, 1st pin is unsettled, 44th pin meets PA11, and the 45th pin meets PA12, and the 46th pin meets PA13,49th pin meets PA14,50th pin meets PA15, and the 54th pin meets PD2, and the 60th pin meets BOOT0.
1 pin and 2 pin of connector JP2 meet power interface VCC-3.3, and 3 pin connect 28 pin of STM32F103RBT6 chip STM1, and 4 pin connect 60 pin of STM32F103RBT6 chip STM1,5 pin and 6 pin ground connection.
W25X16 Flash circuit is made up of W25X16 chips W the 1 and the 29 filter capacitor C9.3rd pin meets VCC-3.3, the 4th pin ground connection, and the 7th, 8 pins connect one end of VCC-3.3 power interface, the 29 filter capacitor C9, the other end ground connection of the 29 filter capacitor C9.
Mini SD card circuit is made up of Mini SD card deck SD1, the first pull-up resistor R3, the second pull-up resistor R4, the 3rd pull-up resistor R5, the 4th pull-up resistor R7 tetra-pull-up resistors.Mini SD card deck SD1 the 1st, 9 pins are unsettled, 6th, 8, 10, 11, 12, 13 ground connection, 2nd pin is connected with SD_CS and connects one end of the first pull-up resistor R3, 3rd pin is connected with SPI1_MOSI and connects one end of the second pull-up resistor R4, 5th pin is connected with SPI1_SCK and connects one end of the 3rd pull-up resistor R5, 7th pin is connected with SPI1_MISO and connects one end of the 4th pull-up resistor R7, 4th pin and VCC-3.3 power interface, the other end of the first pull-up resistor R3, the other end of the second pull-up resistor R4, the other end of the 3rd pull-up resistor R5, the other end of the 4th pull-up resistor R7 connects.
Debug i/f circuit is made up of 2 × 4 row's pin JP1, and the 5th pin is connected with TTL_RXD, and the 7th pin is connected with TTL_TXD.
Beneficial effect of the present invention: design vehicle-mounted wireless network intelligent anti-theft system, inherit like product GPS, GSM function, prevent self-propelled vehicle directly stolen, add that the anti-storage battery that like product do not have is stolen, the function in Google Earth real-time locating query self-propelled vehicle geographic position, can self-propelled vehicle be prevented to a great extent stolen.
Accompanying drawing illustrates:
Fig. 1 is the entire block diagram of patent of the present invention;
Fig. 2 is the mu balanced circuit schematic diagram of the MIC29502WU of patent of the present invention;
Fig. 3 is the LM1117 mu balanced circuit schematic diagram of patent of the present invention;
Fig. 4 is the SIM900A schematic circuit diagram of patent of the present invention;
Fig. 5 is the microphone interface circuit schematic diagram of patent of the present invention;
Fig. 6 is the audio power amplifier circuit schematic diagram of patent of the present invention;
Fig. 7 is the earphone interface circuit schematic diagram of patent of the present invention;
Fig. 8 is the LED indicating circuit schematic diagram of patent of the present invention;
Fig. 9 is the esd protection circuit schematic diagram of patent of the present invention;
Figure 10 is the SIM schematic circuit diagram of patent of the present invention;
Figure 11 is the NEO-6M modular circuit schematic diagram of patent of the present invention;
Figure 12 is the TFT color screen liquid crystal schematic circuit diagram of patent of the present invention;
Figure 13 is the STM32F103RBT6 minimum system schematic circuit diagram of patent of the present invention;
Figure 14 is the W25X16 Flash schematic circuit diagram of patent of the present invention;
Figure 15 is the Mini SD card schematic circuit diagram of patent of the present invention;
Figure 16 is the debug i/f circuit schematic diagram of patent of the present invention.
Detailed description of the invention
Below in conjunction with accompanying drawing, specific description is done to modules in the present invention.
As shown in Figure 1, a kind of wireless automotive networks intelligent anti-theft system comprises power management module 1, GSM/GPRS module 2, GPS module 3, Liquid Crystal Module 4, controller and peripheral module 5 thereof.Described power management module 1 comprise with LM317 be core mu balanced circuit 1-1 and take LM1117 as the mu balanced circuit 1-2 of core, described GSM/GPRS module 2 comprises SIM900A circuit 2-1, microphone interface circuit 2-2, audio power amplifier circuit 2-3, earphone interface circuit 2-4, LED indicating circuit 2-5, esd protection circuit 2-6 and SIM circuit 2-7; Described controller and peripheral module 5 thereof comprise STM32F103RBT6 minimum system circuit 5-1, W25X16 Flash circuit 5-2, Mini SD card circuit 5-3 and debug i/f circuit 5-4.
As shown in Figure 2, be that the mu balanced circuit of core comprises LM317 power supply chip U2, potential device R10, the first Chip-R R8, the first magnetic bead B1, the second magnetic bead B2, diode D1, the first polar capacitor C14, the first filter capacitor C13, the second filter capacitor C15, the 3rd filter capacitor C16 with LM317; 1st pin of LM317 power supply chip U2 is connected with the sliding end of one end of potential device R10, potential device R10, one end of the first Chip-R R8; One end of 2nd pin of LM317 power supply chip U2 and the other end of the first Chip-R R8, the first magnetic bead B1, the anode of diode D1, one end of the first polar capacitor C14, one end of the second filter capacitor C15, one end of the 3rd filter capacitor C16 are connected; The other end of the first magnetic bead B1 is connected with power interface VBAT, the negative electrode of diode D1 is connected with one end of the second magnetic bead B2, the other end of the second magnetic bead B2 is connected with power interface VEXT, the other end ground connection of the other end of the first polar capacitor C14, the other end of the second filter capacitor C15, the 3rd filter capacitor C16; 3rd pin of LM317 power supply chip U2 is connected with one end of the first filter capacitor C13, power interface VIN, the other end of the first filter capacitor C13 and the other end of potential device R10 grounding connection.
As shown in Figure 3, be that the mu balanced circuit of core comprises LM1117 voltage stabilizing chip L3 and the second polar capacitor C18 with LM1117; 1st pin of LM1117 voltage stabilizing chip L3 is connected with power interface VIN, 2nd pin of LM1117 voltage stabilizing chip L3 and one end of the second polar capacitor C18 grounding connection, the 3rd pin of LM1117 voltage stabilizing chip L3 is connected with the other end of power interface VCC-3.3, the second polar capacitor C18.
Described GSM/GPRS module comprises SIM900A circuit, microphone interface circuit, audio power amplifier circuit, earphone interface circuit, LED indicating circuit, esd protection circuit, SIM circuit.
As shown in Figure 4, SIM900A circuit comprises SIM900A module SM1, SMA antennal interface RF2, the first matched resistance R15, the second matched resistance R16, the 3rd matched resistance R21, the second Chip-R R27, the first matching capacitance C25, the 4th filter capacitor C22, the 5th filter capacitor C23, the 6th filter capacitor C36, the 3rd polar capacitor C21, 1st pin of SIM900A module SM1 is connected with one end of the 3rd matched resistance R21, and the other end of the 3rd matched resistance R21 is connected with POWER_KEY, and the 15th pin of SIM900A module SM1 is connected with power interface VDD_EXT, the 17th of SIM900A module SM1, 18, 29, 39, 45, 46, 53, 54, 58, 59, 61, 62, 63, 64, 65 pin ground connection, the 19th pin meets MIC_N, and the 20th pin meets MIC_P, and the 21st pin meets SPK_P, and the 22nd pin meets SPK_N, and the 27th pin meets DBG_TXD, and the 28th pin meets DBG_RXD, and the 26th pin is connected with power interface VCC-3.3, the 34th pin and SIM_PRECENCE, one end of second Chip-R R27 is connected, and the other end of the second Chip-R R27 is connected with power interface SIM_VDD, and the 33rd pin meets SIM_RST, and the 32nd pin meets SIM_CLK, and the 31st pin meets SIM_DATA, No. 30 pin and SIM_VDD power supply, one end of 6th filter capacitor C36 connects, the other end grounding connection of the 6th filter capacitor C36, and the 52nd pin is connected with NETLIGHT, the 55th pin and the 56th pin, 57th pin, power interface VBAT, one end of 3rd polar capacitor C21, one end of 4th filter capacitor C22, one end of 5th filter capacitor C23 connects, the other end of the 3rd polar capacitor C21, the other end of the 4th filter capacitor C22, the other end grounding connection of the 5th filter capacitor C23, the 60th pin is connected with one end of the second matched resistance R16, the other end of the second matched resistance R16 and one end of the first matching capacitance C25, one end of first matched resistance R15 is connected, and the other end of the first matched resistance R15 is connected with SMA antennal interface RF2 the 5th pin, the other end of the first matching capacitance C25 and SMA antennal interface RF2 the 1st, 2, 3, 4 pin grounding connection, the 66th pin meets STATUS.
As shown in Figure 5, microphone interface circuit comprises miaow head M2, the 7th filter capacitor C26, the 8th filter capacitor C27, the 9th filter capacitor C28, the tenth filter capacitor C29, the 11 filter capacitor C30, the 12 filter capacitor C31, one end of 7th filter capacitor C26 and one end of the 8th filter capacitor C27 grounding connection, the other end of the 7th filter capacitor C26 and one end of the 9th filter capacitor C28, one end of miaow head M2, the other end of the 8th filter capacitor C27, one end of tenth filter capacitor C29, MIC_N connects, the other end of the 9th filter capacitor C28 and one end of the 11 filter capacitor C30, the other end of miaow head M2, the other end of the tenth filter capacitor C29, one end of 12 filter capacitor C31, MIC_P is connected, the other end of the 11 filter capacitor C30 is connected with the other end of the 12 filter capacitor C31 and grounding connection.As shown in Figure 6, audio power amplifier circuit comprises LM4890 chip LM1, the 3rd Chip-R R28, the 4th matched resistance R31, the 5th matched resistance R33, the 6th matched resistance R34, the second matching capacitance C40, the 3rd matching capacitance C42, the 4th matching capacitance C43, the 13 filter capacitor C41, loudspeaker BUZZER1.1st pin of LM4890 chip LM1 is connected with SHUTDOWN, one end of 2nd pin and the 3rd Chip-R R28, one end of second matching capacitance C40 is connected, the other end ground connection of the second matching capacitance C40, 3rd pin of LM4890 chip LM1 and the other end of the 3rd Chip-R R28, one end of 4th matched resistance R31 is connected, the other end of the 4th matched resistance R31 is connected with one end of the 3rd matching capacitance C42, the other end of the 3rd matching capacitance C42 is connected with SPK_P, 4th pin of LM4890 chip LM1 and one end of the 5th matched resistance R33, one end of 6th matched resistance R34 is connected, the other end of the 5th matched resistance R33 is connected with one end of the 4th matching capacitance C43, the other end of the 4th matching capacitance C43 is connected with SPK_N, the other end of the 5th pin and the 6th matched resistance R34, SPK_N_A, 2nd pin of loudspeaker BUZZER1 is connected, 6th pin and power interface VIN, one end of 13 filter capacitor C41 is connected, 7th pin of LM4890 chip LM1 and the other end of the 13 filter capacitor C41 grounding connection, 8th pin and the SPK_P_A of LM4890 chip LM1, 1st pin of loudspeaker BUZZER1 is connected.
As shown in Figure 7, earphone interface circuit comprises the 14 filter capacitor C32, the 15 filter capacitor C33, the 16 filter capacitor C34, the 17 filter capacitor C35, the 18 filter capacitor C37, the 19 filter capacitor C38, earphone inserter P1, one end of 14 filter capacitor C32 and one end of the 15 filter capacitor C33 grounding connection, the other end of the 14 filter capacitor C32 and one end of the 16 filter capacitor C43, 4th pin of earphone inserter P1, the other end of the 15 filter capacitor C33, one end of 17 filter capacitor C35, SPK_P connects, the other end of the 16 filter capacitor C43 and one end of the 18 filter capacitor C37, 3rd pin of earphone inserter P1, the other end of the 17 filter capacitor C35, one end of 19 filter capacitor C38, SPK_N connects, the other end of the 18 filter capacitor C37 and the 2nd pin of earphone inserter P1, the other end of the 19 filter capacitor C38 connects and grounding connection, 1st foot rest of earphone inserter P1 is empty.
As shown in Figure 8, LED indicating circuit comprises the first aerotron Q1, the second aerotron Q3, the 3rd aerotron Q4, the first light-emitting diode DS2, the second light-emitting diode DS3, the 4th Chip-R R13, the 5th Chip-R R17, the 6th Chip-R R19, the 7th Chip-R R22, the 8th Chip-R R24, the 9th Chip-R R20, the tenth Chip-R R23, the 11 Chip-R R25, the first button S2; First aerotron Q1 collecting electrode meets POWER_KEY, base stage is connected with one end of the 4th Chip-R R13, one end of the 5th Chip-R R17, the other end of the 4th Chip-R R13 is connected with one end of the first button S2, the other end of the first button S2 is connected with power interface VEXT, and the emitter of the first aerotron Q1 is connected with the other end of the 5th Chip-R R17 and ground connection;
The collecting electrode of the second aerotron Q3 is connected with the negative electrode of the first light-emitting diode DS2, and the anode of the first light-emitting diode DS2 is connected with one end of the 6th Chip-R R19, and the other end of the 6th Chip-R R19 is connected with power interface VEXT; The base stage of the second aerotron Q3 is connected with one end of one end of the 7th Chip-R R22, the 8th Chip-R R24, the other end of the 7th Chip-R R22 is connected with STATUS, and the emitter of the second aerotron Q3 is connected with the other end of the 8th Chip-R R24 and ground connection;
The collecting electrode of the 3rd aerotron Q4 is connected with the negative electrode of the second light-emitting diode DS3, the anode of the second light-emitting diode DS3 is connected with one end of the 9th Chip-R R20, the other end of the 9th Chip-R R20 is connected with power interface VEXT, the base stage of the second aerotron Q3 is connected with one end of the tenth Chip-R R23, one end of the 11 Chip-R R25, and the other end of the tenth Chip-R R23 is connected with NETLIGHT; The emitter of the 3rd aerotron Q3 is connected with the other end of the 11 Chip-R R25 and ground connection.
As shown in Figure 9, esd protection circuit comprises PESD3V3L5UV chip P2; PESD3V3L5UV chip P2 the 1st, 3 pin are unsettled, the 2nd pin ground connection, the 4th pin meets SIM_CLK_ESD, and the 5th pin meets SIM_RST_ESD, and the 6th pin meets SIM_DATA_ESD.
As shown in Figure 10, SIM circuit comprises SIM deck SIM2, the 7th matched resistance R29, the 8th matched resistance R30, the 9th matched resistance R32, the 20 filter capacitor C44.SIM deck SIM2 the 1st pin meets SIM_VDD, 2nd pin connects one end of the 7th matched resistance R29, another termination SIM_RST of 7th matched resistance R29,3rd pin connects one end of the 8th matched resistance R30, and the other end of the 8th matched resistance R30 is connected with SIM_CLK, the 4th pin ground connection, 6th pin connects one end of the 9th matched resistance R32, one end of the 20 filter capacitor C44, another termination SIM_DATA of 9th matched resistance R32, the other end ground connection of the 20 filter capacitor C44, the 5th foot rest is empty.
Described GPS module is made up of the circuit being core with NEO-6M module.
As shown in figure 11, the circuit being core with NEO-6M module comprises UBLOX_NEO_6M module U1, antenna SMA interface RF1, the tenth matched resistance R1, the first inductance L 1; 24th, 13,12,10, the 7 pin ground connection of UBLOX_NEO_6M module U1,3 pin of the 20th pin connector JP1,21st pin connects 1 pin of connector JP1, and the 22nd, 23 pin meet VCC-3.3, the 11st pin is connected with the 5th pin of antenna SMA interface RF1, one end of the first inductance L 1; UBLOX_NEO_6M module U1 the 8th, 9 pin are connected, and are connected with one end of the tenth matched resistance R1, and the other end of the tenth matched resistance R1 is connected with the other end of the first inductance L 1; The 1st, 2,3,4 of antenna SMA interface RF1 is connected and ground connection; 1,2,3,4,5,6,14,15,16,17,18,19 foot rests of UBLOX_NEO_6M module U1 are empty.
Described Liquid Crystal Module is made up of TFT color screen liquid crystal circuit.
As shown in figure 12, TFT color screen liquid crystal circuit is by TFT2.8 cun of liquid crystal T1, the 21 filter capacitor C17, the 22 filter capacitor C20, the 5th matching capacitance C19, the 12 Chip-R R11, the 13 Chip-R R12, TFT2.8 cun of liquid crystal T1 the 1st pin is connected with the 40th pin of STM32F103RBT6 chip STM1, 2nd pin is connected with the 39th pin of STM32F103RBT6 chip STM1, 3rd pin is connected with the 38th pin of STM32F103RBT6 chip STM1, 4th pin is connected with the 37th pin of STM32F103RBT6 chip STM1, 5th pin is connected with the 7th pin of STM32F103RBT6 chip STM1, 6th, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 pins respectively with the 26th of STM32F103RBT6 chip STM1, 27, 28, 55, 56, 57, 58, 59, 61, 62, 29, 30, 33, 34, 35, 36 pin are connected, 22nd, 26 pin grounding connections, 23rd pin is connected with the 53rd pin of STM32F103RBT6 chip STM1, 24th pin is connected with power interface VCC-3.3, and connect one end of the 21 filter capacitor C17, the other end ground connection of the 21 filter capacitor C17, 25th pin is connected with VCC-3.3,27th pin ground connection is also connected with one end of the 5th matching capacitance C19, the other end of the 5th matching capacitance C19 is connected with one end of the 12 Chip-R R11, one end of the 13 Chip-R R12, and the other end of the 12 Chip-R R11 is connected with the 9th pin of STM32F103RBT6 chip STM1.28th pin is connected with power supply VCC-5.0 and connects one end of the 22 filter capacitor C20, the other end ground connection of the 22 filter capacitor C20.29th pin is connected with the 10th pin of STM32F103RBT6 chip STM1,30th pin is connected with the 11st pin of STM32F103RBT6 chip STM1,31st pin is connected with the other end of the 13 Chip-R R12,32nd pin is unsettled, the 2nd pin that 33rd pin meets STM32F103RBT6 chip STM1 is connected, and the 34th pin connects the 8th pin of STM32F103RBT6 chip STM1.
Described controller and peripheral module thereof are made up of STM32F103RBT6 minimum system circuit, W25X16 Flash circuit, Mini SD card circuit, debug i/f circuit.
As shown in figure 13, STM32F103RBT6 minimum system circuit comprises STM32F103RBT6 chip STM1, first shunt capacitance C3, second shunt capacitance C4, 3rd shunt capacitance C5, 4th shunt capacitance C6, quadripolarity electric capacity C7, 23 filter capacitor C1, 24 filter capacitor C8, 25 filter capacitor C11, 26 filter capacitor C12, 27 filter capacitor C2, 28 filter capacitor C10, first crystal oscillator X2, second crystal oscillator X1, 14 Chip-R R2, 15 Chip-R R6, 16 Chip-R R9, second button S1, second inductance L 2, 3rd light-emitting diode DS1, connector JP2, 3rd pin connects one end of the first shunt capacitance C3 and one end of the first crystal oscillator X2, and one end of the other end of the first shunt capacitance C3 and one end of the second shunt capacitance C4, the 3rd shunt capacitance C5, one end of the 4th shunt capacitance C6, the negative pole of quadripolarity electric capacity C7, one end of the 24 filter capacitor C8, the 12nd pin of STM32F103RBT6 chip STM1 are connected and ground connection, 4th pin connects the other end of the second shunt capacitance C4 and the other end of the first crystal oscillator X2, 5th pin connects the other end of the 3rd shunt capacitance C5, one end of the 15 Chip-R R6, one end of the second crystal oscillator X1, 6th pin connects the other end, the other end of the 15 Chip-R R6, the other end of the second crystal oscillator X1 of the 4th shunt capacitance C6, 7th pin connects one end of the 14 Chip-R R2, one end of the second button S1, one end of the 23 filter capacitor C1, the other end of another termination power interface VCC-3.3 of the 14 Chip-R R2, the second button S1 is connected with the other end of the 23 filter capacitor C1 and ground connection, the positive pole of the 13rd pin and quadripolarity electric capacity C7, the other end of the 24 filter capacitor C8, one end of the second inductance L 2 are connected, and the other end of the second inductance L 2 is connected with VCC-3.3 power interface, 14th pin is connected with PA0, 15th pin is connected with PA1, 16th pin is connected with 1 pin of W25X16 chips W 1, 17th pin is connected with SD_CS.18th pin is connected with one end of the 25 filter capacitor C11 and ground connection; 19th pin is connected with power supply VCC-3.3 and is connected with the other end of the 25 filter capacitor C11; 20th pin is connected with RESET_GSM; 21st, 22,23 pins are connected with 6,2,5 pin of W25X16 chips W 1 respectively; 24th pin meets PC4; 25th pin meets SHUTDOWN, and the 31st pin is connected with one end of the 26 filter capacitor C12 and ground connection; 32nd pin is connected with the other end of the 26 filter capacitor C12; 41st pin connects the negative electrode of the 3rd light-emitting diode DS1, and the anode of the 3rd light-emitting diode DS1 connects one end of the 16 Chip-R R9, another termination power interface VCC-3.3 of the 16 Chip-R R9; 42nd, 43 pin are connected with 2,4 pin of connector JP1; 48th pin meets one end and the power interface VCC-3.3 of the 28 filter capacitor C10, and the other end of the 28 filter capacitor C10 is connected with the 47th pin and ground connection; 51st, 52 are connected with 8,6 pin of connector JP1; 64th pin is connected with one end of power interface VCC-3.3, the 27 filter capacitor C2, the other end of the 27 filter capacitor C2 is connected with the 63rd pin and ground connection, 1st pin is unsettled, 44th pin meets PA11, and the 45th pin meets PA12, and the 46th pin meets PA13,49th pin meets PA14,50th pin meets PA15, and the 54th pin meets PD2, and the 60th pin meets BOOT0.
1 pin and 2 pin of connector JP2 meet power interface VCC-3.3, and 3 pin connect 28 pin of STM32F103RBT6 chip STM1, and 4 pin connect 60 pin of STM32F103RBT6 chip STM1,5 pin and 6 pin ground connection.
As shown in figure 14, W25X16 Flash circuit is made up of W25X16 chips W the 1 and the 29 filter capacitor C9.3rd pin meets VCC-3.3, the 4th pin ground connection, and the 7th, 8 pins connect one end of VCC-3.3 power interface, the 29 filter capacitor C9, the other end ground connection of the 29 filter capacitor C9.
As shown in figure 15, Mini SD card circuit is made up of Mini SD card deck SD1, the first pull-up resistor R3, the second pull-up resistor R4, the 3rd pull-up resistor R5, the 4th pull-up resistor R7 tetra-pull-up resistors.Mini SD card deck SD1 the 1st, 9 pins are unsettled, 6th, 8, 10, 11, 12, 13 ground connection, 2nd pin is connected with SD_CS and connects one end of the first pull-up resistor R3, 3rd pin is connected with SPI1_MOSI and connects one end of the second pull-up resistor R4, 5th pin is connected with SPI1_SCK and connects one end of the 3rd pull-up resistor R5, 7th pin is connected with SPI1_MISO and connects one end of the 4th pull-up resistor R7, 4th pin and VCC-3.3 power interface, the other end of the first pull-up resistor R3, the other end of the second pull-up resistor R4, the other end of the 3rd pull-up resistor R5, the other end of the 4th pull-up resistor R7 connects.
As shown in figure 16, debug i/f circuit is made up of 2 × 4 row's pin JP1, and the 5th pin is connected with TTL_RXD, and the 7th pin is connected with TTL_TXD.
Vehicular wireless network intelligent anti-theft system workflow is as follows: whole system is made up of data center (upper computer) and self-propelled vehicle client.The STM32F103 series monolithic of system master chip to be kernel be Cortex-M3, external equipment comprises: SIM900A(GSM/GPRS module), NEO-6M(GPS module), Mini SD memory card.SIM900A, NEO-6M and micro controller system adopt serial communication, and GPS sends locating data bag to micro controller system by the serial ports 1 of micro controller system, and actv. information, after Data Analysis, is sent to SIM900A module by serial ports 3 by micro controller system; Mini SD memory card is used for storing data necessary in garage's process, carries out data exchange with the form of 4 line SPI and micro controller system.For ensureing commonality and the portability of software, system adopts the senior applicational language of MDK micro controller system to write.Software system comprise serial port drive layer, information transmission and application layer.Serial port drive layer first according to the characteristic of SIM900A module to RS232 serial port carry out initialization comprise arrange serial ports mode of operation baud rate initializing variable parameter and zone bit herein communication speed be set to 9600bps.Transmission of messages and application layer send AT instruction control SIM900A module by serial ports 2 and complete the telephone number in the setting of SIM900A module and network entry reading SIM card, send note, receive the function such as note and note data management.Serial ports 1 receives gps data bag, and carries out data packet parsing according to NMEA standard.Data center (upper computer) receives the Google Earth upper computer that data are developed by secondary API, accurately shows geographical location information.
Vehicular wireless network intelligent anti-theft system realizes following function:
1. prevent directly stealing self-propelled vehicle.Cause self-propelled vehicle to be moved the distance of 50M because of certain external factor, realize the alarm of over range note, by GSM, the information that GPS locates is sent to the computer of user.
2. anti-malice cutoff die block power supply.Module is powered separately, maintains system works ability.Avoiding malice cut-out storage battery car power supply makes this product module normally work, and this is that like product does not have.
3. by using the Socket monitoring technique of C# exploitation, receiving GPRS data, and resolving, geographic position being presented on the Google Earth of API secondary development, help car owner to give self-propelled vehicle for change in time.
4. user can be arranged module parameter by mobile phone or computer upper computer.
Claims (1)
1. a wireless automotive networks intelligent anti-theft system comprises power management module, GSM/GPRS module, GPS module, Liquid Crystal Module, controller and peripheral module thereof;
It is characterized in that: described power management module comprises mu balanced circuit that LM317 is core and take LM1117 as the mu balanced circuit of core;
Be that the mu balanced circuit of core comprises LM317 power supply chip U2, potential device R10, the first Chip-R R8, the first magnetic bead B1, the second magnetic bead B2, diode D1, the first polar capacitor C14, the first filter capacitor C13, the second filter capacitor C15, the 3rd filter capacitor C16 with LM317; 1st pin of LM317 power supply chip U2 is connected with the sliding end of one end of potential device R10, potential device R10, one end of the first Chip-R R8; One end of 2nd pin of LM317 power supply chip U2 and the other end of the first Chip-R R8, the first magnetic bead B1, the anode of diode D1, one end of the first polar capacitor C14, one end of the second filter capacitor C15, one end of the 3rd filter capacitor C16 are connected; The other end of the first magnetic bead B1 is connected with power interface VBAT, the negative electrode of diode D1 is connected with one end of the second magnetic bead B2, the other end of the second magnetic bead B2 is connected with power interface VEXT, the other end ground connection of the other end of the first polar capacitor C14, the other end of the second filter capacitor C15, the 3rd filter capacitor C16; 3rd pin of LM317 power supply chip U2 is connected with one end of the first filter capacitor C13, power interface VIN, the other end of the first filter capacitor C13 and the other end of potential device R10 grounding connection;
Be that the mu balanced circuit of core comprises LM1117 voltage stabilizing chip L3 and the second polar capacitor C18 with LM1117; 1st pin of LM1117 voltage stabilizing chip L3 is connected with power interface VIN, 2nd pin of LM1117 voltage stabilizing chip L3 and one end of the second polar capacitor C18 grounding connection, the 3rd pin of LM1117 voltage stabilizing chip L3 is connected with the other end of power interface VCC-3.3, the second polar capacitor C18;
Described GSM/GPRS module comprises SIM900A circuit, microphone interface circuit, audio power amplifier circuit, earphone interface circuit, LED indicating circuit, esd protection circuit, SIM circuit;
SIM900A circuit comprises SIM900A module SM1, SMA antennal interface RF2, the first matched resistance R15, the second matched resistance R16, the 3rd matched resistance R21, the second Chip-R R27, the first matching capacitance C25, the 4th filter capacitor C22, the 5th filter capacitor C23, the 6th filter capacitor C36, the 3rd polar capacitor C21, 1st pin of SIM900A module SM1 is connected with one end of the 3rd matched resistance R21, and the other end of the 3rd matched resistance R21 is connected with POWER_KEY, and the 15th pin of SIM900A module SM1 is connected with power interface VDD_EXT, the 17th of SIM900A module SM1, 18, 29, 39, 45, 46, 53, 54, 58, 59, 61, 62, 63, 64, 65 pin ground connection, the 19th pin meets MIC_N, and the 20th pin meets MIC_P, and the 21st pin meets SPK_P, and the 22nd pin meets SPK_N, and the 27th pin meets DBG_TXD, and the 28th pin meets DBG_RXD, and the 26th pin is connected with power interface VCC-3.3, the 34th pin and SIM_PRECENCE, one end of second Chip-R R27 is connected, and the other end of the second Chip-R R27 is connected with power interface SIM_VDD, and the 33rd pin meets SIM_RST, and the 32nd pin meets SIM_CLK, and the 31st pin meets SIM_DATA, No. 30 pin and SIM_VDD power supply, one end of 6th filter capacitor C36 connects, the other end grounding connection of the 6th filter capacitor C36, and the 52nd pin is connected with NETLIGHT, the 55th pin and the 56th pin, 57th pin, power interface VBAT, one end of 3rd polar capacitor C21, one end of 4th filter capacitor C22, one end of 5th filter capacitor C23 connects, the other end of the 3rd polar capacitor C21, the other end of the 4th filter capacitor C22, the other end grounding connection of the 5th filter capacitor C23, the 60th pin is connected with one end of the second matched resistance R16, the other end of the second matched resistance R16 and one end of the first matching capacitance C25, one end of first matched resistance R15 is connected, and the other end of the first matched resistance R15 is connected with SMA antennal interface RF2 the 5th pin, the other end of the first matching capacitance C25 and SMA antennal interface RF2 the 1st, 2, 3, 4 pin grounding connection, the 66th pin meets STATUS,
Microphone interface circuit comprises miaow head M2, the 7th filter capacitor C26, the 8th filter capacitor C27, the 9th filter capacitor C28, the tenth filter capacitor C29, the 11 filter capacitor C30, the 12 filter capacitor C31, one end of 7th filter capacitor C26 and one end of the 8th filter capacitor C27 grounding connection, the other end of the 7th filter capacitor C26 and one end of the 9th filter capacitor C28, one end of miaow head M2, the other end of the 8th filter capacitor C27, one end of tenth filter capacitor C29, MIC_N connects, the other end of the 9th filter capacitor C28 and one end of the 11 filter capacitor C30, the other end of miaow head M2, the other end of the tenth filter capacitor C29, one end of 12 filter capacitor C31, MIC_P is connected, the other end of the 11 filter capacitor C30 is connected with the other end of the 12 filter capacitor C31 and grounding connection, audio power amplifier circuit comprises LM4890 chip LM1, the 3rd Chip-R R28, the 4th matched resistance R31, the 5th matched resistance R33, the 6th matched resistance R34, the second matching capacitance C40, the 3rd matching capacitance C42, the 4th matching capacitance C43, the 13 filter capacitor C41, loudspeaker BUZZER1, 1st pin of LM4890 chip LM1 is connected with SHUTDOWN, one end of 2nd pin and the 3rd Chip-R R28, one end of second matching capacitance C40 is connected, the other end ground connection of the second matching capacitance C40, 3rd pin of LM4890 chip LM1 and the other end of the 3rd Chip-R R28, one end of 4th matched resistance R31 is connected, the other end of the 4th matched resistance R31 is connected with one end of the 3rd matching capacitance C42, the other end of the 3rd matching capacitance C42 is connected with SPK_P, 4th pin of LM4890 chip LM1 and one end of the 5th matched resistance R33, one end of 6th matched resistance R34 is connected, the other end of the 5th matched resistance R33 is connected with one end of the 4th matching capacitance C43, the other end of the 4th matching capacitance C43 is connected with SPK_N, the other end of the 5th pin and the 6th matched resistance R34, SPK_N_A, 2nd pin of loudspeaker BUZZER1 is connected, 6th pin and power interface VIN, one end of 13 filter capacitor C41 is connected, 7th pin of LM4890 chip LM1 and the other end of the 13 filter capacitor C41 grounding connection, 8th pin and the SPK_P_A of LM4890 chip LM1, 1st pin of loudspeaker BUZZER1 is connected,
Earphone interface circuit comprises the 14 filter capacitor C32, the 15 filter capacitor C33, the 16 filter capacitor C34, the 17 filter capacitor C35, the 18 filter capacitor C37, the 19 filter capacitor C38, earphone inserter P1, one end of 14 filter capacitor C32 and one end of the 15 filter capacitor C33 grounding connection, the other end of the 14 filter capacitor C32 and one end of the 16 filter capacitor C43, 4th pin of earphone inserter P1, the other end of the 15 filter capacitor C33, one end of 17 filter capacitor C35, SPK_P connects, the other end of the 16 filter capacitor C43 and one end of the 18 filter capacitor C37, 3rd pin of earphone inserter P1, the other end of the 17 filter capacitor C35, one end of 19 filter capacitor C38, SPK_N connects, the other end of the 18 filter capacitor C37 and the 2nd pin of earphone inserter P1, the other end of the 19 filter capacitor C38 connects and grounding connection, 1st foot rest of earphone inserter P1 is empty,
LED indicating circuit comprises the first aerotron Q1, the second aerotron Q3, the 3rd aerotron Q4, the first light-emitting diode DS2, the second light-emitting diode DS3, the 4th Chip-R R13, the 5th Chip-R R17, the 6th Chip-R R19, the 7th Chip-R R22, the 8th Chip-R R24, the 9th Chip-R R20, the tenth Chip-R R23, the 11 Chip-R R25, the first button S2; First aerotron Q1 collecting electrode meets POWER_KEY, base stage is connected with one end of the 4th Chip-R R13, one end of the 5th Chip-R R17, the other end of the 4th Chip-R R13 is connected with one end of the first button S2, the other end of the first button S2 is connected with power interface VEXT, and the emitter of the first aerotron Q1 is connected with the other end of the 5th Chip-R R17 and ground connection;
The collecting electrode of the second aerotron Q3 is connected with the negative electrode of the first light-emitting diode DS2, and the anode of the first light-emitting diode DS2 is connected with one end of the 6th Chip-R R19, and the other end of the 6th Chip-R R19 is connected with power interface VEXT; The base stage of the second aerotron Q3 is connected with one end of one end of the 7th Chip-R R22, the 8th Chip-R R24, the other end of the 7th Chip-R R22 is connected with STATUS, and the emitter of the second aerotron Q3 is connected with the other end of the 8th Chip-R R24 and ground connection;
The collecting electrode of the 3rd aerotron Q4 is connected with the negative electrode of the second light-emitting diode DS3, the anode of the second light-emitting diode DS3 is connected with one end of the 9th Chip-R R20, the other end of the 9th Chip-R R20 is connected with power interface VEXT, the base stage of the second aerotron Q3 is connected with one end of the tenth Chip-R R23, one end of the 11 Chip-R R25, and the other end of the tenth Chip-R R23 is connected with NETLIGHT; The emitter of the 3rd aerotron Q3 is connected with the other end of the 11 Chip-R R25 and ground connection;
Esd protection circuit comprises PESD3V3L5UV chip P2; PESD3V3L5UV chip P2 the 1st, 3 pin are unsettled, the 2nd pin ground connection, the 4th pin meets SIM_CLK_ESD, and the 5th pin meets SIM_RST_ESD, and the 6th pin meets SIM_DATA_ESD;
SIM circuit comprises SIM deck SIM2, the 7th matched resistance R29, the 8th matched resistance R30, the 9th matched resistance R32, the 20 filter capacitor C44; SIM deck SIM2 the 1st pin meets SIM_VDD, 2nd pin connects one end of the 7th matched resistance R29, another termination SIM_RST of 7th matched resistance R29,3rd pin connects one end of the 8th matched resistance R30, and the other end of the 8th matched resistance R30 is connected with SIM_CLK, the 4th pin ground connection, 6th pin connects one end of the 9th matched resistance R32, one end of the 20 filter capacitor C44, another termination SIM_DATA of 9th matched resistance R32, the other end ground connection of the 20 filter capacitor C44, the 5th foot rest is empty;
Described GPS module is made up of the circuit being core with NEO-6M module;
The circuit being core with NEO-6M module comprises UBLOX_NEO_6M module U1, antenna SMA interface RF1, the tenth matched resistance R1, the first inductance L 1; 24th, 13,12,10, the 7 pin ground connection of UBLOX_NEO_6M module U1,3 pin of the 20th pin connector JP1,21st pin connects 1 pin of connector JP1, and the 22nd, 23 pin meet VCC-3.3, the 11st pin is connected with the 5th pin of antenna SMA interface RF1, one end of the first inductance L 1; UBLOX_NEO_6M module U1 the 8th, 9 pin are connected, and are connected with one end of the tenth matched resistance R1, and the other end of the tenth matched resistance R1 is connected with the other end of the first inductance L 1; The 1st, 2,3,4 of antenna SMA interface RF1 is connected and ground connection; 1,2,3,4,5,6,14,15,16,17,18,19 foot rests of UBLOX_NEO_6M module U1 are empty;
Described Liquid Crystal Module is made up of TFT color screen liquid crystal circuit;
TFT color screen liquid crystal circuit is by TFT2.8 cun of liquid crystal T1, the 21 filter capacitor C17, the 22 filter capacitor C20, the 5th matching capacitance C19, the 12 Chip-R R11, the 13 Chip-R R12, TFT2.8 cun of liquid crystal T1 the 1st pin is connected with the 40th pin of STM32F103RBT6 chip STM1, 2nd pin is connected with the 39th pin of STM32F103RBT6 chip STM1, 3rd pin is connected with the 38th pin of STM32F103RBT6 chip STM1, 4th pin is connected with the 37th pin of STM32F103RBT6 chip STM1, 5th pin is connected with the 7th pin of STM32F103RBT6 chip STM1, 6th, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 pins respectively with the 26th of STM32F103RBT6 chip STM1, 27, 28, 55, 56, 57, 58, 59, 61, 62, 29, 30, 33, 34, 35, 36 pin are connected, 22nd, 26 pin grounding connections, 23rd pin is connected with the 53rd pin of STM32F103RBT6 chip STM1, 24th pin is connected with power interface VCC-3.3, and connect one end of the 21 filter capacitor C17, the other end ground connection of the 21 filter capacitor C17, 25th pin is connected with VCC-3.3,27th pin ground connection is also connected with one end of the 5th matching capacitance C19, the other end of the 5th matching capacitance C19 is connected with one end of the 12 Chip-R R11, one end of the 13 Chip-R R12, and the other end of the 12 Chip-R R11 is connected with the 9th pin of STM32F103RBT6 chip STM1, 28th pin is connected with power supply VCC-5.0 and connects one end of the 22 filter capacitor C20, the other end ground connection of the 22 filter capacitor C20, 29th pin is connected with the 10th pin of STM32F103RBT6 chip STM1,30th pin is connected with the 11st pin of STM32F103RBT6 chip STM1,31st pin is connected with the other end of the 13 Chip-R R12,32nd pin is unsettled, the 2nd pin that 33rd pin meets STM32F103RBT6 chip STM1 is connected, and the 34th pin connects the 8th pin of STM32F103RBT6 chip STM1,
Described controller and peripheral module thereof are made up of STM32F103RBT6 minimum system circuit, W25X16 Flash circuit, Mini SD card circuit, debug i/f circuit;
STM32F103RBT6 minimum system circuit comprises STM32F103RBT6 chip STM1, first shunt capacitance C3, second shunt capacitance C4, 3rd shunt capacitance C5, 4th shunt capacitance C6, quadripolarity electric capacity C7, 23 filter capacitor C1, 24 filter capacitor C8, 25 filter capacitor C11, 26 filter capacitor C12, 27 filter capacitor C2, 28 filter capacitor C10, first crystal oscillator X2, second crystal oscillator X1, 14 Chip-R R2, 15 Chip-R R6, 16 Chip-R R9, second button S1, second inductance L 2, 3rd light-emitting diode DS1, connector JP2, 3rd pin connects one end of the first shunt capacitance C3 and one end of the first crystal oscillator X2, and one end of the other end of the first shunt capacitance C3 and one end of the second shunt capacitance C4, the 3rd shunt capacitance C5, one end of the 4th shunt capacitance C6, the negative pole of quadripolarity electric capacity C7, one end of the 24 filter capacitor C8, the 12nd pin of STM32F103RBT6 chip STM1 are connected and ground connection, 4th pin connects the other end of the second shunt capacitance C4 and the other end of the first crystal oscillator X2, 5th pin connects the other end of the 3rd shunt capacitance C5, one end of the 15 Chip-R R6, one end of the second crystal oscillator X1, 6th pin connects the other end, the other end of the 15 Chip-R R6, the other end of the second crystal oscillator X1 of the 4th shunt capacitance C6, 7th pin connects one end of the 14 Chip-R R2, one end of the second button S1, one end of the 23 filter capacitor C1, the other end of another termination power interface VCC-3.3 of the 14 Chip-R R2, the second button S1 is connected with the other end of the 23 filter capacitor C1 and ground connection, the positive pole of the 13rd pin and quadripolarity electric capacity C7, the other end of the 24 filter capacitor C8, one end of the second inductance L 2 are connected, and the other end of the second inductance L 2 is connected with VCC-3.3 power interface, 14th pin is connected with PA0, 15th pin is connected with PA1, 16th pin is connected with 1 pin of W25X16 chips W 1, 17th pin is connected with SD_CS, 18th pin is connected with one end of the 25 filter capacitor C11 and ground connection, 19th pin is connected with power supply VCC-3.3 and is connected with the other end of the 25 filter capacitor C11, 20th pin is connected with RESET_GSM, 21st, 22,23 pins are connected with 6,2,5 pin of W25X16 chips W 1 respectively, 24th pin meets PC4, 25th pin meets SHUTDOWN, and the 31st pin is connected with one end of the 26 filter capacitor C12 and ground connection, 32nd pin is connected with the other end of the 26 filter capacitor C12, 41st pin connects the negative electrode of the 3rd light-emitting diode DS1, and the anode of the 3rd light-emitting diode DS1 connects one end of the 16 Chip-R R9, another termination power interface VCC-3.3 of the 16 Chip-R R9, 42nd, 43 pin are connected with 2,4 pin of connector JP1, 48th pin meets one end and the power interface VCC-3.3 of the 28 filter capacitor C10, and the other end of the 28 filter capacitor C10 is connected with the 47th pin and ground connection, 51st, 52 are connected with 8,6 pin of connector JP1, 64th pin is connected with one end of power interface VCC-3.3, the 27 filter capacitor C2, the other end of the 27 filter capacitor C2 is connected with the 63rd pin and ground connection, 1st pin is unsettled, 44th pin meets PA11, and the 45th pin meets PA12, and the 46th pin meets PA13,49th pin meets PA14,50th pin meets PA15, and the 54th pin meets PD2, and the 60th pin meets BOOT0,
1 pin and 2 pin of connector JP2 meet power interface VCC-3.3, and 3 pin connect 28 pin of STM32F103RBT6 chip STM1, and 4 pin connect 60 pin of STM32F103RBT6 chip STM1,5 pin and 6 pin ground connection;
W25X16 Flash circuit is made up of W25X16 chips W the 1 and the 29 filter capacitor C9; 3rd pin meets VCC-3.3, the 4th pin ground connection, and the 7th, 8 pins connect one end of VCC-3.3 power interface, the 29 filter capacitor C9, the other end ground connection of the 29 filter capacitor C9;
Mini SD card circuit is made up of Mini SD card deck SD1, the first pull-up resistor R3, the second pull-up resistor R4, the 3rd pull-up resistor R5, the 4th pull-up resistor R7 tetra-pull-up resistors, Mini SD card deck SD1 the 1st, 9 pins are unsettled, 6th, 8, 10, 11, 12, 13 ground connection, 2nd pin is connected with SD_CS and connects one end of the first pull-up resistor R3, 3rd pin is connected with SPI1_MOSI and connects one end of the second pull-up resistor R4, 5th pin is connected with SPI1_SCK and connects one end of the 3rd pull-up resistor R5, 7th pin is connected with SPI1_MISO and connects one end of the 4th pull-up resistor R7, 4th pin and VCC-3.3 power interface, the other end of the first pull-up resistor R3, the other end of the second pull-up resistor R4, the other end of the 3rd pull-up resistor R5, the other end of the 4th pull-up resistor R7 connects,
Debug i/f circuit is made up of 2 × 4 row's pin JP1, and the 5th pin is connected with TTL_RXD, and the 7th pin is connected with TTL_TXD.
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| CN103499959A (en) * | 2013-09-30 | 2014-01-08 | 浙江大学 | Remote maintenance terminal for textile machine |
| CN103879378A (en) * | 2013-12-31 | 2014-06-25 | 莱阳市科盾通信设备有限责任公司 | Remote alarm device for stolen cars |
| CN106627481A (en) * | 2017-01-18 | 2017-05-10 | 无锡猎吧网络科技有限公司 | Vehicle identification system intelligent control part |
| CN107139880B (en) * | 2017-05-18 | 2023-09-08 | 上海赋锦信息技术股份有限公司 | Positioning anti-theft control system for vehicles and ships |
| CN109448159A (en) * | 2018-12-28 | 2019-03-08 | 中国重汽集团济南动力有限公司 | A kind of vehicle information terminal |
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