CN202795349U - Serial bus data analyzer and analysis system - Google Patents
Serial bus data analyzer and analysis system Download PDFInfo
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- CN202795349U CN202795349U CN 201220389726 CN201220389726U CN202795349U CN 202795349 U CN202795349 U CN 202795349U CN 201220389726 CN201220389726 CN 201220389726 CN 201220389726 U CN201220389726 U CN 201220389726U CN 202795349 U CN202795349 U CN 202795349U
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Abstract
The utility model discloses a serial bus data analyzer and an analysis system. The analyzer comprises a frequency divider, a main controller, a bidirectional reference clock port, a time label timer, a data transmission module, a first controller, a second controller and a memorizer. Frequency division is conducted to a system clock signal through the frequency divider, and a frequency divided clock signal is output. The main controller is used for receiving a control command carrying a working mode identification, distinguishing the working mode identification, allowing the frequency divided clock signal to be transmitted to the time label timer and to the bidirectional reference clock port when the serial bus data analyzer is indicated as a main analyzer, and prohibiting the frequency divided clock signal to be transmitted to the time label timer and to the bidirectional reference clock port when the serial bus data analyzer is indicated as a sub-analyzer. The bidirectional reference clock port is used for outputting the frequency divided clock signal to at least one sub-analyzer, or inputting the frequency divided clock signal output by the main analyzer to the time label timer. The time label timer produces a time label under the control of the frequency divided clock signal. The data transmission module is used for simultaneously sending trigger signals to the first controller and the second controller when transmission of a communication data frame is finished. The first controller is used for reading the communication data frame from the data transmission module and writing the communication data frame into the memorizer. The second controller is used for reading the time label from the time label timer and writing the time label into the memorizer. The memorizer is sued for memorizing the communication data frame and the time label of the communication data frame. According to the embodiments of the serial bus data analyzer and the analysis system, synchronization of time labels produced by different serial bus data analyzers can be achieved, and therefore communication data frames coming from the different serial bus data analyzers have comparability in relative time relationships.
Description
Technical field
The utility model relates to field of computer technology, particularly relates to a kind of serial bus data analyser and analytic system.
Background technology
Because present automobile industry is to security, comfortableness, convenience, low public hazards and cheaply requirement, various electronic control systems are developed, the application of bussing technique in automobile deepens continuously, as, tend to be provided with many CAN (Controller Area Network) bus in the automobile.Can connect by a gateway between a plurality of buses, realize the communication between the bus data.
In bussing technique, in order to guarantee the safety and stability of data communication, usually need to carry out data analysis to the communication data on a plurality of buses by the bus data analyser.So-called bus data analyser, observe exactly the equipment of the communication data frame between a plurality of buses, it not only will gather the communication data frame between a plurality of buses, also will make a call to a time tag to each the communication data frame that gathers, this time tag is used for the relative time of sign communication data frame when bus is transmitted.Like this, the user is by the bus data analyser, not only can observe the communication data frame on the bus, can also observe the relative time relation between the communication data frame, and judge the cause-effect relationship whether data retransmission between each bus is delayed time and delayed time according to the relative time relation.
In present serial bus system, each serial bus data analyser gathers and beats time tag to the communications data frame on its bus of being responsible for respectively independently.But, utility model people finds in the process that the utility model is studied, each serial bus data analysis is when beating time tag to the communication data frame, time tag all produces as benchmark with inner separately clock, and because the clock of different serial bus data analyser inside is nonsynchronous, therefore, the time tag that different serial bus data analysers produces is also asynchronous, like this, when the serial bus data under the different serial bus systems was carried out data analysis, the relative time relation that comes from the communication data frame of different serial bus data analysers did not have comparability.
The utility model content
In order to solve the problems of the technologies described above, the utility model embodiment provides a kind of serial bus data analyser and analytic system, so that the time tag that different serial bus data analysers produces is synchronous, and then, in a serial bus system, make the relative time relation from the communication data frame of different serial bus data analysers have comparability.
The utility model embodiment discloses following technical scheme:
The first serial bus data analyser comprises frequency divider, master controller, two-way reference clock port, time tag timer, data transmission module, the first controller, second controller and storer, wherein,
Described frequency divider is used for clock signal of system being carried out frequency division, the output frequency division clock signal;
Described master controller, be used for receiving the steering order of carrying the mode of operation sign, described mode of operation is identified, when the described serial bus data analyser of described mode of operation sign indication is main analyser, allow described sub-frequency clock signal to be sent to described time tag timer and described two-way reference clock port, when the described serial bus data analyser of described mode of operation sign indication is during from analyser, forbid that described sub-frequency clock signal is sent to described clock label timer and two-way reference clock port;
Described two-way reference clock port, be used for when the described serial bus data analyser of described mode of operation sign indication is main analyser, described sub-frequency clock signal is exported at least one from analyser, perhaps, when the described serial bus data analyser of described mode of operation sign indication be during from analyser, the sub-frequency clock signal that a main analyser is exported is input to described time tag timer;
Described time tag timer is used under the control of described sub-frequency clock signal the generation time label;
Described data transmission module is used for the communication data frame is transmitted, and when finishing the transmission of a communication data frame, sends trigger pip to described the first controller with to described second controller simultaneously;
Described the first controller is used for reading described communication data frame and writing described storer from described data transmission module according to the triggering of described trigger pip;
Described second controller is used for reading time tag and writing the described storer from described time tag timer according to the triggering of described trigger pip;
Described storer is for the time tag of memory communicating Frame and described communication data frame.
A kind of serial bus data analytic system comprises at least two above-mentioned the first serial bus data analysers, wherein, connects by daisy chaining between the reference clock port of described at least dual serial bus data analyser.
The second serial bus data analyser comprises frequency divider, reference clock output port, data transmission module, time tag timer, the first controller, second controller and storer wherein,
Described frequency divider is used for clock signal of system being carried out frequency division, the output frequency division clock signal;
Described reference clock output port is for the serial bus data analyser of described sub-frequency clock signal being exported to other;
Described time tag timer is used under the control of described sub-frequency clock signal the generation time label;
Described data transmission module is used for the communication data frame is transmitted, and when finishing the transmission of a communication data frame, sends trigger pip to described the first controller with to described second controller simultaneously;
Described the first controller is used for reading described communication data frame and writing described storer from described data transmission module according to the triggering of described trigger pip;
Described second controller is used for reading time tag according to the triggering of described trigger pip from described time tag timer, and described time tag is write in the described storer;
Described storer is for the time tag of memory communicating Frame and described communication data frame.
The third serial bus data analyser comprises reference clock input port, data transmission module, time tag timer, the first controller, second controller and storer, wherein,
The reference clock input port is used for the sub-frequency clock signal that other serial bus data analyser is exported is input to described time tag timer;
Described time tag timer is used under the control of described sub-frequency clock signal the generation time label;
Described data transmission module is used for the communication data frame is transmitted, and when finishing the transmission of a communication data frame, sends trigger pip to described the first controller with to described second controller simultaneously;
Described the first controller is used for reading described communication data frame and writing described storer from described data transmission module according to the triggering of described trigger pip;
Described second controller is used for reading time tag according to the triggering of described trigger pip from described time tag timer, and with in the described time tag write store;
Described storer is for the time tag of memory communicating Frame and described communication data frame.
Another kind of serial bus data analytic system, comprise at least dual serial bus data analyser, described at least dual serial bus data analyser comprises above-mentioned the second serial bus data analyser and at least one above-mentioned the third serial bus data analyser, connects by daisy chaining between the reference clock port of described above-mentioned the second serial bus data analyser and at least one above-mentioned the third serial bus data analyser.
As can be seen from the above-described embodiment, determine first the mode of operation of serial bus data analyser instrument, for being in the serial bus data analyser of main analyser mode of operation, in the serial bus data analytic system, be in the reference clock that the time tag timer is provided from the serial bus data analyser of analyser mode of operation as clock source.For being in the serial bus data analyser from the analyser mode of operation, thereby the time tag timer in all serial bus data analysers in the whole serial bus data analytic system that makes that receives that the serial bus data analyser that is in main analyser mode of operation sends has unified time reference.Inner at each serial bus data analyser, whenever finish the transmission of a Frame when data transmission module after, send simultaneously trigger pip to two controllers, in the Frame write store that one of them controller transmits data transmission module under the triggering of trigger pip, simultaneously, another controller reads time tag from the time tag timer under the triggering of trigger pip, and with in the time tag write store.In another kind of serial bus data analytic system, one of them serial bus data analysis of fixed configurations is main analyser from a plurality of serial bus data analyses, and other serial bus data analyser is from analyser.Provide the reference clock of time tag timer to other from analyser as clock source by main analyser, thereby make the time tag timer in all the serial bus data analysers in the whole serial bus data analytic system have unified time reference, and under this time reference, carry out data analysis.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation of an embodiment of a kind of serial bus data analyser of the utility model;
Fig. 2 is the structural representation of an embodiment of a kind of serial bus data analytic system of the utility model;
Fig. 3 is the structural representation of another embodiment of a kind of serial bus data analyser of the utility model;
Fig. 4 is the structural representation of another embodiment of a kind of serial bus data analyser of the utility model;
Fig. 5 is the structural representation of another embodiment of a kind of serial bus data analytic system of the utility model;
Fig. 6 is the structural representation of a kind of CAN serial bus data of the utility model analytic system.
Embodiment
The utility model embodiment provides a kind of serial bus data analytic system and serial bus data analytical approach.In the serial bus data analytic system, can specify one of them serial bus data analyser arbitrarily from a plurality of serial bus data analysers is main analyser, other serial bus data analyser is from analyser, by main analyser as clock source to other provide the reference clock of time tag timer from analyser, thereby make the time tag timer in all serial bus data analysers in the whole serial bus data analytic system have unified time reference.Inner at each serial bus data analyser, whenever finish the transmission of a Frame when data transmission module after, send simultaneously trigger pip to two controllers, in the Frame write store that one of them controller transmits data transmission module under the triggering of trigger pip, simultaneously, another controller reads time tag from the time tag timer under the triggering of trigger pip, and with in the time tag write store.In another kind of serial bus data analytic system, one of them serial bus data analysis of fixed configurations is main analyser from a plurality of serial bus data analyses, and other serial bus data analyser is from analyser.Provide the reference clock of time tag timer to other from analyser as clock source by main analyser, thereby make the time tag timer in all the serial bus data analysers in the whole serial bus data analytic system have unified time reference, and under this time reference, carry out data analysis.
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the utility model embodiment is described in detail.
Embodiment one
See also Fig. 1, it is the structural representation of an embodiment of a kind of serial bus data analyser of the utility model, as shown in Figure 1, this serial bus data analyser 10 comprises: frequency divider 11, master controller 12, two-way reference clock port one 31, time tag timer 14, data transmission module 15, the first control
Device 16 processed, second controller 17 and storer 18, wherein,
Frequency divider 11 is used for clock signal of system being carried out frequency division, the output frequency division clock signal;
Master controller 12, be used for receiving the steering order of carrying the mode of operation sign, described mode of operation is identified, when the described universal serial bus analyser of described mode of operation sign indication is main analyser, allow described sub-frequency clock signal to be sent to time tag timer 14 and two-way reference clock port one 31, when the described serial bus data analyser of described mode of operation sign indication is during from analyser, forbid that described sub-frequency clock signal is sent to clock label timer 14 and reference clock port one 31;
For example, master controller 12 can receive steering order by a built-in or external USB port.After receiving steering order and mode of operation identified, can control an output enable control device by control signal and allow or forbid that the sub-frequency clock signal of frequency divider 11 outputs is sent to time tag timer and two-way reference clock port.Wherein, when the first master controller 12 identifies a serial bus data analyser and is main analyser by mode of operation, be set to the export permit state by control signal output enable control device, allow the sub-frequency clock signal of frequency divider 11 outputs to be sent to time tag timer and two-way reference clock port, at this moment, the reference clock port is equivalent to an output port, sub-frequency clock signal outwards can be exported.When the first master controller 12 identifies a serial bus data analyser for from analyser the time by mode of operation, be set to export illegal state by control signal output enable control device, the sub-frequency clock signal of forbidding frequency divider 11 outputs is sent to time tag timer and two-way reference clock port, at this moment, the reference clock port is equivalent to an input port, can input the clock signal that other serial bus data analyser provides.
Before carrying out data analysis, the first master controller 12 is also according to receiving control signal, and control stops transmitted signal as the analyser that clock source outwards sends reference clock signal, and with the zero clearing of time tag timer.
Two-way reference clock port one 31, be used for when the described serial bus data analyser of described mode of operation sign indication is main analyser, described sub-frequency clock signal is exported at least one from analyser, perhaps, when the described serial bus data analyser of described mode of operation sign indication be during from analyser, the sub-frequency clock signal that a main analyser is exported is input to time tag timer 14;
The first controller 16 is used for reading described communication data frame and write store 18 according to the triggering of described trigger pip from data transmission module 15;
Second controller 17 is used for reading time tag and the write store 18 from time tag timer 14 according to the triggering of described trigger pip;
Storer 18 is for the time tag of memory communicating Frame and described communication data frame.
Preferably, the first controller 16 is a CPU (central processing unit) (CPU), and second controller 17 is a direct memory access controller (DMA).Perhaps, preferred, the first controller 16 and second controller 17 are respectively a direct memory access controller.
Wherein, because DMA is higher than CPU to the priority that universal serial bus takies, therefore, the count value of the time tag timer when DMA can produce trigger pip soon catch and write store 18 in, and can not produce because of the operation of cpu instruction time-delay, the time error of time tag is minimum, can satisfy the time tag timer fully for the requirement of accuracy of timekeeping.
As can be seen from the above-described embodiment, this serial bus data analyser both can be used as a main analyser, provide the reference clock signal of time tag timer to other from analyser as clock source, also can be used as one from analyser, receive the time tag reference clock signal regularly that main analyser provides.Be that the communication data frame is when beating time tag at this serial bus data analyser, at the first controller in data transmission module reading out data and the write store, second controller also reads time tag and write store from the time tag timer at once, thereby makes time tag reflect exactly the time of communication data frame transmission.
Embodiment two
The utility model embodiment also provides a kind of serial bus data analytic system, see also Fig. 2, it is the structural representation of an embodiment of a kind of serial bus data analytic system of the utility model, as shown in Figure 2, this serial bus data analytic system 20 comprises: at least two universal serial bus analysers 10 of describing in embodiment one, wherein, connect by daisy chaining between the reference clock port of described at least dual serial bus data analyser 10.
Wherein, the connected mode of so-called daisy chain is, the reference clock port of serial bus data analyser 1 is connected with the reference clock port of serial bus data analyser 2, the reference clock port of serial bus data analyser 2 is connected with the reference clock port of serial bus data analyser 3 ...., the reference clock port of serial bus data analyser N-1 is connected with the reference clock port of serial bus data analyser N.
For example, in this universal serial bus analytic system, mode of operation entrained in the control signal of the central control unit in the serial bus data analyser 1 according to reception identifies, when determining that serial bus data analyser 1 is main analyser, the permission sub-frequency clock signal is sent to time tag timer and the two-way reference clock port in the serial bus data analyser 1, and two-way reference clock port is exported to sub-frequency clock signal from analyser as output port.Simultaneously, mode of operation entrained in the control signal of the central control unit among the serial bus data analyser 2-N according to reception identifies, determine that serial bus data analyser 2-N is for from analyser the time, forbid that sub-frequency clock signal is sent to time tag timer and the two-way reference clock port among the serial bus data analyser 2-N, with a main analyser, the sub-frequency clock signal of namely serial bus data analyser 1 output is input to the time tag timer of serial bus data analyser 2-N to two-way reference clock port as input port.
Because the inner structure of serial bus data analyser 10 describes in detail in embodiment one, can referring to the description of implementing in, repeat no more in the present embodiment about the inner structure of serial bus data analyser 10.
As can be seen from the above-described embodiment, this serial bus data analyser both can be used as a main analyser, provide the reference clock signal of time tag timer to other from analyser as clock source, also can be used as one from analyser, receive the time tag reference clock signal regularly that main analyser provides.Be that the communication data frame is when beating time tag at this serial bus data analyser, at the first controller from data transmission module in reading out data and the write store, second controller also reads time tag and write store at once from the time tag timer, thereby makes time tag reflect exactly the time of communication data frame transmission.Like this, in whole serial bus data analytic system, not only can realize the communication data frame from different serial bus data analysers is carried out data analysis by time tag, can also be clock source by specifying at random any one serial bus data analyser, realize flexible configuration.
Embodiment three
The utility model embodiment also provides another kind of serial bus data analyser, the difference of the serial bus data analyser that present embodiment and embodiment one provide is, the serial bus data analyser in the present embodiment only can as main analyser to other from analyser output reference clock signal.See also Fig. 3, it is the structural representation of another embodiment of a kind of serial bus data analyser of the utility model, and this serial bus data analyser 30 comprises: frequency divider 11, reference clock output port 132, time tag timer 14, data transmission module 15, the first controller 16, second controller 17 and storer 18;
Frequency divider 11 is used for clock signal of system being carried out frequency division, the signal behind the output frequency division;
Reference clock output port 132 is for the serial bus data analyser of described sub-frequency clock signal being exported to other;
The first controller 16 is used for reading described communication data frame and write store 18 according to the triggering of described trigger pip from data transmission module 15;
Second controller 17 is used for reading time tag according to the triggering of described trigger pip from time tag timer 14, and with in the described time tag write store 18;
Storer 18 is for the time tag of memory communicating Frame and described communication data frame.
Preferably, the first controller 16 is a CPU (central processing unit) (CPU), and second controller 17 is a direct memory access controller (DMA).Perhaps, preferred, the first controller 16 and second controller 17 are respectively a direct memory access controller.
As can be seen from the above-described embodiment, the sub-frequency clock signal of directly frequency divider being exported on the one hand is as the reference clock signal of time tag timer, on the other hand, will sub-frequency clock signal be offered by the reference clock output port other serial bus data analyser as clock source.Be that the communication data frame is when beating time tag at this serial bus data analyser, at the first controller in data transmission module reading out data and the write store, second controller also reads time tag and write store from the time tag timer at once, thereby makes time tag reflect exactly the time of communication data frame transmission.
Embodiment four
The utility model embodiment also provides another kind of serial bus data analyser, the difference of the serial bus data analyser that present embodiment and embodiment one provide is, serial bus data analyser in the present embodiment only can as from analyser, receive the reference clock signal of other main analyser output.See also Fig. 4, it is the structural representation of another embodiment of a kind of serial bus data analyser of the utility model, and this serial bus data analyser 40 comprises: reference clock input port 133, time tag timer 14, data transmission module 15, the first controller 16, second controller 17 and storer 18; Wherein,
Reference clock input port 133 is used for the sub-frequency clock signal that other serial bus data analyser is exported is input to time tag timer 14;
The first controller 16 is used for reading described communication data frame and write store 18 according to the triggering of described trigger pip from data transmission module 15;
Second controller 17 is used for reading time tag according to the triggering of described trigger pip from time tag timer 14, and with in the described time tag write store 18;
Storer 18 is for the time tag of memory communicating Frame and described communication data frame.
Preferably, the first controller 16 is a CPU (central processing unit) (CPU), and second controller 17 is a direct memory access controller (DMA).Perhaps, preferred, the first controller 16 and second controller 17 are respectively a direct memory access controller.
As can be seen from the above-described embodiment, the reference clock signal of generation time label timer not in this serial bus data analyser, but the sub-frequency clock signal of other serial bus data analyser being exported by the reference clock input port is input to the time tag timer, as the reference clock signal of time tag timer.Be that the communication data frame is when beating time tag at this serial bus data analyser, at the first controller in data transmission module reading out data and the write store, second controller also reads time tag and write store from the time tag timer at once, thereby makes time tag reflect exactly the time of communication data frame transmission.
Embodiment five
The utility model embodiment also provides a kind of serial bus data analytic system.The difference of the system that present embodiment and embodiment two provide is, in this system, main analyser and be fixed configurations from analyser cannot exchange arbitrarily.That is to say that main analyser can only be as main analyser, and can not be set to from analyser again, same, also can only be as from analyser from analyser, and can not be set to main analyser.See also Fig. 5, it is the structural representation of another embodiment of a kind of serial bus data analytic system of the utility model, this serial bus data analytic system 50 comprises between the reference clock port of the reference clock port of a serial bus data analyser of describing in embodiment three 30 and at least one 40, one serial bus data analyser 30 of serial bus data analyser of describing in embodiment four and at least one serial bus data analyser 40 and connecting by daisy chaining.
For example, in this universal serial bus analytic system, after the frequency divider output frequency division clock signal in the serial bus data analyser 1, the time tag timer with sub-frequency clock signal as reference clock signal, the generation time label, the reference clock output port is exported this other serial bus data analyser with this sub-frequency clock signal.In serial bus data analyser 2-N, the reference clock input port is input to the time tag timer with the sub-frequency clock signal of serial bus data analyser 1 output, the time tag timer with the sub-frequency clock signal of serial bus data analyser 1 output as reference clock signal, the generation time label.
Because the inner structure of serial bus data analyser 30 describes in detail in embodiment three, the inner structure of serial bus data analyser 40 describes in detail in embodiment four, inner structure about serial bus data analyser 30 and 40 can respectively referring to the description of implementing in three and four, repeat no more in the present embodiment.
As can be seen from the above-described embodiment, in main analyser, the sub-frequency clock signal of directly frequency divider being exported on the one hand is as the reference clock signal of time tag timer, on the other hand, will sub-frequency clock signal be offered by the reference clock output port other serial bus data analyser as clock source.And at the reference clock signal of generation time label timer not from analyser, but the sub-frequency clock signal of other serial bus data analyser being exported by the reference clock input port is input to the time tag timer, as the reference clock signal of time tag timer.Be that the communication data frame is when beating time tag at this serial bus data analyser, at the first controller in data transmission module reading out data and the write store, second controller also reads time tag and write store from the time tag timer at once, thereby makes time tag reflect exactly the time of communication data frame transmission.
Take to the analysis of CAN serial bus data as example, see also Fig. 6, it is the structural representation of a kind of CAN serial bus data of the utility model analytic system.As shown in Figure 6, reference clock port between the CAN serial bus data analyser adopts concentric cable (Sync cable) and links together by the mode of daisy chain, as the reference clock signal path of the time tag timer on the CAN serial bus data analyser.The USB control port of each CAN serial bus data analyser accesses computing machine by usb hub, the user control program that moves on the computing machine sends control command to each CAN serial bus data analyser, order all CAN serial bus data analysers to stop the tranmitting data register signal or stop the receive clock signal, and order all CAN serial bus data analysers with the zero clearing of time tag timer.The user control program that moves on computing machine has monitored the access of CAN serial bus data analyser or has withdrawed from said reference clock signal path, just carries out aforesaid operations one time.After all CAN serial bus data analysers are finished aforesaid operations, be sent completely message to computing machine.User control program sends the steering order of carrying the mode of operation sign to each CAN serial bus data analyser, suppose that the mode of operation sign indication CAN serial bus data analyser 1 in the steering order is main analyser, CAN serial bus data analyser 2-N is from analyser, then CAN serial bus data analyser 1 by concentric cable to CAN serial bus data analyser 2-N tranmitting data register signal, simultaneously, CAN serial bus data analyser 2-N receives the clock signal that CAN serial bus data analyser 1 sends, and this clock signal is the reference clock signal of the time tag timer on the CAN serial bus data analyser 1-N.
Need to prove, serial bus data analyser, analytic system and the analytical approach that provides among each embodiment of the utility model is applicable to various types of serial bus data analysers and analytic system, as, CAN (Controller Area Network, controller local area network) serial bus data analyser and analytic system.
Need to prove, one of ordinary skill in the art will appreciate that all or part of flow process that realizes in above-described embodiment method, to come the relevant hardware of instruction to finish by computer program, described program can be stored in the computer read/write memory medium, this program can comprise the flow process such as the embodiment of above-mentioned each side method when carrying out.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-Only Memory, ROM) or store-memory body (Random Access Memory, RAM) etc. at random.
More than a kind of serial bus data analyser provided by the utility model and analytic system are described in detail, used specific embodiment herein principle of the present utility model and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present utility model and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present utility model, all will change in specific embodiments and applications, in sum, this description should not be construed as restriction of the present utility model.
Claims (13)
1. a serial bus data analyser is characterized in that, comprises frequency divider, master controller, two-way reference clock port, time tag timer, data transmission module, the first controller, second controller and storer, wherein,
Described frequency divider is used for clock signal of system being carried out frequency division, the output frequency division clock signal;
Described master controller, be used for receiving the steering order of carrying the mode of operation sign, described mode of operation is identified, when the described serial bus data analyser of described mode of operation sign indication is main analyser, allow described sub-frequency clock signal to be sent to described time tag timer and described two-way reference clock port, when the described serial bus data analyser of described mode of operation sign indication is during from analyser, forbid that described sub-frequency clock signal is sent to described clock label timer and two-way reference clock port;
Described two-way reference clock port, be used for when the described serial bus data analyser of described mode of operation sign indication is main analyser, described sub-frequency clock signal is exported at least one from analyser, perhaps, when the described serial bus data analyser of described mode of operation sign indication be during from analyser, the sub-frequency clock signal that a main analyser is exported is input to described time tag timer;
Described time tag timer is used under the control of described sub-frequency clock signal the generation time label;
Described data transmission module is used for the communication data frame is transmitted, and when finishing the transmission of a communication data frame, sends trigger pip to described the first controller with to described second controller simultaneously;
Described the first controller is used for reading described communication data frame and writing described storer from described data transmission module according to the triggering of described trigger pip;
Described second controller is used for reading time tag and writing the described storer from described time tag timer according to the triggering of described trigger pip;
Described storer is for the time tag of memory communicating Frame and described communication data frame.
2. analyser according to claim 1 is characterized in that, described the first controller is central processing unit CPU, and described second controller is direct memory access controller DMA.
3. analyser according to claim 1 is characterized in that, described the first controller and second is controlled to be direct memory access controller DMA.
4. serial bus data analytic system, it is characterized in that, comprise at least two such as the described serial bus data analyser of any one among the claim 1-3, wherein, connect by daisy chaining between the reference clock port of described at least dual serial bus data analyser.
5. system according to claim 4 is characterized in that, it is coaxial wire that described daisy chaining connects the wire that adopts.
6. a serial bus data analyser is characterized in that, comprises frequency divider, reference clock output port, data transmission module, time tag timer, the first controller, second controller and storer wherein,
Described frequency divider is used for clock signal of system being carried out frequency division, the output frequency division clock signal;
Described reference clock output port is for the serial bus data analyser of described sub-frequency clock signal being exported to other;
Described time tag timer is used under the control of described sub-frequency clock signal the generation time label;
Described data transmission module is used for the communication data frame is transmitted, and when finishing the transmission of a communication data frame, sends trigger pip to described the first controller with to described second controller simultaneously;
Described the first controller is used for reading described communication data frame and writing described storer from described data transmission module according to the triggering of described trigger pip;
Described second controller is used for reading time tag according to the triggering of described trigger pip from described time tag timer, and described time tag is write in the described storer;
Described storer is for the time tag of memory communicating Frame and described communication data frame.
7. analyser according to claim 6 is characterized in that, described the first controller is central processing unit CPU, and described second controller is direct memory access controller DMA.
8. analyser according to claim 6 is characterized in that, described the first controller and second is controlled to be direct memory access controller DMA.
9. a serial bus data analyser is characterized in that, comprises reference clock input port, data transmission module, time tag timer, the first controller, second controller and storer, wherein,
The reference clock input port is used for the sub-frequency clock signal that other serial bus data analyser is exported is input to described time tag timer;
Described time tag timer is used under the control of described sub-frequency clock signal the generation time label;
Described data transmission module is used for the communication data frame is transmitted, and when finishing the transmission of a communication data frame, sends trigger pip to described the first controller with to described second controller simultaneously;
Described the first controller is used for reading described communication data frame and writing described storer from described data transmission module according to the triggering of described trigger pip;
Described second controller is used for reading time tag according to the triggering of described trigger pip from described time tag timer, and with in the described time tag write store;
Described storer is for the time tag of memory communicating Frame and described communication data frame.
10. analyser according to claim 9 is characterized in that, described the first controller is central processing unit CPU, and described second controller is direct memory access controller DMA.
11. analyser according to claim 9 is characterized in that, described the first controller and second is controlled to be direct memory access controller DMA.
12. serial bus data analytic system, it is characterized in that, comprise at least dual serial bus data analyser, described at least dual serial bus data analyser comprise one such as the described serial bus data analyser of any one among the claim 6-8 and at least one such as the described serial bus data analyser of any one among the claim 9-11, described one as connecting by daisy chaining between the described serial bus data analyser of any one among the claim 6-8 and at least one the reference clock port such as the described serial bus data analyser of any one among the claim 9-11.
13. system according to claim 12 is characterized in that, it is coaxial wire that described daisy chaining connects the wire that adopts.
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| CN 201220389726 CN202795349U (en) | 2012-08-07 | 2012-08-07 | Serial bus data analyzer and analysis system |
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| CN 201220389726 CN202795349U (en) | 2012-08-07 | 2012-08-07 | Serial bus data analyzer and analysis system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103427977A (en) * | 2013-09-03 | 2013-12-04 | 上海聚星仪器有限公司 | Method for achieving synchronous collection of multiple devices through single-channel analogue signal |
| CN104579876A (en) * | 2013-10-10 | 2015-04-29 | 大唐恩智浦半导体有限公司 | Daisy-chain communication bus and protocol |
| CN106445874A (en) * | 2016-11-07 | 2017-02-22 | 衢州学院 | Novel serial bus data analyzer |
-
2012
- 2012-08-07 CN CN 201220389726 patent/CN202795349U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103427977A (en) * | 2013-09-03 | 2013-12-04 | 上海聚星仪器有限公司 | Method for achieving synchronous collection of multiple devices through single-channel analogue signal |
| CN104579876A (en) * | 2013-10-10 | 2015-04-29 | 大唐恩智浦半导体有限公司 | Daisy-chain communication bus and protocol |
| CN106445874A (en) * | 2016-11-07 | 2017-02-22 | 衢州学院 | Novel serial bus data analyzer |
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