CN203746067U - Multi-path ARINC 429 data receiving and transmitting circuit structure based on DSP and CPLD development - Google Patents
Multi-path ARINC 429 data receiving and transmitting circuit structure based on DSP and CPLD development Download PDFInfo
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- CN203746067U CN203746067U CN201420136421.2U CN201420136421U CN203746067U CN 203746067 U CN203746067 U CN 203746067U CN 201420136421 U CN201420136421 U CN 201420136421U CN 203746067 U CN203746067 U CN 203746067U
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Abstract
The utility model discloses a multi-path ARINC 429 data receiving and transmitting circuit structure based on DSP and CPLD development. The multi-path ARINC 429 data receiving and transmitting circuit structure comprises a DSP circuit, a plurality of ARINC 429 bus receiving and transmitting chip circuits and an assist control circuit realized through CPLD programming, wherein the data ends of ARINC 429 bus receiving and transmitting chips are connected with a DSP, the control ends of the ARINC 429 bus receiving and transmitting chips are connected with a CPLD, the DSP circuit sends a control instruction to a register circuit realized through CPLD chip programming to realize control over the ARINC 429 bus receiving and transmitting chips, and decoding receiving and coding sending of ARINC 429 data are realized through programming of software in a DSP chip. According to the multi-channel ARINC 429 data receiving and transmitting circuit structure based on DSP and CPLD development, multiple paths of ARINC 429 data can be read and sent in real time through a DSP chip data bus, data collision, data loss and error codes are avoided, and high-speed processing on data is achieved.
Description
Technical field
The utility model relates to the technical field of ARINC429 data transmit-receive circuit, is specifically related to a kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation.
Background technology
At present, the known ARINC429 data transmit-receive circuit based on DSP and FPGA is made up of DSP circuit, FPGA circuit and ARINC429 bus transceiving chip circuit, while carrying out multichannel data reception, the ways that adopt FPGA algorithm exampleization more, although this design has multichannel transmitting-receiving ability, multiplexer channel synchronization receives ARINC429 data and easily occurs data collision, loss and error code.And known multi-channel A RINC429 receiving circuit based on DSP and CPLD takies the too much external interrupt of DSP, make DSP very limited in circuit function, and in the time that receiving and dispatching, multichannel data synchronization easily there is communication conflict, make in DSP deal with data process, easily occur that the reception of multi-channel A RINC429 data is lost.
Utility model content
The utility model is intended to overcome deficiency of the prior art, a kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation is provided, the data bus direct read/write that this data transmit-receive circuit structure can not only be applied dsp chip is organized the data terminal of ARINC429 bus transceiving chip more, utilize CPLD(CPLD) programming realize register circuit control sequential and logical relation, and multiple external interrupt signals of many groups ARINC429 bus transceiving chip are integrated, greatly save the use to DSP external interrupt resource, effectively avoid data collision, lose and error code.
The utility model solves the problems of the technologies described above adopted technical scheme: a kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation, comprise DSP circuit, many group ARINC429 bus transceiving chip circuit, also comprise the register circuit of being realized by CPLD chip programming;
Data bus XD0～the XD15 of described DSP circuit is connected with the data bus BD00～BD15 of described many group ARINC429 bus transceiving chip circuit by electrical level matching circuit, the steering order end D429_A0～D429_A7 of described DSP circuit, steering order completes excitation end D429_ARDY, data send state end D429_TX/R, data send Enable Pin D429_ENTX, comprehensive receive interruption port D429_RINT, the steering order end D429_A0～D429_A7 of receiving cable coded address end D429_RINTA0～D429_RINTA3 and the described register circuit of being realized by CPLD chip programming, steering order completes excitation end D429_ARDY, data send state end D429_TX/R, data send Enable Pin D429_ENTX, comprehensive receive interruption port D429_RINT, receiving cable coded address end D429_RINTA0～D429_RINTA3 is corresponding to be connected, described many group ARINC429 bus transceiving chip circuit comprise 4 groups, can receive 8 road ARINC429 data simultaneously, send 4 road ARINC429 data, the data sink 1 receive interruption port of the 1st group of transmission circuit wherein
data sink 2 receive interruption ports
receive high/low 16 of data and read selecting side SEL, data sink 1 Enable Pin
data sink 2 Enable Pins
send low 16 of data and write selecting side
send high 16 of data and write selecting side
data send state end TX/R, data send Enable Pin ENTX, chip configuration Enable Pin
the data sink 1 receive interruption port C429A_RDY1 of the 1st group of transmission circuit by electrical level matching circuit and the described register circuit of being realized by CPLD chip programming, the data sink 2 receive interruption port C429A_RDY2 of the 1st group of transmission circuit, high/low 16 of the reception data of the 1st group of transmission circuit read selecting side C429A_SEL, the data sink 1 Enable Pin C429A_EN1 of the 1st group of transmission circuit, the data sink 2 Enable Pin C429A_EN2 of the 1st group of transmission circuit, low 16 of the transmission data of the 1st group of transmission circuit write selecting side C429A_PL1, high 16 of the transmission data of the 1st group of transmission circuit write selecting side C429A_PL2, the data of the 1st group of transmission circuit send state end C429A_TX/R, the data of the 1st group of transmission circuit send Enable Pin C429A_ENTX, the corresponding connection of chip configuration Enable Pin C429A_CWSTR of the 1st group of transmission circuit, the 2nd group of transmission circuit
sEL,
tX/R, ENTX,
end is by the data sink 1 receive interruption port C429B_RDY1 of the 2nd group of transmission circuit of electrical level matching circuit and the described register circuit of being realized by CPLD chip programming, the data sink 2 receive interruption port C429B_RDY2 of the 2nd group of transmission circuit, high/low 16 of the reception data of the 2nd group of transmission circuit read selection C429B_SEL, the data sink 1 Enable Pin C429B_EN1 of the 2nd group of transmission circuit, the data sink 2 Enable Pin C429B_EN2 of the 2nd group of transmission circuit, low 16 of the transmission data of the 2nd group of transmission circuit write selecting side C429B_PL1, high 16 of the transmission data of the 2nd group of transmission circuit write selecting side C429B_PL2, the data of the 2nd group of transmission circuit send state end C429B_TX/R, the data of the 2nd group of transmission circuit send Enable Pin C429B_ENTX, the corresponding connection of chip configuration Enable Pin C429B_CWSTR of the 2nd group of transmission circuit, the 3rd group of transmission circuit
sEL,
tX/R, ENTX,
end is by the data sink 1 receive interruption port C429C_RDY1 of the 3rd group of transmission circuit of electrical level matching circuit and the described register circuit of being realized by CPLD chip programming, the data sink 2 receive interruption port C429C_RDY2 of the 3rd group of transmission circuit, high/low 16 of the reception data of the 3rd group of transmission circuit read selecting side C429C_SEL, the data sink 1 Enable Pin C429C_EN1 of the 3rd group of transmission circuit, the data sink 2 Enable Pin C429C_EN2 of the 3rd group of transmission circuit, low 16 of the transmission data of the 3rd group of transmission circuit write selecting side C429C_PL1, high 16 of the transmission data of the 3rd group of transmission circuit write selecting side C429C_PL2, the data of the 3rd group of transmission circuit send state end C429C_TX/R, the data of the 3rd group of transmission circuit send Enable Pin C429C_ENTX, the corresponding connection of chip configuration Enable Pin C429C_CWSTR of the 3rd group of transmission circuit, the 4th group of transmission circuit
sEL,
tX/R, ENTX,
end is by the data sink 1 receive interruption port C429D_RDY1 of the 4th group of transmission circuit of electrical level matching circuit and the described register circuit of being realized by CPLD chip programming, the data sink 2 receive interruption port C429D_RDY2 of the 4th group of transmission circuit, high/low 16 of the reception data of the 4th group of transmission circuit read selecting side C429D_SEL, the data sink 1 Enable Pin C429D_EN1 of the 4th group of transmission circuit, the data sink 2 Enable Pin C429D_EN2 of the 4th group of transmission circuit, low 16 of the transmission data of the 4th group of transmission circuit write selecting side C429D_PL1, high 16 of the transmission data of the 4th group of transmission circuit write selecting side C429D_PL2, the data of the 4th group of transmission circuit send state end C429D_TX/R, the data of the 4th group of transmission circuit send Enable Pin C429D_ENTX, the corresponding connection of chip configuration Enable Pin C429D_CWSTR of the 4th group of transmission circuit.
Wherein, the chip that described DSP circuit adopts is TMS320F28335.
Wherein, the chip that the register circuit that described CPLD chip programming is realized adopts is EPM570.
Wherein, the chip that described ARINC429 bus transceiving chip circuit adopts is HS3282 and HS3182.
Principle of the present utility model is:
As Figure 1-5, a kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation, comprises DSP circuit 1, organizes ARINC429 bus transceiving chip circuit 2 more, also comprises the register circuit 3 of being realized by CPLD chip programming; By the data bus terminal of the many groups of DSP circuit 1 read-write ARINC429 bus transceiving chip circuit 2, realize the control to many groups ARINC429 bus transceiving chip to register circuit 3 sending controling instructions of being realized by CPLD chip programming.First coordinate DSP circuit 1, by data bus, configuration signal is passed to many group ARINC429 bus transceiving chip circuit 2 successively by register circuit 3, the ARINC429 bus transceiving chip having configured receives ARINC429 data by serial line interface, any road serial line interface receives after ARINC429 data, D429_RINT is held reset by the register circuit 3 of being realized by CPLD chip programming, to trigger the external interrupt of DSP circuit 1, DSP circuit 1 judges the concrete receiving cable of ARINC429 data by reading D429_RINTA0～D429RINTA3, hold negative edge signal of generation to read the ARINC429 data of corresponding receiving cable by the steering order of configuration D429_A0～D429_A7 end with at D429_ARDY again, because the data bus of ARINC429 bus transceiving chip is 16, and the transceiving format of ARINC429 data is 32, therefore read road ARINC429 data, DSP circuit 1 needs double operation D429_A0～D429_A7 and D429_ARDY end, after current read data operation completes, DSP circuit 1 detects D429_RINT port status, if D429_RINT holds register circuit 3 sets that realized by CPLD chip programming, show that current read operation completes, if D429_RINT holds register circuit 3 resets that realized by CPLD chip programming, indicate that multi-path serial interface receives ARINC429 data simultaneously, or receive other follow-up ARINC429 data when other road serial line interfaces in the process of the ARINC429 data that front port receives reading, now DSP circuit 1 again reads D429_RINTA0～D429RINTA3 and judges the concrete receiving cable of not reading ARINC429 data, and repeat aforementioned read operation process, and again detect D429_RINT port status, until register circuit 3 sets that D429_RINT port is realized by CPLD chip programming detected.When the ARINC429 bus transceiving chip having configured sends ARINC429 data by serial line interface, DSP circuit 1 is according to the steering order of the corresponding configuration of the transmission interface of wanting required use D429_A0～D429_A7 end and generate a negative edge signal and write the ARINC429 data of corresponding transmission interface at D429_ARDY end, because the data bus of ARINC429 bus transceiving chip is 16, and the transceiving format of ARINC429 data is 32, therefore send road ARINC429 data, DSP circuit 1 needs double operation D429_A0～D429_A7 and D429_ARDY end, DSP circuit 1 detects the state of D429_TX/R end afterwards, after D429_TX/R end is by reset, D429_ENTX is held set by DSP circuit 1, then DSP circuit 1 detects the state of D429_TX/R end again, after D429_TX/R end is by set, D429_ENTX is held reset by DSP circuit 1.
The various circuit that adopt in this circuit are all bus read modes at a high speed, control transmitting-receiving sequential and the logical relation of multi-channel A RINC429 data by the register circuit 3 of being realized by CPLD chip programming, avoid occurring multichannel data conflict, loss of data and error code, and connect the reset signal of ARINC429 bus transceiving chip by dsp chip, to make ARINC429 bus transceiving chip reset the in the situation that of data from overflow, ensure data normal transmission.
Compared with prior art, the beneficial effects of the utility model are:
1, the utility model can be read multi-channel A RINC429 data in real time and be sent by dsp chip data bus, avoids data collision, loss and error code, realizes the high speed processing to data.
2, multiple external interrupt signals of organizing ARINC429 bus transceiving chip are integrated into one by the utility model circuit structure more, greatly reduce the usage quantity of DSP circuit external interrupt, the in the situation that of DSP external interrupt resource-constrained, make more multi-channel A RINC429 data transmit-receive become possibility, thoroughly solved data collision when multi-channel A RINC429 data are accepted simultaneously, and data in data handling procedure are lost a yard problem.
3, the utility model circuit structure is comparatively succinct, and the sequential confusion while having avoided transceiving data has been saved a large amount of computational resources of DSP inside, rationally distributed, easy to operate, cost is low.
Brief description of the drawings
Fig. 1 is circuit structure structural diagrams intention of the present utility model;
Fig. 2 is the detailed signal processing algorithm schematic diagram of the utility model specific embodiment;
Fig. 3 is the DSP circuit theory diagrams of the utility model specific embodiment;
Fig. 4 is the ARINC429 bus transceiving chip circuit theory diagrams of the utility model specific embodiment;
Fig. 5 is the register circuit schematic diagram that the CPLD chip programming of the utility model specific embodiment is realized;
Fig. 6 is the transmission example waveform of the ARINC429 bus data 0x8025806A of the utility model specific embodiment;
Fig. 7 is the reception example waveform of the ARINC429 bus data 0x03958584 of the utility model specific embodiment.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further described.The utility model, to receive 8 road ARINC429 data, sends 4 road ARINC429 data instances and describes.All brackets " (transmission) " and " (reception) " only represent data and sense.
In Fig. 1, the closure of each functional block diagram and arrow has represented basic circuit principle of the present utility model and signal controlling relation, based on the multi-channel A RINC429 data transmit-receive circuit of DSP and CPLD exploitation, comprise DSP circuit 1, also comprise many group ARINC429 bus transceiving chip circuit 2 and the register circuit 3 of being realized by CPLD chip programming;
Below in conjunction with accompanying drawing 2-accompanying drawing 4, the utility model is further illustrated.
16 bit data bus XD0～XD15 of described DSP circuit 1 are connected with the data bus BD00～BD15 of described many group ARINC429 bus transceiving chip circuit 2 by electrical level matching circuit;
Control output end D429_A0～D429_A7, D429_ARDY, the D429_ENTX end of described DSP circuit 1 are held corresponding connection with control input end D429_A0～D429_A7, D429_ARDY, the D429_ENTX of the described register circuit of being realized by CPLD chip programming 3;
Data accepted flag transmitting terminal D429_RINT, the D429_RINTA0～D429_RINTA3 of the described register circuit of being realized by CPLD chip programming 3 is connected with data accepted flag receiving end D429_RINT and the D429_RINTA0～D429_RINTA3 of described DSP circuit 1;
The ARINC429 data of the described register circuit of being realized by CPLD chip programming 3 send state output end D429_TX/R and are connected with the data transmission state input end D429_TX/R of described DSP circuit 1;
Described many group ARINC429 bus transceiving chip circuit comprise 4 groups, the read-write control end SEL of the 1st group of transmission circuit wherein,
eNTX,
input end is by being connected with read-write control output end C429A_SEL, C429A_EN1, C429A_EN2, C429A_PL1, C429A_PL2, C429A_ENTX, the C429A_CWSTR of register circuit 3 respectively after electrical level matching circuit, the read-write control end SEL of the 2nd group of transmission circuit,
eNTX,
input end is by being connected with read-write control output end C429B_SEL, C429B_EN1, C429B_EN2, C429B_PL1, C429B_PL2, C429B_ENTX, the C429B_CWSTR of register circuit 3 respectively after electrical level matching circuit, the read-write control end SEL of the 3rd group of transmission circuit,
eNTX,
input end is by being connected with read-write control output end C429C_SEL, C429C_EN1, C429C_EN2, C429C_PL1, C429C_PL2, C429C_ENTX, the C429C_CWSTR of register circuit 3 respectively after electrical level matching circuit, the read-write control end SEL of the 4th group of transmission circuit,
eNTX,
input end is connected with read-write control output end C429D_SEL, C429D_EN1, C429D_EN2, C429D_PL1, C429D_PL2, C429D_ENTX, the C429D_CWSTR of register circuit 3 respectively by after electrical level matching circuit;
The reiving/transmitting state output terminal of the 1st group of transmission circuit in described many group ARINC429 bus transceiving chip circuit 2
the corresponding connection of reiving/transmitting state input end C429A_RDY1, C429A_RDY2, C429A_TX/R of the register circuit 3 that TX/R realizes with described CPLD chip programming by electrical level matching circuit, the reiving/transmitting state output terminal of the 2nd group of transmission circuit
the corresponding connection of reiving/transmitting state input end C429B_RDY1, C429B_RDY2, C429B_TX/R of the register circuit 3 that TX/R realizes with described CPLD chip programming by electrical level matching circuit, the reiving/transmitting state output terminal of the 3rd group of transmission circuit
the corresponding connection of reiving/transmitting state input end C429C_RDY1, C429C_RDY2, C429C_TX/R of the register circuit 3 that TX/R realizes with described CPLD chip programming by electrical level matching circuit, the reiving/transmitting state output terminal of the 4th group of transmission circuit
the corresponding connection of reiving/transmitting state input end C429D_RDY1, C429D_RDY2, C429D_TX/R of the register circuit 3 that TX/R realizes with described CPLD chip programming by electrical level matching circuit.
According to above-mentioned connected mode, as shown in Figure 2, the steering order that DSP circuit sends at D429_A0～D429_A7 comprises the instruction of ARINC429 bus transceiving chip initial configuration, ARINC429 bus receives data reading command, ARINC429 bus sends data and writes instruction, receive after these one-level steering orders, the register circuit of being realized by CPLD programming is by the read-write control end of direct control corresponding A RINC429 bus transceiving chip after electrical level matching circuit, also decoding goes out secondary steering order contained in one-level steering order simultaneously, the data of indicating corresponding ARINC429 bus transceiving chip circuit in one-level instruction are sent state end (C429A_TX/R by secondary steering order, C429B_TX/R, C429C_TX/R or C429D_TX/R) the level state data that copy to the register circuit of being realized by CPLD programming send states (transmissions) and hold D429_TX/R to judge for DSP electric circuit inspection, and the data transmission Enable Pin D429_ENTX level state of the register circuit of realizing being programmed by CPLD copies to the data transmission Enable Pin (C429A_ENTX of corresponding ARINC429 bus transceiving chip, C429B_ENTX, C429C_ENTX or C429D_ENTX) to realize DSP circuit, the data of ARINC429 bus transceiving chip circuit are sent and enabled.In the time receiving ARINC429 data, the register circuit of being realized by CPLD programming is all the time by receive interruption (reception) port (C429A_RDY1 of 8 road ARINC429 bus receiving cables, C429A_RDY2, C429B_RDY1, C429B_RDY2, C429C_RDY1, C429C_RDY2, C429D_RDY1, C429D_RDY2) comprehensive Wei Yi road comprehensive receive interruption port D429_RINT, in the time interrupting occurring, receiving cable coded address (transmission) end D429_RINTA0～D429_RINTA3 is sent to in current receiving cable coded address to interrupt reading for DSP circuit, if Multiple Interrupt occurs or new receive interruption occurs when reading out data simultaneously, DSP circuit completes after current data read operation, comprehensive receive interruption port D429_RINT maintains interruption status, and other are not sent to receiving cable coded address (transmission) end D429_RINTA0～D429_RINTA3 in the channel coding address of read channel, realize whole receiving circuit with this accurate, high speed processing, avoid data collision, lose and error code.
The chip that DSP circuit described in the utility model adopts is TMS320F28335.
CPLD chip described in the utility model adopts EPM570.
The chip that ARINC429 bus transceiving chip circuit described in the utility model adopts is HS3282 and HS3182.
Fig. 5 is the register circuit schematic diagram that the CPLD chip programming of the utility model specific embodiment is realized;
Fig. 6 is the transmission example waveform of the ARINC429 bus data 0x8025806A of the utility model specific embodiment; This transmission example waveform is the schematic diagram that the utility model correct coding is sent out several.
Fig. 7 is the reception example waveform of the ARINC429 bus data 0x03958584 of the utility model specific embodiment.This reception example waveform is that the utility model correctly, is inerrably encoded and received the schematic diagram of number.
The not detailed disclosed part of the utility model belongs to the known technology of this area.
Although above the illustrative embodiment of the utility model is described; so that those skilled in the art understand the utility model; but should be clear; the utility model is not limited to the scope of embodiment; to those skilled in the art; as long as various variations appended claim limit and the spirit and scope of the present utility model determined in; these variations are apparent, and all innovation and creation that utilize the utility model design are all at the row of protection.
Claims (4)
1. the multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation, comprises DSP circuit (1), organizes ARINC429 bus transceiving chip circuit (2) more, characterized by further comprising the register circuit (3) of being realized by CPLD chip programming;
Data bus XD0～the XD15 of described DSP circuit (1) is connected with the data bus BD00～BD15 of described many group ARINC429 bus transceiving chip circuit (2) by electrical level matching circuit, the steering order end D429_A0～D429_A7 of described DSP circuit (1), steering order completes excitation end D429_ARDY, data send state end D429_TX/R, data send Enable Pin D429_ENTX, comprehensive receive interruption port D429_RINT, the steering order end D429_A0～D429_A7 of receiving cable coded address end D429_RINTA0～D429_RINTA3 and the described register circuit of being realized by CPLD chip programming (3), steering order completes excitation end D429_ARDY, data send state end D429_TX/R, data send Enable Pin D429_ENTX, comprehensive receive interruption port D429_RINT, receiving cable coded address end D429_RINTA0～D429_RINTA3 is corresponding to be connected, described many group ARINC429 bus transceiving chip circuit (2) comprise 4 groups, can receive 8 road ARINC429 data simultaneously, send 4 road ARINC429 data, the data sink 1 receive interruption port of the 1st group of transmission circuit wherein
data sink 2 receive interruption ports
receive high/low 16 of data and read selecting side SEL, data sink 1 Enable Pin
data sink 2 Enable Pins
, send low 16 of data write selecting side
send high 16 of data and write selecting side
data send state end TX/R, data send Enable Pin ENTX, chip configuration Enable Pin
the data sink 1 receive interruption port C429A_RDY1 of the 1st group of transmission circuit by electrical level matching circuit and the described register circuit of being realized by CPLD chip programming (3), the data sink 2 receive interruption port C429A_RDY2 of the 1st group of transmission circuit, high/low 16 of the reception data of the 1st group of transmission circuit read selecting side C429A_SEL, the data sink 1 Enable Pin C429A_EN1 of the 1st group of transmission circuit, the data sink 2 Enable Pin C429A_EN2 of the 1st group of transmission circuit, low 16 of the transmission data of the 1st group of transmission circuit write selecting side C429A_PL1, high 16 of the transmission data of the 1st group of transmission circuit write selecting side C429A_PL2, the data of the 1st group of transmission circuit send state end C429A_TX/R, the data of the 1st group of transmission circuit send Enable Pin C429A_ENTX, the corresponding connection of chip configuration Enable Pin C429A_CWSTR of the 1st group of transmission circuit, the 2nd group of transmission circuit
sEL,
tX/R, ENTX,
end is by the data sink 1 receive interruption port C429B_RDY1 of the 2nd group of transmission circuit of electrical level matching circuit and the described register circuit of being realized by CPLD chip programming (3), the data sink 2 receive interruption port C429B_RDY2 of the 2nd group of transmission circuit, high/low 16 of the reception data of the 2nd group of transmission circuit read selection C429B_SEL, the data sink 1 Enable Pin C429B_EN1 of the 2nd group of transmission circuit, the data sink 2 Enable Pin C429B_EN2 of the 2nd group of transmission circuit, low 16 of the transmission data of the 2nd group of transmission circuit write selecting side C429B_PL1, high 16 of the transmission data of the 2nd group of transmission circuit write selecting side C429B_PL2, the data of the 2nd group of transmission circuit send state end C429B_TX/R, the data of the 2nd group of transmission circuit send Enable Pin C429B_ENTX, the corresponding connection of chip configuration Enable Pin C429B_CWSTR of the 2nd group of transmission circuit, the 3rd group of transmission circuit
sEL,
tX/R, ENTX,
end is by the data sink 1 receive interruption port C429C_RDY1 of the 3rd group of transmission circuit of electrical level matching circuit and the described register circuit of being realized by CPLD chip programming (3), the data sink 2 receive interruption port C429C_RDY2 of the 3rd group of transmission circuit, high/low 16 of the reception data of the 3rd group of transmission circuit read selecting side C429C_SEL, the data sink 1 Enable Pin C429C_EN1 of the 3rd group of transmission circuit, the data sink 2 Enable Pin C429C_EN2 of the 3rd group of transmission circuit, low 16 of the transmission data of the 3rd group of transmission circuit write selecting side C429C_PL1, high 16 of the transmission data of the 3rd group of transmission circuit write selecting side C429C_PL2, the data of the 3rd group of transmission circuit send state end C429C_TX/R, the data of the 3rd group of transmission circuit send Enable Pin C429C_ENTX, the corresponding connection of chip configuration Enable Pin C429C_CWSTR of the 3rd group of transmission circuit, the 4th group of transmission circuit
sEL,
tX/R, ENTX,
end is by the data sink 1 receive interruption port C429D_RDY1 of the 4th group of transmission circuit of electrical level matching circuit and the described register circuit of being realized by CPLD chip programming (3), the data sink 2 receive interruption port C429D_RDY2 of the 4th group of transmission circuit, high/low 16 of the reception data of the 4th group of transmission circuit read selecting side C429D_SEL, the data sink 1 Enable Pin C429D_EN1 of the 4th group of transmission circuit, the data sink 2 Enable Pin C429D_EN2 of the 4th group of transmission circuit, low 16 of the transmission data of the 4th group of transmission circuit write selecting side C429D_PL1, high 16 of the transmission data of the 4th group of transmission circuit write selecting side C429D_PL2, the data of the 4th group of transmission circuit send state end C429D_TX/R, the data of the 4th group of transmission circuit send Enable Pin C429D_ENTX, the corresponding connection of chip configuration Enable Pin C429D_CWSTR of the 4th group of transmission circuit.
2. a kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation according to claim 1, is characterized in that: the chip that described DSP circuit (1) adopts is TMS320F28335.
3. a kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation according to claim 1, is characterized in that: the chip that the register circuit (3) that described CPLD chip programming is realized adopts is EPM570.
4. a kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation according to claim 1, is characterized in that: the chip that described ARINC429 bus transceiving chip circuit (2) adopts is HS3282 and HS3182.
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| CN201420136421.2U CN203746067U (en) | 2014-03-25 | 2014-03-25 | Multi-path ARINC 429 data receiving and transmitting circuit structure based on DSP and CPLD development |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103823785A (en) * | 2014-03-25 | 2014-05-28 | 北京航空航天大学 | Multi-way ARINC429 data transmit-receive circuit structure based on development of DSP and CPLD |
| CN104990550A (en) * | 2015-07-29 | 2015-10-21 | 北京航空航天大学 | Three-unit rotation-modulation redundant strapdown inertial navigation system |
| CN105959194A (en) * | 2016-06-16 | 2016-09-21 | 成都易云知科技有限公司 | DSP-based electronic communication system |
| CN115550098A (en) * | 2022-09-16 | 2022-12-30 | 哈尔滨工业大学 | ARINC429 bus communication assembly and device based on MiniVPX framework |
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2014
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103823785A (en) * | 2014-03-25 | 2014-05-28 | 北京航空航天大学 | Multi-way ARINC429 data transmit-receive circuit structure based on development of DSP and CPLD |
| CN103823785B (en) * | 2014-03-25 | 2017-01-11 | 北京航空航天大学 | Multi-way ARINC429 data transmit-receive circuit structure based on development of DSP and CPLD |
| CN104990550A (en) * | 2015-07-29 | 2015-10-21 | 北京航空航天大学 | Three-unit rotation-modulation redundant strapdown inertial navigation system |
| CN105959194A (en) * | 2016-06-16 | 2016-09-21 | 成都易云知科技有限公司 | DSP-based electronic communication system |
| CN115550098A (en) * | 2022-09-16 | 2022-12-30 | 哈尔滨工业大学 | ARINC429 bus communication assembly and device based on MiniVPX framework |
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