CN202143046U - Complementary metal oxide semiconductor (CMOS) digital logic gate circuit structure capable of resisting negative bias temperature instability (NBTI) effect - Google Patents
Complementary metal oxide semiconductor (CMOS) digital logic gate circuit structure capable of resisting negative bias temperature instability (NBTI) effect Download PDFInfo
- Publication number
- CN202143046U CN202143046U CN201120267408U CN201120267408U CN202143046U CN 202143046 U CN202143046 U CN 202143046U CN 201120267408 U CN201120267408 U CN 201120267408U CN 201120267408 U CN201120267408 U CN 201120267408U CN 202143046 U CN202143046 U CN 202143046U
- Authority
- CN
- China
- Prior art keywords
- pipe
- nbti
- effect
- digital logic
- logic gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The utility model discloses a complementary metal oxide semiconductor (CMOS) digital logic gate circuit structure capable of resisting a negative bias temperature instability (NBTI) effect, namely a branch circuit formed by a source follower N-channel metal oxide semi-conductor (NMOS) pipe and a current source load NMOS pipe is led in between an input node in an original CMOS digital logic gate circuit and a grid electrode of a P-channel metal oxide semi-conductor (PMOS) pipe. A drain electrode of the source follower NMOS pipe is connected with a power supply, a grid electrode of the source follower NMOS pipe is connected with the input node in the logic gate circuit, and a source electrode of the source follower NMOS pipe is connected with the grid electrode of the PMOS pipe. A source electrode of the current source load NMOS pipe is connected with the ground, a grid electrode of the current source load NMOS pipe is connected with the power supply, and the drain electrode of the current source load NMOS pipe is connected with the grid electrode of the PMOS pipe. Under the effect of the source follower, minus gate voltage of a PMOS device is reduced, the NBTI effect is weakened, and accordingly drifting volume of threshold voltage of the PMOS device and circuit delay of the logic gate circuit are reduced. By means of the CMOS digital logic gate circuit structure, under the condition that normal logic functions are obtained, influence of the NBTI effect is the smallest, and accordingly NBTI effect resisting capacity of a CMOS digital integration circuit is improved.
Description
Technical field
The utility model relates to the CMOS technical field of integrated circuits, is specifically related to the cmos digital logic gates structure of anti-NBTI effect.
Background technology
Develop rapidly along with the CMOS IC industry; To circuit reliability require increasingly high; It is one of main direction of present IC industry development that characteristic size continues to dwindle; Yet the meeting that reduces of size causes effects that some degenerate the device performance generation; Wherein Negative Bias Temperature Instability (NBTI:Negative Bias Temperature Instability) has become the key factor that influences the deep-submicron CMOS IC reliability at present; The mechanism of NBTI effect can use reaction-diffusion model (R-D Model) to explain; The hole of PMOSFET device inversion layer under the high temperature minus gate voltage receives thermal excitation; Satisfy through silicon/silicon dioxide (
) interface; Owing to have a large amount of Si-H keys at
interface; The hole of thermal excitation and the effect of Si-H key generate the H atom; Thereby stay dangling bonds at
interface; And because the unsteadiness of H atom; Two H atoms will combine; Form with hydrogen molecule discharges; Away from
interface to
/Poly interfacial diffusion, thereby cause the negative sense drift of threshold voltage.
After having experienced more deep device level NBTI failure mechanism and process modification research, circuit stages NBTI Study on Effect and on the basis of considering the NBTI effect, carry out the new research focus of circuit reliability design having become.Though people have proposed much to weaken the way of circuit stages NBTI effect; As regulate supply voltage, change the input vector, grid size adjusting of digital integrated circuit etc.; But has the circuit of particular requirement for some; Supply voltage and input vector all need be taked the value of fixing, and possibly cause other degradation effect and regulate grid size, so all there is certain limitation in these methods.
The utility model content
When under the high temperature PMOS device being applied minus gate voltage; The NBTI effect will occur, and that is to say, temperature and minus gate voltage are for forming the most important component of NBT stress; But the temperature during owing to circuit working is difficult to adjustment, so minus gate voltage has just become to influence the principal element of NBTI effect.The utility model proposes a kind of cmos digital gate (inverter, NAND gate, NOR gate) circuit structure of anti-NBTI effect from reducing the gate source voltage of PMOS.
The cmos digital logic gates structure of anti-NBTI effect; Specifically be to be provided with by a source follower NMOS pipe between the grid of input node and the PMOS pipe in former cmos digital logic gates to manage the branch road that forms with a current source load NMOS; Wherein the drain electrode of source follower NMOS pipe links to each other with power supply; Grid connects and imports node in the logic gates, and source electrode links to each other with the grid of said PMOS pipe; Current source load NMOS manages source ground, and grid links to each other with power supply, and drain electrode links to each other with the grid of said PMOS pipe.
In the cmos digital logic gates structure of above-mentioned anti-NBTI effect, said former cmos digital logic gates can be in the inverter simplified most, NAND gate, the OR-NOT circuit any.
Compared with prior art; The utlity model has following advantage and technique effect: in the cmos digital logic gates structure of the anti-NBTI effect of the utility model; After adding input signal, the gate source voltage of PMOS pipe will reduce, and promptly reduce minus gate voltage; Therefore reduce the threshold voltage shift amount of PMOS pipe after standing NBT stress, thereby reduced the increment of circuit delay.
The HSPICE simulation result is found; The NBTI ruggedized construction of carrying has not only improved gate and has not received the preceding service behaviour of NBT stress; Circuit delay reduces, and makes logic gates reduced significantly by the circuit delay increment behind the NBT stress, and cmos logic gate circuit (inverter NAND gate, NOR gate) is being realized under the normal logic function; The influence that receives the NBTI effect is minimum, thereby improves the ability of the anti-NBTI effect of cmos digital integrated circuit.
Description of drawings
Inverter circuit after Fig. 1 a and Fig. 1 b are respectively common inverter and reinforce.
Fig. 2 be common NAND gate with reinforce after NAND gate circuit.
Fig. 3 be common NOR gate with reinforce after OR-NOT circuit.
Fig. 4 a and Fig. 4 b are the HSPICE emulation input and output oscillogram of corresponding diagram 1a and Fig. 1 b circuit.
Fig. 5 a and Fig. 5 b are the HSPICE emulation input and output oscillogram of corresponding diagram 2a and Fig. 2 b circuit.
Fig. 6 a and Fig. 6 b are the HSPICE emulation input and output oscillogram of corresponding diagram 3a and Fig. 3 b circuit.
Embodiment
Below in conjunction with accompanying drawing and embodiment the practical implementation of the utility model is described further, but enforcement of the utility model and protection range are not limited thereto.
For not using the plain inverter circuit of the utility model, Fig. 1 b is the utility model inverter embodiment circuit like Fig. 1 a.In Fig. 1 b present embodiment, input signal Vin connects the grid of the second metal-oxide-semiconductor M2 and the grid of source follower the 4th metal-oxide-semiconductor M4 simultaneously; The source output terminal of the 4th metal-oxide-semiconductor M4 connects the grid of the first metal-oxide-semiconductor M1; The 6th metal-oxide-semiconductor M6 grid links to each other with VCC, and the source electrode of the 4th metal-oxide-semiconductor M4 is received in drain electrode, and source ground is promptly as current source load; The drain electrode of the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 links to each other and is connected to output Vout.When Vin is high level, make the second metal-oxide-semiconductor M2 conducting, output signal Vout output low level; When Vin is low level, the M1 conducting, output signal Vout is a high level.The 4th metal-oxide-semiconductor M4 and the 6th metal-oxide-semiconductor M6 undercut the gate source voltage of the first metal-oxide-semiconductor M1, weaken the NBTI effect.
Fig. 2 a is not for using the common NAND gate circuit of the utility model, and Fig. 2 b is the utility model NAND gate embodiment circuit, and input signal links to each other with the grid of source with device the 12 metal-oxide-semiconductor M12 with the grid of the tenth metal-oxide-semiconductor M10 simultaneously; The source output terminal of the 12 metal-oxide-semiconductor M12 connects the drain electrode of grid and current source load the 14 metal-oxide-semiconductor M14 of the 8th metal-oxide-semiconductor M8 simultaneously; The 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8 are the last pull-up network of NAND gate; The 9th metal-oxide-semiconductor M9 and the tenth metal-oxide-semiconductor M10 are pulldown network; At the grid input high level of the 7th metal-oxide-semiconductor M7 and the 9th metal-oxide-semiconductor M9, make the function of NAND gate realization inverter, promptly when input signal Vin is high level; The 9th metal-oxide-semiconductor M9 and the tenth all conductings of metal-oxide-semiconductor M10 are output as low level; When input signal Vin was low level, the 8th metal-oxide-semiconductor M8 conducting was output as high level.The 12 metal-oxide-semiconductor M12 and the 14 metal-oxide-semiconductor M14 drag down the gate source voltage of the 8th metal-oxide-semiconductor M8, weaken the NBTI effect.
Fig. 3 a is not for using the common OR-NOT circuit of the utility model; Fig. 3 b is the utility model NOR gate embodiment circuit; Same quadrat method; The 20 metal-oxide-semiconductor M20 and the 22 metal-oxide-semiconductor M22 are connected between the 15 metal-oxide-semiconductor M15 grid and the input node with device and current source load as the source respectively, and the 15 metal-oxide-semiconductor M15 and the 16 metal-oxide-semiconductor M16 are the last pull-up network of NOR gate, and the 17 metal-oxide-semiconductor M17 and the 18 metal-oxide-semiconductor M18 are pulldown network.At the grid input low level of the 16 metal-oxide-semiconductor M16 and the 17 metal-oxide-semiconductor M17, make NOR gate realize the function of inverter, promptly when input signal Vin was high level, the 18 metal-oxide-semiconductor M18 conducting was output as low level; When input signal Vin was low level, the 15 metal-oxide-semiconductor M15 and the 16 metal-oxide-semiconductor M16 conducting were output as high level.Equally, the 20 metal-oxide-semiconductor M20 and the 22 metal-oxide-semiconductor M22 drag down the gate source voltage of the 15 metal-oxide-semiconductor M15, weaken the NBTI effect.
Utilize HSPICE that the emulation that the circuit among Fig. 1, Fig. 2 and Fig. 3 applies NBT stress front and back (is adopted the component library of 0.18mm CMOS; Temperature is 125 ℃); Utilize Avanwaves to check the input and output waveform; Shown in Fig. 4 a, Fig. 4 b, Fig. 5 a, Fig. 5 b and Fig. 6 a, Fig. 6 b, the circuit after finding to reinforce can normally be realized function in the scope that error allows; Check .LIS file logging circuit delay, as shown in table 1, the gate source voltage of reinforcing back PMOS pipe is reduced to 0.92V by 1.8V; Thereby make the threshold voltage shift amount be reduced to 0.307mV from 20mV, therefore, than common logic gates; The delay of the logic gates after the reinforcing has had certain decrease than circuit common; And reduced 2 to 3 one magnitude at the increment that receives to postpone under the NBTI effects, that is, the anti-NBTI effect performance of circuit is enhanced after reinforcing.
The comparison of logic gates performance before and after table 1. is reinforced
Claims (2)
1. the cmos digital logic gates structure of anti-NBTI effect; Comprise former cmos digital logic gates; It is characterized in that being provided with by a source follower NMOS pipe between the grid of input node and the PMOS pipe in former cmos digital logic gates and manage the branch road that forms with a current source load NMOS; Wherein the drain electrode of source follower NMOS pipe links to each other with power supply, and grid connects and imports node in the logic gates, and source electrode links to each other with the grid of said PMOS pipe; Current source load NMOS manages source ground, and grid links to each other with power supply, and drain electrode links to each other with the grid of said PMOS pipe.
2. the cmos digital logic gates structure of anti-NBTI effect according to claim 1 is characterized in that said former cmos digital logic gates is in the inverter simplified most, NAND gate, the OR-NOT circuit any.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120267408U CN202143046U (en) | 2011-07-26 | 2011-07-26 | Complementary metal oxide semiconductor (CMOS) digital logic gate circuit structure capable of resisting negative bias temperature instability (NBTI) effect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120267408U CN202143046U (en) | 2011-07-26 | 2011-07-26 | Complementary metal oxide semiconductor (CMOS) digital logic gate circuit structure capable of resisting negative bias temperature instability (NBTI) effect |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202143046U true CN202143046U (en) | 2012-02-08 |
Family
ID=45554081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201120267408U Expired - Fee Related CN202143046U (en) | 2011-07-26 | 2011-07-26 | Complementary metal oxide semiconductor (CMOS) digital logic gate circuit structure capable of resisting negative bias temperature instability (NBTI) effect |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202143046U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016109994A1 (en) * | 2015-01-09 | 2016-07-14 | 深圳市华星光电技术有限公司 | Scan driving circuit and nand gate logic operation circuit thereof |
| CN109219926A (en) * | 2016-05-23 | 2019-01-15 | 高通股份有限公司 | Low power receiver with wide input voltage range |
-
2011
- 2011-07-26 CN CN201120267408U patent/CN202143046U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016109994A1 (en) * | 2015-01-09 | 2016-07-14 | 深圳市华星光电技术有限公司 | Scan driving circuit and nand gate logic operation circuit thereof |
| GB2549862A (en) * | 2015-01-09 | 2017-11-01 | Shenzhen China Star Optoelect | Scan driving circuit and nand gate logic operation circuit therof |
| GB2549862B (en) * | 2015-01-09 | 2021-07-14 | Shenzhen China Star Optoelect | Scan driving circuit and nand logic operation circuit therof |
| CN109219926A (en) * | 2016-05-23 | 2019-01-15 | 高通股份有限公司 | Low power receiver with wide input voltage range |
| CN109219926B (en) * | 2016-05-23 | 2022-04-12 | 高通股份有限公司 | Low power receiver with wide input voltage range |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102332907A (en) | Anti-NBTI (Negative-Bias Temperature Instability) effect reinforcing method based on CMOS (Complementary Metal-Oxide-Semiconductor Transistor) digital logic gate circuit | |
| US6794902B2 (en) | Virtual ground circuit | |
| CN202143046U (en) | Complementary metal oxide semiconductor (CMOS) digital logic gate circuit structure capable of resisting negative bias temperature instability (NBTI) effect | |
| Venkatesan et al. | Analysis of 1-bit full adder using different techniques in Cadence 45nm Technology | |
| CN109884873B (en) | Time-to-digital converter adopting dynamic threshold technology | |
| Manikkule et al. | Encapsulation of Full Adder Using 180nm CNTFET | |
| Lin et al. | An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimes | |
| Min et al. | Leakage-suppressed clock-gating circuit with zigzag super cut-off cmos (zsccmos) for leakage-dominant sub-70-nm and sub-1-vv/sub dd/lsis | |
| CN105827232A (en) | Recovery circuit for improving negative bias temperature instability (NBTI) of SSLC level conversion circuit | |
| Kong et al. | Charge recycling differential logic for low-power application | |
| KR101622827B1 (en) | Logig gate using schmitt trigger circuit | |
| Shah et al. | PVT variations aware low leakage DOIND approach for nanoscale domino logic circuits | |
| Berg et al. | Ultra low-voltage and high speed dynamic and static cmos precharge logic | |
| CN202435358U (en) | D flip-flop based on hybrid single electron transistor(SET)/metal oxide semiconductor (MOS) structure | |
| Eratne et al. | Leakage control in full adders with selectively stacked inverters | |
| US8994415B1 (en) | Multiple VDD clock buffer | |
| Shah et al. | Comparative study of Area, Delay and Power Dissipation for LECTOR and INDEP (Leakage control techniques) at 70 nm technology node | |
| CN102611429A (en) | Summing device of SET/MOS (Single Electron Transistor/Metal Oxide Semiconductor) mixed structure based on threshold logic | |
| Kulshethra et al. | Design of Low Leakage Arithmetic Logic circuit Using Efficient Power Gating Schemes | |
| CN202435386U (en) | SET/MOS (Single Electron Transistor/Metal Oxide Semiconductor) hybrid structure-based 8-3 encoder | |
| Verma et al. | Implementation and Analysis of Efficient Low Power Dynamic Circuit Technique | |
| Vijayakumar et al. | Area and power efficient hybrid PTCSL MUX design | |
| Guduri et al. | Novel Pass-transistor Logic based Ultralow Power Variation Resilient CMOS Full Adder | |
| Lee et al. | Design of a Low-Power 8 x 8-Bit Parallel Multiplier Using MOS Current Mode Logic Circuit | |
| Adwani et al. | Analysis of Power Dissipation & Low Power VLSI Chip Design |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120208 Termination date: 20140726 |
|
| EXPY | Termination of patent right or utility model |