CN102332907A - Anti-NBTI (Negative-Bias Temperature Instability) effect reinforcing method based on CMOS (Complementary Metal-Oxide-Semiconductor Transistor) digital logic gate circuit - Google Patents
Anti-NBTI (Negative-Bias Temperature Instability) effect reinforcing method based on CMOS (Complementary Metal-Oxide-Semiconductor Transistor) digital logic gate circuit Download PDFInfo
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Abstract
The invention discloses an anti-NBTI (Negative-Bias Temperature Instability) effect reinforcing method based on a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) digital logic gate circuit, which comprises the step of introducing a branch consisting of a source follower NMOS (N-channel Metal Oxide Semiconductor) transistor and a current source load NMOS transistor between an input node of the original CMOS digital logic gate circuit and a grid electrode of a PMOS (P-channel Metal Oxide Semiconductor) transistor, wherein the drain electrode of the source follower NMOS transistor is connected with a power supply, the grid electrode of the source follower NMOS transistor is connected with the input node of the logic gate circuit, the source electrode of the source follower NMOS transistor is connected with the grid electrode of the PMOS transistor; and the source electrode of the current source load NMOS transistor is grounded, the grid electrode of the current source load NMOS transistor is connected with the power supply, and the drain electrode of the current source load NMOS transistor is connected with the grid electrode of the PMOS transistor. Under the action of a source follower, the negative grid voltage of the PMOS transistor is reduced, the NBTI effect is weakened, and the drifting amount of the threshold voltage of the PMOS transistor and the circuit delay of the logic gate circuit are reduced. By using the anti-NBTI effect reinforcing method based on the CMOS digital logic gate circuit, the influence of the NBTI effect is minimized under a normal logic function, therefore, the anti-NBTI effect capacity of the CMOS digital integrated circuit is improved.
Description
Technical field
The present invention relates to the CMOS technical field of integrated circuits, be specifically related to anti-NBTI effect reinforcement means based on cmos digital gate (inverter, NAND gate, NOR gate) circuit.
Background technology
Develop rapidly along with the CMOS IC industry; To circuit reliability require increasingly high; It is one of main direction of present IC industry development that characteristic size continues to dwindle; Yet the meeting that reduces of size causes effects that some degenerate the device performance generation; Wherein Negative Bias Temperature Instability (NBTI:Negative Bias Temperature Instability) has become the key factor that influences the deep-submicron CMOS IC reliability at present; The mechanism of NBTI effect can use reaction-diffusion model (R-D Model) to explain; The hole of PMOSFET device inversion layer under the high temperature minus gate voltage receives thermal excitation; Satisfy through silicon/silicon dioxide (
) interface; Owing to have a large amount of Si-H keys at
interface; The hole of thermal excitation and the effect of Si-H key generate the H atom; Thereby stay dangling bonds at
interface; And because the unsteadiness of H atom; Two H atoms will combine; Form with hydrogen molecule discharges; Away from
interface to
/Poly interfacial diffusion, thereby cause the negative sense drift of threshold voltage.
After having experienced more deep device level NBTI failure mechanism and process modification research, circuit stages NBTI Study on Effect and on the basis of considering the NBTI effect, carry out the new research focus of circuit reliability design having become.Though people have proposed much to weaken the way of circuit stages NBTI effect; As regulate supply voltage, change the input vector, grid size adjusting of digital integrated circuit etc.; But has the circuit of particular requirement for some; Supply voltage and input vector all need be taked the value of fixing, and possibly cause other degradation effect and regulate grid size, so all there is certain limitation in these methods.
Summary of the invention
When under the high temperature PMOS device being applied minus gate voltage; The NBTI effect will occur, and that is to say, temperature and minus gate voltage are for forming the most important component of NBT stress; But the temperature during owing to circuit working is difficult to adjustment, so minus gate voltage has just become to influence the principal element of NBTI effect.The present invention proposes the anti-NBTI effect reinforcement means based on cmos digital gate (inverter, NAND gate, NOR gate) circuit from reducing the gate source voltage of PMOS.
Anti-NBTI effect reinforcement means based on the cmos digital logic gates; Specifically be to introduce by a source follower NMOS pipe between the grid of input node and the PMOS pipe in former cmos digital logic gates to manage the branch road that forms with a current source load NMOS; Wherein the drain electrode of source follower NMOS pipe links to each other with power supply; Grid connects and imports node in the logic gates, and source electrode links to each other with the grid of said PMOS pipe; Current source load NMOS manages source ground, and grid links to each other with power supply, and drain electrode links to each other with the grid of said PMOS pipe.
In the above-mentioned anti-NBTI effect reinforcement means based on the cmos digital logic gates, said former cmos digital logic gates can be in the inverter simplified most, NAND gate, the OR-NOT circuit any.
Compared with prior art; The present invention has following advantage and technique effect: in the cmos digital logic gates structure of anti-NBTI effect of the present invention; After adding input signal, the gate source voltage of PMOS pipe will reduce, and promptly reduce minus gate voltage; Therefore reduce the threshold voltage shift amount of PMOS pipe after standing NBT stress, thereby reduced the increment of circuit delay.
The HSPICE simulation result is found; The NBTI ruggedized construction of carrying has not only improved gate and has not received the preceding service behaviour of NBT stress; Circuit delay reduces, and makes logic gates reduced significantly by the circuit delay increment behind the NBT stress, and cmos logic gate circuit (inverter NAND gate, NOR gate) is being realized under the normal logic function; The influence that receives the NBTI effect is minimum, thereby improves the ability of the anti-NBTI effect of cmos digital integrated circuit.
Description of drawings
Inverter circuit after Fig. 1 a and Fig. 1 b are respectively common inverter and reinforce.
Fig. 2 be common NAND gate with reinforce after NAND gate circuit.
Fig. 3 be common NOR gate with reinforce after OR-NOT circuit.
Fig. 4 a and Fig. 4 b are the HSPICE emulation input and output oscillogram of corresponding diagram 1a and Fig. 1 b circuit.
Fig. 5 a and Fig. 5 b are the HSPICE emulation input and output oscillogram of corresponding diagram 2a and Fig. 2 b circuit.
Fig. 6 a and Fig. 6 b are the HSPICE emulation input and output oscillogram of corresponding diagram 3a and Fig. 3 b circuit.
Embodiment
Below in conjunction with accompanying drawing and embodiment practical implementation of the present invention is described further, but enforcement of the present invention and protection range are not limited thereto.
For not using plain inverter circuit of the present invention, Fig. 1 b is an inverter embodiment circuit of the present invention like Fig. 1 a.In Fig. 1 b present embodiment, input signal Vin connects the grid of the second metal-oxide-semiconductor M2 and the grid of source follower the 4th metal-oxide-semiconductor M4 simultaneously; The source output terminal of the 4th metal-oxide-semiconductor M4 connects the grid of the first metal-oxide-semiconductor M1; The 6th metal-oxide-semiconductor M6 grid links to each other with VCC, and the source electrode of the 4th metal-oxide-semiconductor M4 is received in drain electrode, and source ground is promptly as current source load; The drain electrode of the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 links to each other and is connected to output Vout.When Vin is high level, make the second metal-oxide-semiconductor M2 conducting, output signal Vout output low level; When Vin is low level, the M1 conducting, output signal Vout is a high level.The 4th metal-oxide-semiconductor M4 and the 6th metal-oxide-semiconductor M6 undercut the gate source voltage of the first metal-oxide-semiconductor M1, weaken the NBTI effect.
Fig. 2 a is not for using common NAND gate circuit of the present invention, and Fig. 2 b is a NAND gate embodiment circuit of the present invention, and input signal links to each other with the grid of source with device the 12 metal-oxide-semiconductor M12 with the grid of the tenth metal-oxide-semiconductor M10 simultaneously; The source output terminal of the 12 metal-oxide-semiconductor M12 connects the drain electrode of grid and current source load the 14 metal-oxide-semiconductor M14 of the 8th metal-oxide-semiconductor M8 simultaneously; The 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8 are the last pull-up network of NAND gate; The 9th metal-oxide-semiconductor M9 and the tenth metal-oxide-semiconductor M10 are pulldown network; At the grid input high level of the 7th metal-oxide-semiconductor M7 and the 9th metal-oxide-semiconductor M9, make the function of NAND gate realization inverter, promptly when input signal Vin is high level; The 9th metal-oxide-semiconductor M9 and the tenth all conductings of metal-oxide-semiconductor M10 are output as low level; When input signal Vin was low level, the 8th metal-oxide-semiconductor M8 conducting was output as high level.The 12 metal-oxide-semiconductor M12 and the 14 metal-oxide-semiconductor M14 drag down the gate source voltage of the 8th metal-oxide-semiconductor M8, weaken the NBTI effect.
Fig. 3 a is not for using common OR-NOT circuit of the present invention; Fig. 3 b is a NOR gate embodiment circuit of the present invention; Same quadrat method; The 20 metal-oxide-semiconductor M20 and the 22 metal-oxide-semiconductor M22 are connected between the 15 metal-oxide-semiconductor M15 grid and the input node with device and current source load as the source respectively, and the 15 metal-oxide-semiconductor M15 and the 16 metal-oxide-semiconductor M16 are the last pull-up network of NOR gate, and the 17 metal-oxide-semiconductor M17 and the 18 metal-oxide-semiconductor M18 are pulldown network.At the grid input low level of the 16 metal-oxide-semiconductor M16 and the 17 metal-oxide-semiconductor M17, make NOR gate realize the function of inverter, promptly when input signal Vin was high level, the 18 metal-oxide-semiconductor M18 conducting was output as low level; When input signal Vin was low level, the 15 metal-oxide-semiconductor M15 and the 16 metal-oxide-semiconductor M16 conducting were output as high level.Equally, the 20 metal-oxide-semiconductor M20 and the 22 metal-oxide-semiconductor M22 drag down the gate source voltage of the 15 metal-oxide-semiconductor M15, weaken the NBTI effect.
Utilize HSPICE that the emulation that the circuit among Fig. 1, Fig. 2 and Fig. 3 applies NBT stress front and back (is adopted the component library of 0.18mm CMOS; Temperature is 125 ℃); Utilize Avanwaves to check the input and output waveform; Shown in Fig. 4 a, Fig. 4 b, Fig. 5 a, Fig. 5 b and Fig. 6 a, Fig. 6 b, the circuit after finding to reinforce can normally be realized function in the scope that error allows; Check .LIS file logging circuit delay, as shown in table 1, the gate source voltage of reinforcing back PMOS pipe is reduced to 0.92V by 1.8V; Thereby make the threshold voltage shift amount be reduced to 0.307mV from 20mV, therefore, than common logic gates; The delay of the logic gates after the reinforcing has had certain decrease than circuit common; And reduced 2 to 3 one magnitude at the increment that receives to postpone under the NBTI effects, that is, the anti-NBTI effect performance of circuit is enhanced after reinforcing.
The comparison of logic gates performance before and after table 1. is reinforced
Claims (2)
1. based on the anti-NBTI effect reinforcement means of cmos digital logic gates; It is characterized in that introducing by a source follower NMOS pipe between the grid of input node and the PMOS pipe in former cmos digital logic gates and manage the branch road that forms with a current source load NMOS; Wherein the drain electrode of source follower NMOS pipe links to each other with power supply; Grid connects and imports node in the logic gates, and source electrode links to each other with the grid of said PMOS pipe; Current source load NMOS manages source ground, and grid links to each other with power supply, and drain electrode links to each other with the grid of said PMOS pipe.
2. the anti-NBTI effect reinforcement means based on the cmos digital logic gates according to claim 1 is characterized in that said former cmos digital logic gates is in the inverter simplified most, NAND gate, the OR-NOT circuit any.
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| CN201110211195A CN102332907A (en) | 2011-07-26 | 2011-07-26 | Anti-NBTI (Negative-Bias Temperature Instability) effect reinforcing method based on CMOS (Complementary Metal-Oxide-Semiconductor Transistor) digital logic gate circuit |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103424684A (en) * | 2012-05-24 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | Bias voltage temperature instability detection circuit and detection method |
| CN104333355A (en) * | 2014-11-14 | 2015-02-04 | 浙江工商大学 | QC-BC01 circuit module for clock transformation |
| CN104485943A (en) * | 2014-11-14 | 2015-04-01 | 浙江工商大学 | CMOS (Complementary Metal-Oxide-Semiconductor) technology-based QC(Quaternary Clock)-BC(Binary Clock)12 circuit |
| CN104575425A (en) * | 2015-01-09 | 2015-04-29 | 深圳市华星光电技术有限公司 | Scanning driving circuit and NAND logic operation circuit thereof |
| CN105827232A (en) * | 2016-03-18 | 2016-08-03 | 苏州芯宽电子科技有限公司 | Recovery circuit for improving negative bias temperature instability (NBTI) of SSLC level conversion circuit |
| CN107039299A (en) * | 2016-11-10 | 2017-08-11 | 中国电子产品可靠性与环境试验研究所 | Metal-oxide-semiconductor parameter degradation circuit and metal-oxide-semiconductor parameter degradation early warning circuit |
| CN108923777A (en) * | 2018-07-02 | 2018-11-30 | 安徽大学 | The inverter module of radiation hardened |
| CN109219926A (en) * | 2016-05-23 | 2019-01-15 | 高通股份有限公司 | Low power receiver with wide input voltage range |
| CN110097900A (en) * | 2018-01-31 | 2019-08-06 | 三星电子株式会社 | IC apparatus and semiconductor device with gating signal transmitter |
| CN113472343A (en) * | 2021-07-14 | 2021-10-01 | 山东大学 | Construction method of logic gate |
-
2011
- 2011-07-26 CN CN201110211195A patent/CN102332907A/en active Pending
Non-Patent Citations (2)
| Title |
|---|
| LIU LINING等: "Design for improved NBTI reliability of CMOS digital IC", 《ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2010 IEEE INTERNATIONAL CONFERENCE OF》 * |
| 尹彬锋等: "NBTI的研究进展和改善途径", 《中国集成电路》 * |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103424684B (en) * | 2012-05-24 | 2015-12-09 | 中芯国际集成电路制造(上海)有限公司 | The instable testing circuit of Bias Temperature and detection method |
| CN103424684A (en) * | 2012-05-24 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | Bias voltage temperature instability detection circuit and detection method |
| CN104333355B (en) * | 2014-11-14 | 2017-12-08 | 浙江工商大学 | QC BC01 circuit modules for clock conversion |
| CN104333355A (en) * | 2014-11-14 | 2015-02-04 | 浙江工商大学 | QC-BC01 circuit module for clock transformation |
| CN104485943A (en) * | 2014-11-14 | 2015-04-01 | 浙江工商大学 | CMOS (Complementary Metal-Oxide-Semiconductor) technology-based QC(Quaternary Clock)-BC(Binary Clock)12 circuit |
| CN104575425A (en) * | 2015-01-09 | 2015-04-29 | 深圳市华星光电技术有限公司 | Scanning driving circuit and NAND logic operation circuit thereof |
| CN105827232B (en) * | 2016-03-18 | 2019-01-15 | 苏州芯宽电子科技有限公司 | A kind of restoring circuit improving SSLC level shifting circuit Negative Bias Temperature Instability |
| CN105827232A (en) * | 2016-03-18 | 2016-08-03 | 苏州芯宽电子科技有限公司 | Recovery circuit for improving negative bias temperature instability (NBTI) of SSLC level conversion circuit |
| CN109219926A (en) * | 2016-05-23 | 2019-01-15 | 高通股份有限公司 | Low power receiver with wide input voltage range |
| CN109219926B (en) * | 2016-05-23 | 2022-04-12 | 高通股份有限公司 | Low power receiver with wide input voltage range |
| CN107039299A (en) * | 2016-11-10 | 2017-08-11 | 中国电子产品可靠性与环境试验研究所 | Metal-oxide-semiconductor parameter degradation circuit and metal-oxide-semiconductor parameter degradation early warning circuit |
| CN107039299B (en) * | 2016-11-10 | 2019-10-18 | 中国电子产品可靠性与环境试验研究所 | Metal-oxide-semiconductor parameter degradation circuit and metal-oxide-semiconductor parameter degradation early warning circuit |
| CN110097900A (en) * | 2018-01-31 | 2019-08-06 | 三星电子株式会社 | IC apparatus and semiconductor device with gating signal transmitter |
| CN108923777A (en) * | 2018-07-02 | 2018-11-30 | 安徽大学 | The inverter module of radiation hardened |
| CN113472343A (en) * | 2021-07-14 | 2021-10-01 | 山东大学 | Construction method of logic gate |
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Application publication date: 20120125 |