CN201657185U - Device for synthetizing multichannel high-definition video image picture - Google Patents
Device for synthetizing multichannel high-definition video image picture Download PDFInfo
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- CN201657185U CN201657185U CN2010201297845U CN201020129784U CN201657185U CN 201657185 U CN201657185 U CN 201657185U CN 2010201297845 U CN2010201297845 U CN 2010201297845U CN 201020129784 U CN201020129784 U CN 201020129784U CN 201657185 U CN201657185 U CN 201657185U
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Abstract
The utility model relates to a device for synthetizing a multichannel high-definition video image picture, which adopts the design of a mode of inserting a card and comprises N video input synchronous cards and an image controller. The N video input synchronous cards select to receive N channels of real-time video signals and respectively output image data to the image controller by the tristate logic. All the video input synchronous cards output the image data by one group of common horizontal and vertical synchronous singles and image pixel clock signals. Each video input synchronous card can respectively set the position and the size of an output image and generates effective image data control signals Hor-DE-SPn and Ver-DE-SPn corresponding to an output picture of the video input synchronous card. The image controller increases one grade of tristate latch or in-phase and reversed-phase buffer driving circuit at intervals of p slots and simultaneously generates a high-impedance state enable control single corresponding to each grade of tristate latch or in-phase and reversed-phase buffer driving circuit and a control single corresponding to each video input synchronous card to switch to gate the image data output by each video input synchronous card so as to realize the function of synthetizing the picture.
Description
Technical field:
The utility model relates to the electronic engineering video image processing technology, particularly the multi-channel video image frame is synthesized the image processing apparatus of width of cloth video image output.
Technical background:
At present, video image synthesizer or image splitter can be exported by video image synthetic 1 road video image after realtime graphic is handled dissimilar multichannel or form, and this output is connect 1 display device, can demonstrate several real time video images.
Common video image synthesizer can only be imported SD composite video (PAL/NTSC), and still with the output of 1 road composite video, image definition is very low after picture is synthetic for the multichannel composite video.This mode is all adopted in the real-time monitoring in present most scene;
The video image synthesizer that high-resolution such as can importing VGA or DV is also arranged, output also can be digital interfaces such as DVI.Two kinds of designs are arranged usually:
A kind of is to adopt the design of single circuit plate, and the synthetic dedicated video integrated circuit of band picture-in-picture that adopts of video pictures is realized.This mode designs complexity, synthetic divided frame or sprite limited amount, and the picture-in-picture passage video bandwidth of dedicated video integrated circuit is narrow, algorithm is simple, the synthetic image sharpness of influence;
Another kind is to adopt the plug-in card mode to design, and every input card all shows the input of this card in the picture-in-picture mode, and its output connects the next stage input card and as its background frame, many thus card levels are unified into many pictures in one tunnel output picture.This mode video frequency processing chip picture-in-picture passage video bandwidth is narrow, algorithm is simple, and therefore synthetic picture is unintelligible.Simultaneously, first order input video must just be exported through multistep treatment, and delay time is oversize, and visual real-time is very poor;
Summary of the invention:
The purpose of this utility model is, application according to present digital high-definition video (HDMI, HDSDI) is more and more universal, also has computer video images such as common SD composite video (PAL/NTSC), SD/high definition component vide, VGA or DVI etc. simultaneously in a large number; The video image synthesizer of looking for novelty is wanted to insert more eurypalynous video image, and also full HD (1920 * 1080 resolution) real-time video is handled, and proposes a kind of new video image synthesizer thus and satisfies above-mentioned needs.
Another purpose of the present utility model is that the video image synthesizer will realize also that picture tiles, windows, picture complex functionality flexibly such as stack.
The utility model is achieved through the following technical solutions, a kind of device of synthesizing multi-path high-definition video image picture, comprise cabinet, image processing apparatus reaches the power supply for their power supplies, image processing apparatus comprises: (1), be used to switch each video-input image data of gating, a synthetic thus width of cloth output image, the realization picture is synthetic, comprise tiling, window or the Overlay function, according to Hor-DE-SPn, Ver-DE-SPn, Sys-Clk and user's setup parameter User-Defi-Paras come to produce image output enable control signal to video input sync card: IMG-OE-SPn (n=1,2,3 ... N) and the high-impedance state that produces the drive circuit of correspondence image data transmission channel enable control signal IMG-OE-BT m (m=1,2,3 ... M) image control base plate or backboard; (2), be connected, the N of optionally connected receipts N road real time video signals and output image data signal opens video input sync card with image control base plate or backboard signal input part.
The device of described a kind of synthesizing multi-path high-definition video image picture, its described video input sync card is that card insert type is connected with the mode that image control base plate or backboard signal input part are connected.
The device of described a kind of synthesizing multi-path high-definition video image picture, the circuit of its described image control base plate or backboard comprises: be used to control the logic control circuit of entire circuit and the field line synchronization circuit, system clock and the clock drive circuit that are electrically connected with it, respectively with import the corresponding buffering of sync card or latch drive circuit, VGA output circuit and DVI/HDMI output circuit.
The device of described a kind of synthesizing multi-path high-definition video image picture, the circuit of its video input sync card comprises: be used for to image dwindle/video image of processing and amplifying, frame speed conversion processing handles application-specific integrated circuit and video input processing IC, video memory, the ternary latch that be electrically connected with it and be used for handling the microprocessor MCU that loads user's setup parameter.
The device of described a kind of synthesizing multi-path high-definition video image picture, image resolution ratio form output image to the image that its video input sync card is set with image control base plate or backboard is controlled base plate or backboard, promptly, convert a kind of image resolution ratio form output image of default to by it no matter video input sync card is selected the vision signal input of which kind of type or which kind of resolution format; Moreover, the resolution format of all video input sync card output images is all identical, promptly by one group of common row, field sync signal and image pixel clock signal output image.
The device of described a kind of synthesizing multi-path high-definition video image picture, its video input sync card can be set the position and the size of output image respectively under the image resolution ratio form of setting.
The device of described a kind of synthesizing multi-path high-definition video image picture, it according to row field sync signal Hor-Sync-BT, Ver-Sync-BT, system clock Sys-Clk and user's setup parameter User-Defi-Paras, directly produces the control signal that corresponding every video input sync card is exported effective view data: Hor-DE-SPn and Ver-DE-SPn by image control base plate or backboard.
The device of described a kind of synthesizing multi-path high-definition video image picture, its all video input sync card all latchs with the form of three-state or homophase, anti-phase buffering drive output image data and control base plate or backboard to image, its high-impedance state is by image output enable control signal IMG-OE-SPn control, and this signal is produced through the logic synthesis unification by image control base plate or backboard according to Hor-DE-SPn and Ver-DE-SPn etc.
The device of described a kind of synthesizing multi-path high-definition video image picture, it is in order to expand more video input sync cards, image control base plate or backboard increase just that the one-level three-state latchs or homophase, reverse buffering drive circuit every p slot, and the high-impedance state that produces corresponding every stage drive circuit simultaneously enables control signal IMG-OE-BTm (m=1,2,3 ... M).
Advantage of the present utility model is, multi-channel video picture signals such as having common SD composite video (PAL/NTSC), SD/high definition component vide, VGA, DVI, HDMI and HDSDI at present can be carried out real-time video and handle, realize tile, window, stack etc. flexibly picture synthesize.
Description of drawings
Fig. 1 is a system block diagram of the present utility model;
Fig. 2 is a video input sync card output sprite stack schematic diagram of the present utility model;
Fig. 3 controls base plate or backboard image data transmission passage with the form output image data of three-state to image control base plate or backboard and image for video of the present utility model input sync card and drives the view data schematic diagram step by step with the form of three-state;
Fig. 4 is of the present utility model by image control base plate or backboard generation IMG-OE-SPn and IMG-OE-BTm schematic diagram;
Fig. 5 is the circuit block diagram schematic diagram of video input sync card of the present utility model;
Fig. 6 is the ternary latch cicuit instance graph of video input sync card output image data of the present utility model;
Fig. 7 is the logic control circuit instance graph of image control base plate of the present utility model or backboard.
Concrete enforcement
This picture synthesizer adopts the plug-in card mode to design, and shown in Fig. 1 system block diagram, it mainly comprises N piece video input sync card and image control base plate or backboard.Every video input sync card can receive the vision signal of the dissimilar and form of multichannel, and the user can choose wherein 1 the tunnel wantonly and show as the synthon picture.N piece video input sync card then can produce N width of cloth synthon picture, and N width of cloth synthon picture switches by the transmission and the selection of image control base plate or backboard, and then synthetic 1 width of cloth output image, with the form output of VGA, DVI or HDMI.
Video input sync card is supported the dissimilar and format video signal input of multichannel, such as: PAL/NTSC * 2+HDSDI * 1+HDMI * 1+VGA * 1+DVI * 1.Simultaneously, the image resolution ratio form output image data that this card is set with image control base plate or backboard, such as high-definition format line by line entirely, resolution: 1920 * 1080, field frequency 60Hz.Image control base plate or backboard are set the image resolution ratio form with row, field sync signal and image pixel clock signal, such as above-mentioned resolution is 1920 * 1080, field frequency is that the full line frequency of high-definition format line by line of 60Hz is 67.5KHz, and line frequency is 60Hz, and pixel clock is 148MHz.The N piece video input sync card that inserts image control base plate or backboard is all with identical image resolution ratio form output image data.Moreover, we also can set the size and the position of every video input sync card output image arbitrarily and promptly compress inputted video image in a sprite window, and it is respectively by following four groups of parameter-definitions:
| The horizontal original position of output image | Hor-Str-SPn |
| The output image horizontal width | Hor-Wid-SPn |
| The vertical original position of output image | Ver-Str-SPn |
| The output image vertical height | Hor-Str-SPn |
As shown in Figure 2, under 1920 * 1080 resolution formats, No. 1 video input sync card output sprite SP1, No. 2 video input sync card output sprite SP2, the SP2 part is superimposed upon above the SP1.
Simultaneously, as shown in Figure 2, video input sync card can produce image of corresponding its output sprite and export effective control signal, as to sprite SP1, and the effective control signal Hor-DE-SP1 of its level, vertical effectively control signal Ver-DE-SP1.
All video input sync cards all latch or cushion the driving output image data to image control base plate or backboard, as shown in Figure 3 with the form of three-state.Its high-impedance state is by image output enable control signal IMG-OE-SPn control, and IMG-OE-SPn is produced by image control base plate or backboard.
In the synthetic picture of N width of cloth output image to 1 width of cloth for synthetic N piece video input sync card, image control base plate or backboard produce image output enable control signal must for every video input sync card: IMG-OE-SPn (n=1,2,3 ... N).Simultaneously, in order to expand more video input sync cards, image control base plate or backboard increase just that the one-level three-state latchs or homophase, reverse buffering drive circuit every p slot, and the high-impedance state that produces corresponding every stage drive circuit simultaneously enables control signal IMG-OE-BT m (m=1,2,3 ... M).
Image control base plate or backboard produce IMG-OE-SPn and IMG-OE-BTm according to Hor-DE-SPn, Ver-DE-SPn, Sys-Clk and user's setup parameter User-Defi-Paras.As shown in Figure 4, Hor-DE-SPn, Ver-DE-SPn are also directly produced according to row field sync signal Hor-Sync-BT, Ver-Sync-BT, system clock Sys-Clk and user's setup parameter User-Defi-Paras by image control base plate or backboard.
IMG-OE-SPn and IMG-OE-BTm are the switch-over control signals of realizing that picture is synthetic, and as shown in Figure 2, SP2 is the top layer sprite, then:
IMG-OE-SP2=Hor-DE-SP2 logical AND Ver-DE-SP2
Yet SP1 is a second layer sprite:
IMG-OE-SP1=(Hor-DE-SP1 logical AND Ver-OverLap-DE-SP1) logic OR (Hor-OverLap-DE-SP1 logical AND Ver-DE-SP1 logical AND Ver-DE-SP2)
Image control base plate or backboard enable the view data that control signal selects to switch each video input sync card output according to IMG-OE-SPn and IMG-OE-BTm output image data, as showing the SP1 sub picture period, IMG-OE-SP1=0, and other IMG-OE-SPn (n ≠ 1)=1.
Whole system adopts the unified clock design, and the clock frequency of image control base plate or backboard and all input sync cards is identical.
It is as follows that part of the present utility model is specifically implemented circuit diagram:
Fig. 5 is the circuit block diagram of video input sync card, and the dedicated video input processing IC that wherein adopts ST company to produce selects for use FLI32626H-BG to import processing integrated circuit as video image.FLI32626H-BG can directly receive HDMI, DVI, VGA, CVBS high definition or SD vision signals such as (PAL/NTSC), the HDSDI/SDI digital high-definition video signal then earlier through the demodulator circuit GS2974 demodulation decoding circuit GS2974 decoding of GENNUM company, is transported to the DIGITAL INPUT mouth of FLI32626H-BG.FLI32626H-BG works in the motor synchronizing mode, and FLI32626H-BG is with the synthetic required image pixel clock of different-format of 19.6608MHz crystal, and to row, field sync signal that should form.FLI32626H-BG output image data to video image is handled application-specific integrated circuit.Video image is handled the effect that application-specific integrated circuit is mainly finished image compression and the conversion of frame speed, it is with external sync mode work, and the pixel clock of its output image data (Pixel Clk), row field sync signal (Hor-Sync, Ver-Sync) are from image control base plate or backboard; The concrete model of ternary latch is LVC1637 among the figure; Microprocessor MCU is used for handling loading user setup parameter.
Fig. 6 is the ternary latch cicuit of video input sync card output image data, latch is selected the SN74LVC16374ADGGR of TI company for use, totally 30 of the view data of N10 output, each 10 of red, green and blues, N12 among Fig. 6 latchs wherein 15, and remaining 15 are latched by another sheet SN74LVC16374ADGGR.View data CH1D0 ~ the CH1D14 of N10 output is output as CH1Q0 ~ CH1Q14 after latching.And " IMG-OE-CH1 " when being high, and CH1Q0 ~ CH1Q14 is high resistant output.
Fig. 7 is the logic control circuit of image control base plate or backboard, and N25 selects programmable logic chip (EPLD) the EPM7064AETC44 design of ALTERA company for use.Wherein input signal Sys-Clk, Hor-Sync-BT, Ver-Sync-BT are that image control base plate or backboard are set the pixel clock of image resolution ratio form and row, field sync signal; MCU-CNT0, MCU-CNT1, MCU-CNT2 and MCU-CNT3 are the Communication Control signal of microprocessor and EPM7064AETC44, are used for loading user's setup parameter: User-Defi-Paras.The logical relation of each input/output signal is mainly determined by the EPM7064AETC44 programming in Fig. 7 example, be mainly: EPM7064AETC44 at first produces M signal according to Sys-Clk, Hor-Sync-BT, Ver-Sync-BT and User-Defi-Paras: Hor-DE-SPn and Ver-DE-SPn, and then generate IMG-OE-SPn (n=1...9) and IMG-OE-BTm (m=1...3) by the stacked relation of Hor-DE-SPn, Ver-DE-SPn and each sprite.
Concrete sprite situation as shown in Figure 2, SP2 is the top layer sprite, then:
IMG-OE-SP2=Hor-DE-SP2 logical AND Ver-DE-SP2
Yet SP1 is a second layer sprite:
The different stacked relation of picture of IMG-OE-SP1=(Hor-DE-SP1 logical AND Ver-OverLap-DE-SP1) logic OR (Hor-OverLap-DE-SP1 logical AND Ver-DE-SP1 logical AND Ver-DE-SP2), the logical relation difference between the signal.
Claims (9)
1. the device of a synthesizing multi-path high-definition video image picture, the power supply that comprises cabinet, image processing apparatus and power for their is characterized in that image processing apparatus comprises:
(1), is used to switch each video-input image data of gating, a synthetic thus width of cloth output image, the realization picture is synthetic, comprise tiling, window or the Overlay function, come to produce image output enable control signal according to Hor-DE-SPn, Ver-DE-SPn, Sys-Clk and user's setup parameter User-Defi-Paras: IMG-OE-SPn (n=1,2,3 to video input sync card ... N) and the high-impedance state that produces the drive circuit of correspondence image data transmission channel enable control signal IMG-OE-BT m (m=1,2,3 ... M) image control base plate or backboard; (2), be connected, the N of optionally connected receipts N road real time video signals and output image data signal opens video input sync card with image control base plate or backboard signal input part.
2. the device of a kind of synthesizing multi-path high-definition video image picture according to claim 1 is characterized in that, described video input sync card is that card insert type is connected with the mode that image control base plate or backboard signal input part are connected.
3. the device of a kind of synthesizing multi-path high-definition video image picture according to claim 1 and 2, it is characterized in that the circuit of described image control base plate or backboard comprises: be used to control the logic control circuit of entire circuit and the field line synchronization circuit, system clock and the clock drive circuit that are electrically connected with it, respectively with import the corresponding buffering of sync card or latch drive circuit, VGA output circuit and DVI/HDMI output circuit.
4. the device of a kind of synthesizing multi-path high-definition video image picture according to claim 3, it is characterized in that the circuit of video input sync card comprises: be used for to image dwindle/video image of processing and amplifying, frame speed conversion processing handles application-specific integrated circuit and video input processing IC, video memory, the ternary latch that be electrically connected with it and be used for handling the microprocessor MCU that loads user's setup parameter.
5. the device of a kind of synthesizing multi-path high-definition video image picture according to claim 1 and 2, it is characterized in that, image resolution ratio form output image to the image that video input sync card is set with image control base plate or backboard is controlled base plate or backboard, promptly, convert a kind of image resolution ratio form output image of default to by it no matter video input sync card is selected the vision signal input of which kind of type or which kind of resolution format; Moreover, the resolution format of all video input sync card output images is all identical, promptly by one group of common row, field sync signal and image pixel clock signal output image.
6. the device of a kind of synthesizing multi-path high-definition video image picture according to claim 1 and 2 is characterized in that, video input sync card can be set the position and the size of output image respectively under the image resolution ratio form of setting.
7. the device of a kind of synthesizing multi-path high-definition video image picture according to claim 1 and 2, it is characterized in that, according to row field sync signal Hor-Sync-BT, Ver-Sync-BT, system clock Sys-Clk and user's setup parameter User-Defi-Paras, directly produce the control signal that corresponding every video input sync card is exported effective view data: Hor-DE-SPn and Ver-DE-SPn by image control base plate or backboard.
8. the device of a kind of synthesizing multi-path high-definition video image picture according to claim 1 and 2, it is characterized in that, all video input sync card all latchs with the form of three-state or homophase, anti-phase buffering drive output image data and control base plate or backboard to image, its high-impedance state is by image output enable control signal IMG-OE-SPn control, and this signal is produced through the logic synthesis unification by image control base plate or backboard according to Hor-DE-SPn and Ver-DE-SPn etc.
9. the device of a kind of synthesizing multi-path high-definition video image picture according to claim 1 and 2, it is characterized in that, in order to expand more video input sync cards, image control base plate or backboard increase just that the one-level three-state latchs or homophase, reverse buffering drive circuit every p slot, and the high-impedance state that produces corresponding every stage drive circuit simultaneously enables control signal IMG-OE-BT m (m=1,2,3 ... M).
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101778199A (en) * | 2010-02-09 | 2010-07-14 | 深圳市唯奥视讯技术有限公司 | Realization method for synthesizing multi-path high-definition video image picture |
| CN103544130A (en) * | 2013-10-24 | 2014-01-29 | 北京时代奥视数码技术有限公司 | Multi-window display device and multi-window display method |
| CN106993150A (en) * | 2017-04-14 | 2017-07-28 | 深圳市唯奥视讯技术有限公司 | The video image processing system and method for a kind of compatible ultra high-definition video input |
| CN112637443A (en) * | 2020-02-21 | 2021-04-09 | 西安诺瓦星云科技股份有限公司 | Source synchronous phase locking method, device and system and card-inserting type video processing equipment |
-
2010
- 2010-02-09 CN CN2010201297845U patent/CN201657185U/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101778199A (en) * | 2010-02-09 | 2010-07-14 | 深圳市唯奥视讯技术有限公司 | Realization method for synthesizing multi-path high-definition video image picture |
| CN101778199B (en) * | 2010-02-09 | 2014-02-19 | 深圳市唯奥视讯技术有限公司 | Realization method for synthesizing multi-path high-definition video image picture |
| CN103544130A (en) * | 2013-10-24 | 2014-01-29 | 北京时代奥视数码技术有限公司 | Multi-window display device and multi-window display method |
| CN103544130B (en) * | 2013-10-24 | 2016-01-20 | 北京时代奥视科技股份有限公司 | A kind of windows display equipment and display packing |
| CN106993150A (en) * | 2017-04-14 | 2017-07-28 | 深圳市唯奥视讯技术有限公司 | The video image processing system and method for a kind of compatible ultra high-definition video input |
| CN106993150B (en) * | 2017-04-14 | 2024-02-06 | 深圳市唯奥视讯技术有限公司 | Video image processing system and method compatible with ultra-high definition video input |
| CN112637443A (en) * | 2020-02-21 | 2021-04-09 | 西安诺瓦星云科技股份有限公司 | Source synchronous phase locking method, device and system and card-inserting type video processing equipment |
| CN112637443B (en) * | 2020-02-21 | 2024-05-10 | 西安诺瓦星云科技股份有限公司 | Source synchronous phase locking method, device, system and plug-in card type video processing equipment |
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