CN101778199B - Realization method for synthesizing multi-path high-definition video image picture - Google Patents
Realization method for synthesizing multi-path high-definition video image picture Download PDFInfo
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Abstract
The invention relates to a realization method for synthesizing a multi-path high-definition video image picture, which is designed by adopting a card insertion mode. The invention comprises N video input synchronization cards and an image controller. The N video input synchronization cards select and receive N paths of real-time video signals and output image data to the image controller by tristate logic respectively. The video input synchronization cards all output the image data by a group of common horizontal and field synchronizing signals and image pixel clock signals, and each video input synchronization card can respectively set the position and the size of an output image and generates effective image data control signals corresponding to an output picture of the output image: Hor-DE-SPn and Ver-DE-SPn. The image controller adds a primary tristate latch or same-phase/opposite-phase buffer drive circuit at intervals of p slots and also generates a high-impedance state enable control signal corresponding to each stage and a control signal corresponding to each video input synchronization card so as to switch and gate the image data output by each video input synchronization card, so that the function of picture synthesis is realized.
Description
Technical field:
The present invention relates to electronic engineering video image processing technology, particularly multiple paths of video images picture is synthesized to the technology of a width video image output.
Technical background:
At present, video image synthesizer or image splitter can be exported by video image synthetic 1 road video image after realtime graphic is processed multichannel is dissimilar or form, and this output is connect to 1 display device, can demonstrate several real time video images.
Common video image synthesizer can only be inputted SD composite video (PAL/NTSC), and multichannel composite video is still with 1 road composite video output after picture is synthetic, and image definition is very low.The real-time monitoring in scene of most all adopts which;
Also have high-resolution video image synthesizers such as can inputting VGA or DVI, output also can be the digital interfaces such as DVI.Conventionally there are two kinds of designs:
A kind of is to adopt the design of single circuit plate, and synthetic employing of video pictures realized with the dedicated video integrated circuit of picture-in-picture.Which design is complicated, synthetic divided frame or sprite limited amount, and the picture-in-picture passage video bandwidth of dedicated video integrated circuit is narrow, algorithm is simple, the synthetic image sharpness of impact;
Another kind is to adopt plug-in card mode to design, and every input card all shows the input of this card in picture-in-picture mode, and its output connects next stage input card and as its background frame, many card levels are unified in many pictures Yu Yi road output picture thus.Which video frequency processing chip picture-in-picture passage video bandwidth is narrow, algorithm is simple, and therefore synthetic picture is unintelligible.Meanwhile, first order input video must just be exported through multistep treatment, and delay time is oversize, and visual real-time is very poor.
Summary of the invention:
The object of the invention is, more and more universal according to the application of current digital high-definition video (HDMI, HDSDI), also there is in a large number the Video Images such as common SD composite video (PAL/NTSC), SD/high definition component vide, VGA or DVI etc. simultaneously; The video image synthesizer of looking for novelty is wanted to access more eurypalynous video image, and the needs that also full HD (1920 * 1080 resolution) real-time video is processed, provide a kind of new video image synthetic method to meet above-mentioned needs.
Another object of the present invention is that video image synthesizer also will have tiling, windows, the picture complex functionality flexibly such as stack.
The object of the invention can be achieved through the following technical solutions: a kind of implementation method of synthesizing multi-path high-definition video image picture, comprising:
(1), be used for switching each video-input image data of gating, synthesize thus a width output image, realize picture synthetic, comprise tiling, window or Overlay function, according to the effective control signal Hor-DE-SPn of level, vertical effectively control signal Ver-DE-SPn, system clock Sys-Clk and user's setup parameter User-Defi-Paras come to produce image output enable control signal: IMG-OE-SPn to video input sync card, n=1, 2, 3 ... N, enable control signal IMG-OE-BT m with the high-impedance state that produces the drive circuit of correspondence image data transmission channel, m=1, 2, 3 ... M, image controller,
(2), be connected with image controller signal input part, the N of optionally connected receipts N road real time video signals output image signal opens video input sync card.
The implementation method of described a kind of synthesizing multi-path high-definition video image picture, the mode that its video input sync card is connected with image controller signal input part is that card insert type is connected.
The implementation method of described a kind of synthesizing multi-path high-definition video image picture, its image controller is set image resolution ratio form with row, field sync signal and image pixel clock signal.
The implementation method of described a kind of synthesizing multi-path high-definition video image picture, the image resolution ratio formatted output image that its video input sync card is set with image controller is to image controller, no matter video input sync card is selected the vision signal input of which kind of type or which kind of resolution format, by it, convert a kind of image resolution ratio formatted output image of default to; Moreover, the resolution format of all video input sync card output images is all identical, by one group of common row, field sync signal and image pixel clock signal output image.
The implementation method of described a kind of synthesizing multi-path high-definition video image picture, its video input sync card can be set respectively position and the size of output image under the image resolution ratio form of setting, and both can be produced by video input sync card the effective image data controlling signal of corresponding its output picture: Hor-DE-SPn and Ver-DE-SPn, or the logical AND signal HorVer-DE-SPn of Hor-DE-SPn and Ver-DE-SPn.
The implementation method of described a kind of synthesizing multi-path high-definition video image picture, also can, by image controller according to row field sync signal Hor-Sync-BT, Ver-Sync-BT, system clock Sys-Clk and user's setup parameter User-Defi-Paras, directly produce the control signal of corresponding every video input sync card output effective image data: Hor-DE-SPn and Ver-DE-SPn.
The implementation method of described a kind of synthesizing multi-path high-definition video image picture, its all video input sync card all with the form of tri-state, latchs or homophase, anti-phase buffering driver output view data to image controller, its high-impedance state is controlled by image output enable control signal IMG-OE-SPn, and this signal is produced through logic synthesis unification by image controller according to Hor-DE-SPn and Ver-DE-SPn.
The implementation method of described a kind of synthesizing multi-path high-definition video image picture, in order to expand more video input sync cards, image controller just increases that one-level tri-state latchs or homophase, reverse buffering drive circuit every p slot, the high-impedance state that simultaneously produces corresponding every stage drive circuit enables control signal IMG-OE-BT m, m=1,2,3 ... M.
The invention has the advantages that, video signals such as having at present common SD composite video (PAL/NTSC), SD/high definition component vide, VGA, DVI, HDMI and HDSDI can be carried out to real-time video processing; Realize tile, windows, stack etc. flexibly picture synthesize.
Accompanying drawing explanation
Fig. 1 is system block diagram of the present invention;
Fig. 2 is video input sync card output sprite stack schematic diagram of the present invention;
To be video input sync card of the present invention step by step drive view data schematic diagram to image controller and image controller image data transmission passage with the form of tri-state with the formal output view data of tri-state to Fig. 3;
Fig. 4 is of the present invention by image controller generation IMG-OE-SPn and IMG-OE-BTm schematic diagram;
Fig. 5 is the circuit block diagram schematic diagram of video input sync card of the present invention;
Fig. 6 is the tri-state latch cicuit instance graph of video input sync card output image data of the present invention;
Fig. 7 is the logic control circuit instance graph of image controller of the present invention.
Concrete enforcement
This picture synthesizer adopts plug-in card mode to design, and as shown in Fig. 1 system block diagram, it mainly comprises N piece video input sync card and image controller (base plate or backboard).Every video input sync card can receive the vision signal of the dissimilar and form of multichannel, user can be optionally wherein 1 tunnel as synthon picture disply.N piece video input sync card can produce N width synthon picture, and N width synthon picture switches by transmission and the selection of image controller, and then synthetic 1 width output image, with the formal output of VGA, DVI or HDMI.
Video input sync card support multichannel is dissimilar to be inputted with format video signal, such as: PAL/NTSC * 2+HDSDI * 1+HDMI * 1+VGA * 1+DVI * 1.Meanwhile, the image resolution ratio formatted output view data that this card is set with image controller, such as high-definition format line by line entirely, resolution: 1920 * 1080, field frequency 60Hz.Image controller is set image resolution ratio form with row, field sync signal and image pixel clock signal, such as above-mentioned resolution is 1920 * 1080, field frequency is that the full line frequency of high-definition format line by line of 60Hz is 67.5KHz, and line frequency is 60Hz, and pixel clock is 148MHz.Insert the N piece video input sync card of image controller all with identical image resolution ratio formatted output view data.Moreover, we also can set arbitrarily size and the position of every video input sync card output image and compress inputted video image in a sprite window, and it is respectively by four groups of parameter-definitions below:
| The horizontal original position of output image | Hor-Str-SPn |
| Output image horizontal width | Hor-Wid-SPn |
| The vertical original position of output image | Ver-Str-SPn |
| Output image vertical height | Hor-Str-SPn |
As shown in Figure 2, under 1920 * 1080 resolution formats, No. 1 video input sync card output sprite SP1, No. 2 video input sync card output sprite SP2, SP2 local stacking is on SP1.
Meanwhile, as shown in Figure 2, video input sync card can produce image of corresponding its output sprite and export effective control signal, as to sprite SP1, and the effective control signal Hor-DE-SP1 of its level, vertical effectively control signal Ver-DE-SP1.
All video input sync cards all latch or cushion driver output view data to image controller, as shown in Figure 3 with the form of tri-state.Its high-impedance state is controlled by image output enable control signal IMG-OE-SPn, and IMG-OE-SPn is produced by image controller.
In the synthetic picture of N width output image to 1 width for synthetic N piece video input sync card, image controller produces image output enable control signal must to every video input sync card: IMG-OE-SPn (n=1,2,3 ... N).Simultaneously, in order to expand more video input sync cards, image controller just increases that one-level tri-state latchs or homophase, reverse buffering drive circuit every p slot, and the high-impedance state that simultaneously produces corresponding every stage drive circuit enables control signal IMG-OE-BT m (m=1,2,3 ... M).
Image controller produces IMG-OE-SPn and IMG-OE-BTm according to Hor-DE-SPn, Ver-DE-SPn, Sys-Clk and user's setup parameter User-Defi-Paras.As shown in Figure 4, Hor-DE-SPn, Ver-DE-SPn not only can be produced by input sync card, also can according to row field sync signal Hor-Sync-BT, Ver-Sync-BT, system clock Sys-Clk and user's setup parameter User-Defi-Paras, directly be produced by image controller.
IMG-OE-SPn and IMG-OE-BTm realize the synthetic switch-over control signal of picture, and as shown in Figure 2, SP2 is top layer sprite:
IMG-OE-SP2=Hor-DE-SP2 logical AND Ver-DE-SP2
Yet SP1 is second layer sprite:
IMG-OE-SP1=(Hor-DE-SP1 logical AND Ver-OverLap-DE-SP1) logic OR (Hor-OverLap-DE-SP1 logical AND Ver-DE-SP1 logical AND Ver-DE-SP2).
Image controller enables according to IMG-OE-SPn and IMG-OE-BTm output image data the view data that control signal selects to switch each video input sync card output, as shown SP1 sub picture period, IMG-OE-SP1=0, and other IMG-OE-SPn(n ≠ 1)=1.
Whole system adopts unified clock design, and image control base plate is identical with the clock frequency of all input sync cards.
Specific embodiment of the invention circuit diagram can be as follows:
Fig. 5 is the circuit block diagram of video input sync card, wherein adopts the dedicated video image that ST company produces to process integrated circuit FLI32626H-BG as video input process chip.FLI32626H-BG can directly receive HDMI, DVI, VGA, CVBS(PAL/NTSC) etc. high definition or SD vision signal, HDSDI/SDI digital high-definition video signal first separate to be in harmonious proportion GS2974 decoding through the GS2974 of GENNUM company and to transport to the DIGITAL INPUT mouth of FLI32626H-BG.FLI32626H-BG works in motor synchronizing mode, and FLI32626H-BG is with the synthetic required image pixel clock of different-format of 19.6608MHz crystal, and to row, field sync signal that should form.FLI32626H-BG output image data is to video image application-specific integrated circuit (ASIC) N10.N10 mainly completes the effect of image compression and the conversion of frame speed, and it is with external sync mode work, and the pixel clock of its output image data (Pixel Clk), row field sync signal (Hor-Sync, Ver-Sync) are from image controller.
Fig. 6 is the tri-state latch cicuit of video input sync card output image data, latch is selected the SN74LVC16374ADGGR of TI company, totally 30 of the view data of N10 output, each 10 of red, green and blues, N12 in Fig. 6 latchs wherein 15, and remaining 15 are latched by another sheet SN74LVC16374ADGGR.View data CH1D0 ~ the CH1D14 of N10 output is output as CH1Q0 ~ CH1Q14 after latching.And " IMG-OE-CH1 " while being high, CH1Q0 ~ CH1Q14 is high resistant output.
Fig. 7 is the logic control circuit of image controller, and N25 selects programmable logic chip (EPLD) the EPM7064AETC44 design of ALTERA company.Wherein input signal Sys-Clk, Hor-Sync-BT, Ver-Sync-BT are that image controller is set the pixel clock of image resolution ratio form and row, field sync signal; MCU-CNT0, MCU-CNT1, MCU-CNT2 and MCU-CNT3 are the Communication Control signal of microprocessor and EPM7064AETC44, are used for loading user's setup parameter: User-Defi-Paras.In Fig. 7 example, the logical relation of each input/output signal is mainly determined by EPM7064AETC44 programming, be mainly: first EPM7064AETC44 produces M signal according to Sys-Clk, Hor-Sync-BT, Ver-Sync-BT and User-Defi-Paras: Hor-DE-SPn and Ver-DE-SPn, and then generate IMG-OE-SPn(n=1.. .9 by the stacked relation of Hor-DE-SPn, Ver-DE-SPn and each sprite) and IMG-OE-BTm(m=1.. .3).
Concrete sprite situation as shown in Fig. 2, SP2 is top layer sprite:
IMG-OE-SP2=Hor-DE-SP2 logical AND Ver-DE-SP2
Yet SP1 is second layer sprite:
IMG-OE-SP1=(Hor-DE-SP1 logical AND Ver-OverLap-DE-SP1) logic OR
(Hor-OverLap-DE-SP1 logical AND Ver-DE-SP1 logical AND Ver-DE-SP2)
The stacked relation of different pictures, the logical relation between signal is different.
Claims (3)
1. an implementation method for synthesizing multi-path high-definition video image picture, comprising:
(1), image controller is used for switching each video-input image data of gating, synthesize thus a width output image, realize picture synthetic, comprise tiling, window or Overlay function, according to the effective control signal Hor-DE-SPn of level, vertical effectively control signal Ver-DE-SPn, system clock Sys-Clk and user's setup parameter User-Defi-Paras come to produce image output enable control signal: IMG-OE-SPn to video input sync card, n=1, 2, 3 ... N, enable control signal IMG-OE-BT m with the high-impedance state that produces the drive circuit of correspondence image data transmission channel, m=1, 2, 3 ... M,
(2), N opens that video input sync card is connected with image controller signal input part, optionally connected receipts N road real time video signals output image signal;
The mode that wherein video input sync card is connected with image controller signal input part be card insert type be connected and described image controller with row, field sync signal and image pixel clock signal are set image resolution ratio form, it is characterized in that, video input sync card can be set respectively position and the size of output image under the image resolution ratio form of setting, by video input sync card, produced the effective image data controlling signal of corresponding its output picture: Hor-DE-SPn and Ver-DE-SPn, or the logical AND signal HorVer-DE-SPn of Hor-DE-SPn and Ver-DE-SPn.
2. the implementation method of a kind of synthesizing multi-path high-definition video image picture according to claim 1, it is characterized in that, all video input sync cards all with the form of tri-state, latch or homophase, anti-phase buffering driver output view data to image controller, its high-impedance state is controlled by image output enable control signal IMG-OE-SPn, and this signal is produced through logic synthesis unification by image controller according to Hor-DE-SPn and Ver-DE-SPn.
3. the implementation method of a kind of synthesizing multi-path high-definition video image picture according to claim 1 and 2, it is characterized in that, in order to expand more video input sync cards, image controller just increases that one-level tri-state latchs or homophase, reverse buffering drive circuit every p slot, the high-impedance state that simultaneously produces corresponding every stage drive circuit enables control signal IMG-OE-BT m, m=1,2,3 ... M.
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| CN102737614A (en) * | 2011-04-13 | 2012-10-17 | 宁波奇科威智能科技有限公司 | Method for realizing multi-layer image display on joint screen and joint screen |
| CN102427511B (en) * | 2011-09-28 | 2014-06-04 | 杭州士兰微电子股份有限公司 | Multi-channel digital video image processing method and device |
| CN102665048A (en) * | 2012-04-12 | 2012-09-12 | 北京华夏电通科技股份有限公司 | Method and system for implementation of multi-picture composition |
| CN102724431A (en) * | 2012-06-19 | 2012-10-10 | 深圳市宇泰科技有限公司 | Method and system for synthesis of multipicture high-definition images |
| CN103137094A (en) * | 2012-12-04 | 2013-06-05 | 江苏清投视讯科技有限公司 | Split joint image processor used for image matting |
| CN106341622B (en) * | 2015-07-06 | 2020-01-24 | 阿里巴巴集团控股有限公司 | Method and device for encoding multi-channel video stream |
| CN105704408B (en) * | 2016-02-04 | 2018-08-03 | 天津市英贝特航天科技有限公司 | The real-time overlapping controller of asynchronous image and its stacking method |
| CN106507139A (en) * | 2016-11-16 | 2017-03-15 | 深圳市捷视飞通科技股份有限公司 | Multi-path high-definition video multiplex display packing and device |
| CN109600532B (en) * | 2018-12-13 | 2020-04-03 | 中国科学院西安光学精密机械研究所 | Unmanned aerial vehicle multi-channel video seamless switching system and method |
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