CN1755697A - System-level circuit inspection method and tool - Google Patents
System-level circuit inspection method and tool Download PDFInfo
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- CN1755697A CN1755697A CN 200410051694 CN200410051694A CN1755697A CN 1755697 A CN1755697 A CN 1755697A CN 200410051694 CN200410051694 CN 200410051694 CN 200410051694 A CN200410051694 A CN 200410051694A CN 1755697 A CN1755697 A CN 1755697A
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Abstract
The invention relates to a circuit checking method and tool. First, guiding a middle file with general layout from each function picture of the system circuit, forming initial data and storing them by analyzing the middle file, doing data checking according to the relation between the single bands, the relation between the connector of the single bands, the user selecting faucet and the signal equipment; chaining and riddling the data and returning the data with checking result.
Description
Technical field
The present invention relates to circuit is examined to guarantee the correct electric circuit inspection technical field that connects of electrical network, relate in particular to a kind of system-level circuit checking method and instrument.
Background technology
In the electronic market of high competition, the time of going on the market of product more and more shortens.The communications field particularly, central processing unit (CPU) at a high speed, digital signal processor (DSP) wait to use and get more and more, and function also becomes increasingly complex.The of short duration research and development of products cycle forces development teams to stand on forefathers' the shoulder to carry out local renewal to reach the performance of expectation at new unit.In order to improve design efficiency (for example change chip or increase function), realize that the circuit of a certain function often is designed to module, and by unified interface---bus is connected in the system.Along with improving constantly of processor processing ability, the bus of various different structures is applied in the product simultaneously, become increasingly complex by being connected of circuit become between module and the module, do not note the low staging error that will connect in the design slightly, directly the progress of influence research and development.
At present, connector is widely used in the electronic equipment in order to connect two or polylith circuit board: have plenty of the restriction of the small product size of being subjected to, be forced to use the polylith printed panel in order to put down all electronic components, as mobile phone, individual palm PC etc.; Have plenty of for the dirigibility that improves product function and dispose, can realize multiple function etc. by inserting different integrated circuit boards as computer motherboard.Be illustrated in figure 1 as the common a kind of topological structure of system-level circuit, adopt veneer+buckle, or the form of mainboard+plug-in card.Be illustrated in figure 2 as the common another kind of topological structure of system-level circuit, adopt the form of backboard+veneer.Say that from electrical principle connector just connects two circuit boards by connecting between the veneer, as long as the electrical network that pin connected on both sides is the just passable of unanimity.But along with the increase of circuit complexity, a signal wire has usually connected the several piece veneer and need pass through a plurality of connectors.Trouble is the system that structure can flexible configuration, its connector can connect dissimilar veneer (for example the expansion slot of computer motherboard can connect network interface card, sound card and video card or the like) to expand different functions in different application scenarios, no problem when being very easy to take place to connect veneer A, plug the collapse fault that board B then can cause total system.
For the ease of design and management, each piece veneer is typically designed as an independently schematic diagram.These schematic diagrams use audit function that design tools (as the ViewDraw of Mentor company) provide can inspection plate in the connection correctness of schematic diagram electrical network.But just can't use for this audit function of circuit (schematic diagrams of other veneers) that connector is outer, need the manual schematic diagram of slip-stick artist to carry out manual review in conjunction with the definition of the connector in the specification and each design, two relevant interface units of contrast are examined each connects electrical network in two schematic diagrams to pin correctness one by one.
The shortcoming of prior art is:
1, the difference of design team use habit causes the making of schematic diagram to use different principle diagram design instruments, the incompatible examination difficulty that has increased system-level circuit of form;
2, examination relate to the several piece veneer, the unusual difficulty of the system level signals line that passes through a plurality of connectors;
3, examination efficient is exponential form decline with the increase of design complexity, and simple manual review also is very easy to make mistakes.
Summary of the invention
Technical matters to be solved by this invention is: overcome the deficiency that can't examine system-level circuit easily and effectively when prior art is carried out the circuit examination, a kind of system-level circuit checking method and instrument are provided, thereby can realize system-level circuit examination convenient, efficiently and accurately.
The present invention solves the problems of the technologies described above the technical scheme that is adopted to be:
This system-level circuit checking method may further comprise the steps:
A, each the principle diagram design instrument that is at first adopted from the single-plate grade circuit design are derived a kind of intermediate file that comprises components and parts and electrical network information of common format;
After B, described intermediate file are handled by analysis, form raw data and preserve;
C, raw data is carried out data query according to the relation of connector on the relation between veneer and the veneer and each veneer and connector or the signal wire that the user will examine;
D, data are linked and screen, and return the data that comprise examination result.
Described method also further comprises: the data of returning are handled, generated and to comprise form, the file of examination result, or call drafting system according to the examination result circuit topological structure intuitively that draws.
Described intermediate file can adopt the net table.Among the described step B, middle file is carried out analyzing and processing be may further comprise the steps: according to the difference of described intermediate file format, call corresponding analysis engine and each intermediate file is carried out the unit separates and the coupling of information type, therefrom draw the raw data of device number, device package, device parameters, electrical network label, device annexation; Then raw data is removed the format manipulation of invalid information.
With the connector be examination object when examining, to data screen, step of connecting comprises:
D1, from the device number of a certain veneer, search, and filter out the device pin of the connector that will examine by the examination object;
D2, in the electrical network of this veneer, search each pin on this connector, and filter out and be attached thereto the electrical network that connects, form the electrical network group that is connected with this connector according to device pin;
D3, filter out the connection situation of all electrical networks on this veneer, comprise that all are connected to components and parts and connector on this electrical network group according to this electrical network group;
D4, obtain each root electrical network on this electrical network group on this veneer except that being examined all connectors of connector, and find this electrical network group to be penetrated into the connector of other veneer in concerning according to the connector that is set by the user;
D5, filter out the connection situation of connector on described other veneer according to D1, D2, the described method of D3 again;
D6, the electrical network of the above-mentioned electrical network group several sections on each veneer that gets access to is connected, remove and draw electrical network group complete structure in system design behind the connector;
Obtain the particulars of a certain signal wire if desired, then from the result that above-mentioned steps D6 generates, filter out the signal wire of being examined, draw the situation of the components and parts that connected on this signal wire.
Corresponding a kind of system-level circuit examination instrument comprises schematic diagram data analysis module, data processing module, database module and subscriber interface module; Described schematic diagram data analysis module, data processing module and database module are linked in sequence, the schematic diagram data analysis module reads components and parts and the electrical network information on each principle diagram design instrument design concept figure, and these information are sent to data processing module; Data processing module carries out the data on the schematic diagram to deposit described database module in after the analyzing and processing; Described subscriber interface module is connected with database module with described data processing module respectively, the relation of connector on veneer that is used to be provided with and the relation between the veneer and each veneer, and select connector or the signal wire that to examine, issue Inspection Order, generate database instruction and carry out data query to database module.
Beneficial effect of the present invention is: the present invention uses the intermediate file of common format such as net table to obtain schematic diagram information, supports the schematic diagram of multiple principle diagram design tool making, for multi-platform design provides interface, has solved the problem of multiple schematic diagram interface examination; Can use database module to manage all schematic diagram data of whole design, be connected etc. with the topological structure that is used to obtain local bus and individual signals line detailed according to certain mode.The present invention realizes penetrating of electrical network according to the annexation of connector both sides pin, make a plurality of schematic diagrams be coupled to a complete design, the efficient and the accuracy of the examination of veneer interface circuit have been improved, can obtain the topological structure of bus in total system fast, and can support to consult in the total system all and be connected to the device form of specifying electrical network, thereby find the hidden danger of HW High Way on integral body connects in advance.
In sum, the present invention can carry out system-level circuit examination, eliminated the incompatible influence of form that multiple principle diagram design instrument causes system-level schematic diagram examination, and eliminated the influence of connector to examination, the system that a plurality of veneers are formed merges into a complete electrical network, for follow-up examination provides data.And can give prominence to certain connector or certain the root signal wire that the user pays close attention to, and electrical network that is attached thereto on all veneers and device, the then conductively-closed that other are irrelevant, thereby the scope that can dwindle examination improve the efficient of examination.
Description of drawings
Fig. 1 is the common a kind of topological structure synoptic diagram of system-level circuit;
Fig. 2 is the common another kind of topological structure synoptic diagram of system-level circuit;
Fig. 3 is the structural representation of the system-level circuit examination of the present invention instrument;
Fig. 4 is a principle of the invention diagram data acquisition methods synoptic diagram;
Fig. 5 is a data input stream journey synoptic diagram of the present invention;
Fig. 6 is a data query schematic flow sheet of the present invention;
Fig. 7 exports synoptic diagram for the result that the present invention examines connector;
Fig. 8 exports synoptic diagram for the result that the present invention examines signal wire.
Embodiment
With embodiment the present invention is described in further detail with reference to the accompanying drawings below:
The difficult point of system-level circuit examination is that connector has cut off the circuit of disparate modules (veneer), one side may be drawn high positive supply from the signal wire of seeing of connector separately, no problem; From the another side of connector, it also is no problem that signal wire draws by hanging down to power supply ground again, and both sides all adhere to specification, yet two circuit boards are made the back butt joint, the consequential signal line is neither high level neither low level, and system enters unsure state immediately, and fault is so far just found.For the system level signals line that is connected to the polylith veneer, the probability that this problem occurs is just bigger.Only remove the influence of connector, grasp the situation of signal wire after passing connector, just can guarantee the correctness of each root signal wire in total system on each module from the overall situation.
In order to improve the shortcoming of prior art, the present invention utilizes the powerful data management function of computing machine that the data of whole design are handled, the user only need need examine that connector or signal wire by close friend's the interface instrument of telling, wait and to obtain related with it all information (for example topological structure or the like), the then conductively-closed that other are irrelevant, thus the efficient of examination improved.
As shown in Figure 3, the present invention realizes by software design, form system-level circuit examination instrument, bus level circuit examination instrument of the present invention by schematic diagram data analysis module, data processing module, database module and user interface totally four major parts constitute, the effect of each several part is as follows:
1) the schematic diagram data analysis module is used to eliminate multiple principle diagram design instrument to the influence that system-level schematic diagram examination causes, and is responsible for reading information such as components and parts on the various principle diagram design instrument design concept figure and electrical network;
2) data processing module is responsible for the raw data that the schematic diagram data analysis module reads being classified and formaing, and the data of choosing wherein such as components and parts model, pin and electrical network deposit database module in;
3) database module is used for the management and the inquiry of data, will be merged into a complete electrical network by the examination design circuit, eliminates the influence and certain connector of outstanding user concern or the be connected situation of certain root signal wire of connector to examination;
4) subscriber interface module provides friendly interface, operates the ease for use of raising instrument with the wizard of hommization.
Below principle of the present invention is specifically described:
One, the schematic diagram data obtaining and analyzing
Each principle diagram design instrument all can adopt the design document of specific format to be used for the management of schematic diagram, but since these privately owned forms generally can externally not announce, therefore directly from design document, obtain data and be unusual difficulty.Investigate the designed schematic diagram of different principle plan design tool, the information that it comprised can be divided into these three kinds of data of device, electrical network and note basically.Removing this class help information of note, is exactly device and electrical network corresponding to the critical data of a schematic diagram, and just the net table (netlist).
The net table has multiple form, common net table generally is the text of ASCII coding, it self rule is arranged (for example: leading expression resistance device R10 for the net table of different-format for " #R10 ", “ $GND " expression electrical network GND or the like), but based on it is bridge between principle diagram design and the printed board design, most form all is disclosed, and more relatively easily, so the present invention adopts the net table to examine as raw data at the tectonic analysis engine.As long as the principle diagram design instrument can be exported the net table of common format, the present invention just can read the schematic diagram that is designed by this principle diagram design instrument by corresponding data analysis module.
As shown in Figure 4, analysis engine is one section text grammer routine analyzer writing according to the rule of difference net table in the data analysis module of the present invention, is used to separate every unit information, mates and removes leading symbol etc.Extension name difference according to user-in file judges which kind of type the net table is, calls corresponding analysis engine automatically these net tables are analyzed.The subsequent analysis engine begins to read the text in the net meter file, and according to the tabular difference of net, analysis engine is at first searched specific separator, and a pile text that will obtain from the net table carries out the unit to be separated.The text that has separated carries out the information type coupling at once, be converted to raw data such as device number, device package, device parameters, electrical network label, device annexation respectively, start formatting module simultaneously and raw data is removed invalid informations such as space and leading symbol, it is stand-by to be saved in database at last.
Net table (file extension is generally * .tel) with common Allegro form is specifically introduced below:
Represent following be device package information and device parameters as this key word.
SR0603!′R0603_4K7′！′4.7K′；R51?R52?R171?R172
Wherein, " SR0603 " expression device is numbered the device package model of R51/R52/R171/R172, and ' R0603_4K7 ' is a supplemental instruction, and ' 4.7K ' is the resistance sizes of resistor, "! " and "; " be leading character, " " (space) is decollator.
Represent the following electrical network information that is as this key word.
′+5VI′；C36：F2041.2C38：F2028.1C39：F2000.1
Wherein, '+5VI ' expression network label, decollator "; " data of expression back are device and the pin that electrical network connected, for example the 2nd pin of " C36:F2041.2 " expression capacitor C 36 be connected to+5VI on, ": " and ". " have been exactly leading character here.
Separate exactly and need the text on each row be separated into " '+5VI ' ", "; C36:F2041.2 " and " C38:F2028.1 " these unit, coupling then is to search “ $NETS ", "; ", ": " or the like contain the character of Special Significance, and then can sort out these texts, so just can be the unite purpose of the multiple principle diagram design instrument of realization compatibility of different net tables.
Two, the implementation of circuit examination
System-level circuit examination needs the schematic diagram of at least 2 associations just can carry out.As shown in Figure 5 and Figure 6, from the net table of principle diagram design instrument derivation common format, deposit database module in after the analysis of schematic diagram data process data analysis module, the processing.The user issues Inspection Order by the user interface of examination instrument then.These orders are converted into the information that comprises examination object, review mode and examination rule etc. on the backstage, generate database instruction and carry out data query in conjunction with user-specified parameters (comprising schematic diagram relation, connector relation or the like) back.
As shown in Figure 7, current examination object is connector J1, and it is corresponding to the groove position 1 of backboard, and corresponding is connector J1 on veneer A.Bus Z cross-over connection on connector J1 backboard, veneer A, B and C.The relation of connector on relation (for example: backboard, master control borad, business board or the like) between veneer and the veneer and each veneer is set by subscriber interface module by the user; Connector that selection is examined or signal wire, issue Inspection Order by user interface, these orders generate the data query that database instruction carries out database module after being converted into the information of examining object (as connector J1), review mode (as obtain connector J1 and go up bus Z at the electrical network on veneer A and the board B) and examination rule (as reporting the device that comprises that serial resistance, matching capacitance etc. link to each other with bus Z) etc. on the backstage.Database engine screens, connects and sort data according to instruction, and concrete steps are as follows:
1, from the device number of veneer A, searches the device pin of being examined object connector J1 and filtering out connector;
2, the result who draws according to step 1 searches in the electrical network of veneer A by each pin on the examination object, and filters out and be attached thereto the electrical network that connects, and forms the electrical network group (bus Z) that is connected with connector J1;
3, the bus Z that draws according to step 2 filters out the connection situation of all electrical networks on the bus Z in the electrical network of veneer A, comprise that all are connected to components and parts and connector on the bus Z, so far device and the electrical network conductively-closed that has nothing to do with quilt examination object on the veneer A;
4, obtain " bus Z " one by one and go up each root electrical network all connectors except that connector J1 on veneer A, and according to finding " bus Z " to be penetrated on the connector of backboard in the connector relation that is set by the user;
5, on backboard, filter out the situation that is connected with the corresponding connector of its connector (J2, J3) according to similar step 1 and 2 method, same, with the irrelevant device of these connectors and electrical network also conductively-closed;
6, the electrical network of bus Z several sections on backboard, veneer A and board B that above-mentioned steps is got access to is connected, and removes and draws bus Z complete structure in system design behind the connector;
7, can select at last the result to be sorted according to the network numbering of electrical network.
Examination result is sent to subscriber interface module, because the information that generally comprises is many on the bus Z, and the screen size of computing machine is limited, so what at first show on the user interface is the topological structure of bus Z.According to user's use habit, subscriber interface module will use the topological structure of form output character form, or calls position and numbering that drafting system is depicted veneer and their position and relation, connector, also has the topological structure of bus Z.
For signal wire at a high speed, also need the slip-stick artist in bus, to extract, analyze primary controller, build-out resistor, last pull down resistor, coupling capacitance, connector and equipment etc. and be connected to whether all devices meet the standard of this bus on this HW High Way, thereby scent a hidden danger in advance.The particulars of single signal if desired, the query function that can use the examination instrument to provide.Activating querying command behind the electrical network that the user only need select to be examined gets final product.As shown in Figure 8, obtain the particulars of a certain signal wire if desired, can from the result that above-mentioned data query step generates, filter out the signal wire of being examined, the device shielding that has no truck with, subscriber interface module will reuse the examination result of form output character form or call the connection situation that drafting system is described this signal wire position, network label and each device, thereby draw the resistance, electric capacity, connector and the chip that are connected on this signal wire or the like information.Among the graphical result such as output a resistance R 1 is arranged, then can on screen, draw the symbol of a resistance, belong to any piece veneer, so realize the visualize of examination result with device number and device parameters, the mark resistance of this resistance of tense marker.
The present invention uses intermediate file (including but not limited to the net table) to obtain schematic diagram information, solves the problem of multiple schematic diagram interface examination; Use database module to manage all schematic diagram data of whole design, be connected with the topological structure that is used to obtain local bus and individual signals line detailed etc. according to certain mode; Annexation according to connector both sides pin realizes penetrating of electrical network, makes a plurality of schematic diagrams be coupled to a complete design.The efficient and the accuracy of the examination of veneer interface circuit have been improved, can obtain the topological structure of bus in total system fast, support is consulted in the total system all and is connected to the device form of specifying electrical network, thereby finds the hidden danger of HW High Way on integral body connects in advance.
Those skilled in the art do not break away from essence of the present invention and spirit, can there be the various deformation scheme to realize the present invention, the above only is the preferable feasible embodiment of the present invention, be not so limit to interest field of the present invention, the equivalent structure that all utilizations instructions of the present invention and accompanying drawing content are done changes, and all is contained within the interest field of the present invention.
Claims (7)
1, a kind of system-level circuit checking method is characterized in that, may further comprise the steps:
A, each the principle diagram design instrument that is at first adopted from the single-plate grade circuit design are derived a kind of intermediate file that comprises components and parts and electrical network information of common format;
After B, described intermediate file are handled by analysis, form raw data and preserve;
C, raw data is carried out data query according to the relation of connector on the relation between veneer and the veneer and each veneer and connector or the signal wire that the user will examine;
D, data are linked and screen, and return the data that comprise examination result.
2, system-level circuit checking method according to claim 1, it is characterized in that: described method also further comprises: the data of returning are handled, generation comprises form, the file of examination result, or calls drafting system according to the examination result circuit topological structure intuitively that draws.
3, system-level circuit checking method according to claim 1 and 2 is characterized in that: the intermediate file of described general format adopts the net table.
4, system-level circuit checking method according to claim 3 is characterized in that: among the described step B, middle file is carried out analyzing and processing may further comprise the steps:
The difference of B1, the described file layout of foundation, call corresponding analysis engine and each intermediate file is carried out the unit separates and the coupling of information type, therefrom draw the raw data of device number, device package, device parameters, electrical network label, device annexation;
B2, raw data removed the format manipulation of invalid information.
5, system-level circuit checking method according to claim 3 is characterized in that: with the connector be examination object when examining, the step that data are linked, screen comprises:
D1, from the device number of a certain veneer, search, and filter out the device pin of the connector that will examine by the examination object;
D2, in the electrical network of this veneer, search each pin on this connector, and filter out and be attached thereto the electrical network that connects, form the electrical network group that is connected with this connector according to device pin;
D3, filter out the connection situation of all electrical networks on this veneer, comprise that all are connected to components and parts and connector on this electrical network group according to this electrical network group;
D4, obtain each root electrical network on this electrical network group on this veneer except that being examined all connectors of connector, and find this electrical network group to be penetrated into the connector of other veneer in concerning according to the connector that is set by the user;
D5, filter out the connection situation of connector on described other veneer according to said method again;
D6, the electrical network of the above-mentioned electrical network group several sections on each veneer that gets access to is connected, remove and draw electrical network group complete structure in system design behind the connector.
6, system-level circuit checking method according to claim 5, it is characterized in that: the particulars of obtaining a certain signal wire if desired, then from the result of above-mentioned generation, filter out the signal wire of being examined, draw the situation of the components and parts that connected on this signal wire.
7, a kind of system-level circuit examination instrument is characterized in that: comprise schematic diagram data analysis module, data processing module, database module and subscriber interface module;
Described schematic diagram data analysis module, data processing module and database module are linked in sequence, the schematic diagram data analysis module reads components and parts and the electrical network information on each principle diagram design instrument design concept figure, and these information are sent to data processing module; Data processing module carries out the data on the schematic diagram to deposit described database module in after the analyzing and processing;
Described subscriber interface module is connected with database module with described data processing module respectively, the relation of connector on veneer that is used to be provided with and the relation between the veneer and each veneer, and select connector or the signal wire that to examine, issue Inspection Order, generate database instruction and carry out data query to database module.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100516948A CN100426304C (en) | 2004-09-30 | 2004-09-30 | System-level circuit inspection method and tool |
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| CNB2004100516948A CN100426304C (en) | 2004-09-30 | 2004-09-30 | System-level circuit inspection method and tool |
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| CNB2004100516948A Expired - Fee Related CN100426304C (en) | 2004-09-30 | 2004-09-30 | System-level circuit inspection method and tool |
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| CN102323964A (en) * | 2011-08-16 | 2012-01-18 | 北京芯愿景软件技术有限公司 | Digital circuit net list data processing method |
| CN103020339A (en) * | 2012-11-29 | 2013-04-03 | 王志欣 | Method for implementing combined automobile circuit diagrams |
| CN103745050A (en) * | 2013-12-27 | 2014-04-23 | 北京亚科鸿禹电子有限公司 | Pin mapping method and system |
| CN105701317A (en) * | 2016-03-01 | 2016-06-22 | 上海斐讯数据通信技术有限公司 | Method and system for correcting signal missing in schematic diagram designing |
| CN107506340A (en) * | 2017-08-11 | 2017-12-22 | 深圳市贝思科尔软件技术有限公司 | A kind of data transfer device and system |
| CN107515958A (en) * | 2016-06-16 | 2017-12-26 | 迈普通信技术股份有限公司 | Wiring inspection method and device |
| CN107644137A (en) * | 2017-09-26 | 2018-01-30 | 郑州云海信息技术有限公司 | A kind of mating interface defines inspection method and system |
| CN111859826A (en) * | 2020-07-22 | 2020-10-30 | 深圳市一博科技股份有限公司 | Method and tool for converting PROTEL netlist into ALLEGRO text |
| CN113688595A (en) * | 2020-05-19 | 2021-11-23 | 上海复旦微电子集团股份有限公司 | System-in-package circuit schematic diagram design method and device and readable storage medium |
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| US5051938A (en) * | 1989-06-23 | 1991-09-24 | Hyduke Stanley M | Simulation of selected logic circuit designs |
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| US6751744B1 (en) * | 1999-12-30 | 2004-06-15 | International Business Machines Corporation | Method of integrated circuit design checking using progressive individual network analysis |
| CN1435695A (en) * | 2002-02-01 | 2003-08-13 | 华为技术有限公司 | Method for testing circuit board interconnction line based on boundary scanning device |
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| CN102323964B (en) * | 2011-08-16 | 2014-06-25 | 北京芯愿景软件技术有限公司 | Digital circuit net list data processing method |
| CN103020339A (en) * | 2012-11-29 | 2013-04-03 | 王志欣 | Method for implementing combined automobile circuit diagrams |
| CN103745050A (en) * | 2013-12-27 | 2014-04-23 | 北京亚科鸿禹电子有限公司 | Pin mapping method and system |
| CN103745050B (en) * | 2013-12-27 | 2016-09-14 | 北京亚科鸿禹电子有限公司 | A kind of pin mapping method and system |
| CN105701317A (en) * | 2016-03-01 | 2016-06-22 | 上海斐讯数据通信技术有限公司 | Method and system for correcting signal missing in schematic diagram designing |
| CN107515958A (en) * | 2016-06-16 | 2017-12-26 | 迈普通信技术股份有限公司 | Wiring inspection method and device |
| CN107506340A (en) * | 2017-08-11 | 2017-12-22 | 深圳市贝思科尔软件技术有限公司 | A kind of data transfer device and system |
| CN107644137A (en) * | 2017-09-26 | 2018-01-30 | 郑州云海信息技术有限公司 | A kind of mating interface defines inspection method and system |
| CN113688595A (en) * | 2020-05-19 | 2021-11-23 | 上海复旦微电子集团股份有限公司 | System-in-package circuit schematic diagram design method and device and readable storage medium |
| CN113688595B (en) * | 2020-05-19 | 2023-08-18 | 上海复旦微电子集团股份有限公司 | System-in-package circuit schematic design method and device, and readable storage medium |
| CN111859826A (en) * | 2020-07-22 | 2020-10-30 | 深圳市一博科技股份有限公司 | Method and tool for converting PROTEL netlist into ALLEGRO text |
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