CN1534509A - Flash memory calculating method possessing quick and preventing improper operation function and its control system - Google Patents
Flash memory calculating method possessing quick and preventing improper operation function and its control system Download PDFInfo
- Publication number
- CN1534509A CN1534509A CNA031214363A CN03121436A CN1534509A CN 1534509 A CN1534509 A CN 1534509A CN A031214363 A CNA031214363 A CN A031214363A CN 03121436 A CN03121436 A CN 03121436A CN 1534509 A CN1534509 A CN 1534509A
- Authority
- CN
- China
- Prior art keywords
- data
- mapping table
- physical blocks
- flash memory
- algorithm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Memory System (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
A flash memory algorithm able to quickly create a map table and prevent the data error or disorder caused by abnormal power down and its control system are disclosed. A map table between logic section address and physical section address is stored in the section page of memory and protected by ECC data. When computer host is started, the data of map table is directly transferred to a latch of controller for reading it by said controller. When the data is disordered because of abnormal power down, it can be restored by reading it from said section page.
Description
Technical field
The invention relates to a kind of fast flash memory bank algorithm, refer to a kind of fast flash memory bank algorithm and control system thereof that has run-up table soon and prevent the undesired outage data entanglement of deriving especially.
Background technology
IT industry's development is at a tremendous pace, is subjected to CPU speed to reach the influence that IA product rises more and more soon, and the data storage device of high-speed transfer (memory body) also will be played the part of very important role.And in various data storage devices, because fast flash memory bank has non-volatile and is easy to change the characteristic of data access and expected by the user.
Press, shown in Figure 1A, be the organigram of physical data stocking system; At least one data storage device is (as Smart Media memory card, various fast flash memory banks such as Memory Stick memory card) 11～19 mainly is to be connected with a host computer 29 by a control device 20 (certainly, this control device 20 also can in be built in the subsystem of host computer 29), include a microprocessor 25 in this control device 20, it can meet PCMCIA by one, IDE, ATA, MMC, SD, the main frame interfacial level controller 24 of Compact Flash or its combined type specification agreement and interconnecting, an end of microprocessor 25 with host computer 29 then can via one store control logic circuit 26 with line in this data storage device 11～19; Microprocessor 25 also can connect a working area controller 22, and these working area controller 22 may command host computers 29 are desired the access data and are temporary in (first working storage 211, second working storage 213 and the N working storage 219) in the data storage district 21.In addition, line is in microprocessor 25, temporary memory controller 22 and storage control logic circuit 26 respectively for 23 of ECC logical circuits, and it is controlled by microprocessor 25 and gives corresponding error correcting code ECC data to the data magnetic region of desiring access.Again, microprocessor 25 can connect a search listing (Lookup Table) 255, and this search listing 255 can be in order to record logical blocks address (L
0～L
M+1) and all physical blocks address data value (PDA) of each data storage device 11 corresponding with it.
See also Figure 1B, search tabulation 255 employed memory bodys, mainly be to be access unit as random access memory (RAM), and be divided into a plurality of characters address (logical blocks address) L with character (WORD)
0, L
1..., L
m, L
M+1..., include in each logical blocks address and writing down relative shadow to memory body physical blocks address data value PBA (B
3, B
2..., B
M+1, B
m...).Fast flash memory bank 11 mainly is to be that access unit divides and is slit into a plurality of physical blocks address B with block (block)
0～B
n, each physical blocks address B
0～B
XPhysical blocks in (Data
0～Data
n) all include the plurality of blocks paging, and each paging is equivalent to a minimum storage element magnetic region (sector) of host side, can be equipped with the error correcting code hurdle ECC (E of each corresponding paging in the record block after each paging again
0～E
nError-correctingcode), reach the corresponding logical blocks (L of record
2, L
3, L
1.., L
M+1) logical blocks address hurdle LBA, be corresponding relation in the PDA hurdle of wherein searching tabulation 255 and the LBA hurdle of memory body 11, memory body data physical blocks B for example
0Interior stored data Data
0The logical bit address data value be the magnetic region L that point to search in the tabulation 255
2So, in its LBA hurdle, promptly log on as L
2(even also will store after the outage of this data and do not disappear), and search 255 the magnetic region L of tabulating
2The PBA hurdle promptly login and be oriented to B
0(this data is promptly given disappearance after outage), shown in the solid line double-head arrow, the rest may be inferred, shown in Figure 1B.
When system boot, the PBA hurdle of search listing 255 is not exist, microprocessor 25 will scan each the physical blocks address and the block logical bit address data value LBA of fast flash memory bank 11～19, and corresponding relation is inserted among the physical blocks address hurdle PBA of search listing 255, thus to set up complete search listing 255 according to the logical blocks address.Only, the operating type of search listing is set up in this kind scanning again, the not only inconvenient and waste activity duration.
Again, because the structure of fast flash memory bank 11 makes so, it is erased or during the access data is is unit with block 5, thus when the physical blocks correction is changed (as B
2), must change block B to desire
2The interior data Data that has originally stored
2Elder generation's unloading is available but do not store the clean physical blocks (B of one of data as yet in one
M+1) in, and at this physical blocks B
M+1After the LBA hurdle in login logical bit address L1, afterwards and desire is changed block B
2Interior data Data
2Erase become a clean block or the record do not use.Only, if work as clean block (as B
M+1) finished the data unloading and inserted logical bit address data value program, but desire change block B
2Do not finish as yet when erasing action, taking place as sudden power or, and, two data blocks B may arranged in starting shooting again and microprocessor 25 when scanning each memory body 11 each physical blocks logical bit address documentor once more when undesired shutdown situations such as machines
2And B
M+1All login logical blocks address value for L1 and point to same corresponding search 255 address (shown in dashed double) of tabulating, some block and connectionless situation perhaps may appear, so not only cause the mistake of data to link easily, even the damage of the data of formation.
Therefore how to use another kind of more novel fast flash memory bank mapping table and constructing method thereof, not only can be directly when system boot and set up mapping table fast, and can prevent upset operation situations such as various bursts or outage again, with the accuracy of guaranteeing that data links, be not to use for a long time the person eagerly to look forward to and difficulty place that desire row of the present invention solves always, and the inventor produces product research based on engaging in information for many years, exploitation, and the practical experience of selling, it is the idea of thinking and improveing, poor its people's professional knowledge, through design in many ways, inquire into, and after studying sample and improvement many times, can create a kind of fast flash memory bank algorithm and control system thereof that has fast and prevent improper operation effect of the present invention eventually.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of fast flash memory bank algorithm and control system thereof that has fast and prevent improper operation effect, it mainly is to utilize the paging of a physical blocks to store the mapping table data, switch fast in the working storage and when system boot, directly from the block paging, be reproduced in, and need not microprocessor utilization scanning formula each memory body physical blocks is carried out the scanning of logical bit address data, so the activity duration that not only can simplify microprocessor, and also can significantly save the activity duration person.
Secondary objective of the present invention is to provide a kind of fast flash memory bank algorithm and control system thereof that has fast and prevent improper operation effect, can put down in writing the mapping table data in its memory body physical blocks paging, can avoid thus because upset operation causes the sorry of the undesired binding of data down.
Another purpose of the present invention is to provide a kind of fast flash memory bank algorithm and control system thereof that has fast and prevent improper operation effect, and its mapping table data can be by the protection of one group of ECC data, to improve the correctness of its data.
Another purpose of the present invention is to provide a kind of fast flash memory bank algorithm and control system thereof that has fast and prevent improper operation effect, it can be with all memory body number of blocks according to working storage or block paging memory body capacity and be divided into a plurality of segment identifiers, each segment identifier all has a corresponding working storage mapping table to set up the data mapping relations, when changing, the block data only can have influence on relevant mapping table data, therefore can effectively reduce the change activity duration of mapping table, and can effectively reduce data mistake link condition and send out the survivor.
Another purpose of the present invention is to provide a kind of fast flash memory bank algorithm and control system thereof that has fast and prevent improper operation effect, all physical blocks can be divided into a plurality of subregions, so that the size of mapping table is reduced to what a magnetic region (256Words) just, so that this mapping table also can ought be deposited in the fast flash memory bank for physical data, therefore can significantly save the memory body capacity of login block entity address data, and applicable in the stocking system that links a plurality of fast flash memory banks.
The object of the present invention is achieved like this: a kind of control system of fast flash memory bank, it mainly is to be connected to a host computer and at least one fast flash memory bank by a control device, be provided with a plurality of working storages in this control device, and the part working storage can be in order to be written into the mapping table data of logical blocks address and physical blocks corresponding with it address data value, and this mapping table data can be stored in the part physical blocks of a fast flash memory bank.
Physical blocks quantity in this fast flash memory bank is a plurality of subregion group for the storage volume that cooperates working storage can be segmented into.
Each subregion group all has the branch page map table data of a correspondence, and divides the page map table data can be stored in the paging of corresponding memory body physical blocks.
The storage volume of this mapping table is to select one of them of 256bytes and 512bytes.
The memory body physical blocks quantity that one mapping table can shine upon be can select 128 and 256 one of them.
A character number in this mapping table can be logined and shine upon a corresponding memory body block.
This working storage that can login mapping table can be a data storage device.
This memory body physical blocks that stores the mapping table data is provided with a special marking.
The algorithm of a kind of fast flash memory bank of the present invention, it mainly is to store a mapping table data that records each physical blocks address data value of memory body and corresponding logical blocks address with it in a fast flash memory bank, when system boot, this mapping table data directly can be reproduced in the working storage of this control device by the control of a control device.
Above-mentioned algorithm still includes the following step: when desire is changed the stored data of a physical blocks meat, at first can with in this desire change block not need more changed information to be reproduced in one available but do not store as yet in the clean physical blocks of other data, erase afterwards and with all data that desire is changed in the block, and this related entities block address data will directly be changed in the mapping table of working storage, and the mapping table data storage after after a while this being changed is in another physical blocks of memory body.
Above-mentioned algorithm still can include the following step: after the data in the desire change block has been erased, when starting shooting again if take place the situation of upset operation to take place, the mapping table data that control device will be stored in the memory body physical blocks before will be reproduced in the working storage.
Whether above-mentioned algorithm still includes the following step: come identification to have the situation of upset operation to take place by the ECC data of the physical blocks that stores the mapping table data.
Above-mentioned algorithm still includes the following step: recording the relevant mapping table data that links address of each physical blocks of memory body is to be stored in the physical blocks part paging of memory body, and the address of this part paging is to include a special marking to be beneficial to system can to search this minute page map table data and being reproduced in the working storage immediately when start.
Physical blocks quantity in this fast flash memory bank is a plurality of segmentation group for the storage volume that cooperates working storage can be segmented into.
The physical blocks of each segment identifier all have one and corresponding partition map table.
A character number in this mapping table can write down and shine upon a corresponding memory body block.
The memory body physical blocks quantity that one mapping table can shine upon be can select 128 and 256 one of them.
Mapping table data after the change also can directly be stored in the mapping table data physical blocks paging that is fixed.
Description of drawings
Figure 1A is the organigram of general fast flash memory bank stocking system;
Figure 1B is a mapping table organigram of commonly using fast flash memory bank;
Fig. 2 A is the organigram of fast flash memory bank stocking system of the present invention;
Fig. 2 B is the mapping table organigram of fast flash memory bank of the present invention;
Fig. 2 C is the organigram of fast flash memory bank physical blocks part of the present invention paging;
Fig. 3 is the action flow chart of fast flash memory bank of the present invention when the access data: and
Action flow chart when Fig. 4 is a construction mapping table of the present invention.
The figure number explanation:
11～19 fast flash memory banks, 20 control device
21 data working areas, 211 first working storages
213 second working storages, 219 N working storages
22 working area controllers, 23 ECC logical circuits
24 main frame interfacial level controllers, 25 microprocessors
26 store control logic circuit 29 host computers
255 mapping tables, 31～39 fast flash memory banks
311 part pagings, 40 control device
41 data working areas, 411 first working storages
413 second working storages, 419 mapping tables
42 working area controllers, 43 ECC logical circuits
44 main frame interfacial level controllers, 45 microprocessors
46 store control logic circuit 49 host computers
Embodiment
Seeing also Fig. 2 A, is the organigram of fast flash memory bank stocking system of the present invention; At least one fast flash memory bank 31～39 mainly is to be connected with a host computer 49 by a control device 40 (certainly, this control device 40 also can in be built in the subsystem of host computer 49), include a microprocessor 45 in this control device 40, it can meet the main frame interfacial level controller 44 of PCMCIA, IDE, ATA, MMC, SD, Compact Flash or the agreement of its combined type specification and interconnect with host computer 49 by one, an end of microprocessor 45 then can via one store control logic circuit 46 with line in this data storage device 31～39; Microprocessor 45 also can connect a working area controller 42, and these working area controller 42 may command host computers 49 are desired the access data and temporarily are stored in (first working storage 411, second working storage 413 and the N working storage 419) in the data storage district 41.In addition, line is in microprocessor 45, temporary memory controller 42 and storage control logic circuit 46 respectively for 43 of ECC logical circuits, and it is controlled by microprocessor 45 and gives corresponding error correcting code ECC data to the data magnetic region of desiring access.Wherein, the part working storage 419 in data storage district 41 can be used to as the mapping table 419 (mappingtable) that stores each memory body physical blocks related entities block address data value PBA of record.
See also Fig. 2 B, in embodiments of the present invention, its mapping table 419 that records corresponding memory body physical blocks address data value PBA is to login in the part working storage 419 that control device adds, and is collocation working storage 419 or physical blocks (B
0) paging (page) memory storage capacity 256bytes or each character of 512bytes (also being exactly 128 or 256 character numbers) mapping table 419 count W
0, W
1... W
mAll include and represent a corresponding block B
0, B
1... B
The address value of mSo mapping table 419 can corresponding 128 or less than 256 memory body physical blocks (B
0), so the total number of memory body physical blocks can be divided into a plurality of subregion (Seg of group in good time
0～Seg
n), wherein each will be limited in (or within 128) within 256 by the contained block of the segemnet of cutting (Block) number, all have in each segement certainly a special record map updating (Mapping update) special reservation block (as the * number expression of Fig. 2 B or Fig. 2 C shown in).
Each segment identifier Segement all has the special reservation block (this mapping block first make to build tabular value be to set up) of a corresponding map updating (Mapping update) in order to set up the data mapping relations when system initialization, when host computer 49 is desired the accessing file data, the LBA value that the microprocessor 45 of control device 40 will be imported into by host computer 49 is divided by physical blocks numerical value contained in the subregion, the magnetic region that includes divided by block (sector) number is to obtain the mapping table in the required segement segmentation of reading into again, and this partition map table is stored in mapping working storage 419 by the latest update paging transfer of the special reservation block of map updating (Mapping update), thus to make things convenient for system to find the physical blocks address of the required mapping of this LBA.Again, each segment identifier Segement all has the special reservation block of a corresponding map updating (Mapping update) to store the data mapping relations of up-to-date foundation, when block mapping data changes, only can upgrade this partition map and upgrade the up-to-date paging of (Mapping update) special reservation block, therefore the change activity duration of whole mapping table can be effectively reduced, and the generation of data mistake link condition can be effectively reduced.
Because mapping table 419 of the present invention itself is one and can stores data, so when the login data in the mapping table 419 is had some change, can be in the physical blocks part paging 311 of the special reservation block of a map updating (Mapping update) with this data storage, and this part paging 311 is the not mapped data blocks that is marked with special marking " * ", and wherein this part paging 311 is divided into a plurality of subregion page or leaf MT
0, MT
1, MT
2...., MT
m, wherein m is the branch number of pages that Block includes, and sees also Fig. 2 C, when the login data in the mapping table 419 is had some change, and can be with the MT of this data storage in the entity paging 311 of the special reservation block of a map updating (Mapping update)
nIn, when upgrading once again, new mapping relations will be stored in MT
N+1In, during every increase new login data, new renewal is shone upon down to divide to buy and is write, begin to upgrade by paging O again up to writing completely then again the special reservation block of this map updating of Erase (Mapping update), can be reproduced in the data of a working storage 419 with as next booting computer the time immediately, therefore the present invention need not to rebulid the search tabulation as needing by logical bit address (as the L value among Figure 1B) data of host computer 49 each block of scanning with stocking system, therefore not only can omit the dynamic program of doing of host computer 49, also can significantly save to make up and search the tabulation time.
Certainly because of the present invention focusing in the paging that the mapping table data can be stored in a physical blocks, with convenient can be directly when the system boot and be reproduced in rapidly in the mapping table memory body.
Moreover, see also Fig. 3, be to be fast flash memory bank of the present invention action flow chart during the construction mapping table under writing (or reading) operation: as shown in the figure, its key step is to include:
After step 301, host computer or control device became start or power supply, total system became armed state;
Step 305 is compared this by the paging that has write in the old block and the address that writes is detected is write instruction and whether be the situation of overriding, and does not then directly write in the old block and need not upgrade mapping relations and be back to armed state if having; If then execution in step 305:
Step 307 will before be stored in the old block and the data that is not modified is moved in this clean block;
Step 310 is with next paging in the special reservation block of map updating (Mapping update) of the mapping table data updating of working storage, can conveniently search and reprint the data of mapping table as next booting computer timed unit.
At last, seeing also Fig. 4, is to be the action flow chart of system of the present invention when wanting the construction mapping table; As shown in the figure:
Step 404 is represented the generation of upset operation situation, and the reply relation of a mapping table in the necessary backtracking is shone upon paging in memory body as long as read recently last one in the special reservation block of map updating (Mapping update) again;
Step 405 continues the executive system action.
In sum, the invention relates to a kind of fast flash memory bank algorithm, refer to a kind of fast flash memory bank algorithm and control system thereof that has run-up table soon and prevent the undesired outage data entanglement of deriving especially when knowing.So the present invention one is rich in novelty, progressive, and can utilize effect person for industry, should meet the application for a patent for invention important document undoubtedly, the whence proposes application for a patent for invention in accordance with the law, prays hook office and grants quasi patent early, and most sense is prayed.
Only the above person only is a preferred embodiment of the present invention, is not to be used for limiting scope of the invention process.Be that all equalizations of doing according to the described shape of the present patent application claim, structure, feature and spirit change and modification, all should be included in the claim of the present invention.
Claims (18)
1, a kind of control system of fast flash memory bank, it mainly is to be connected to a host computer and at least one fast flash memory bank by a control device, it is characterized in that, be provided with a plurality of working storages in this control device, and the part working storage can be in order to be written into the mapping table data of logical blocks address and physical blocks corresponding with it address data value, and this mapping table data can be stored in the part physical blocks of a fast flash memory bank.
2, control system as claimed in claim 1 is characterized in that, the physical blocks quantity in this fast flash memory bank is a plurality of subregion group for the storage volume that cooperates working storage can be segmented into.
3, control system as claimed in claim 2 is characterized in that, each subregion group all has the branch page map table data of a correspondence, and divides the page map table data can be stored in the paging of corresponding memory body physical blocks.
4, control system as claimed in claim 1 is characterized in that, the storage volume of this mapping table is to select one of them of 256bytes and 512bytes.
5, control system as claimed in claim 4 is characterized in that, the memory body physical blocks quantity that a mapping table can shine upon be can select 128 and 256 one of them.
6, control system as claimed in claim 1 is characterized in that, a character number in this mapping table can be logined and shine upon a corresponding memory body block.
7, control system as claimed in claim 1 is characterized in that, this working storage that can login mapping table can be a data storage device.
8, control system as claimed in claim 1 is characterized in that, this memory body physical blocks that stores the mapping table data is provided with a special marking.
9, a kind of algorithm of fast flash memory bank, it mainly is to store a mapping table data that records each physical blocks address data value of memory body and corresponding logical blocks address with it in a fast flash memory bank, when system boot, this mapping table data directly can be reproduced in the working storage of this control device by the control of a control device.
10, algorithm as claimed in claim 9 is characterized in that, still includes the following step:
When desire is changed the stored data of a physical blocks meat, at first can with in this desire change block not need more changed information to be reproduced in one available but do not store as yet in the clean physical blocks of other data, erase afterwards and with all data that desire is changed in the block, and this related entities block address data will directly be changed in the mapping table of working storage, and the mapping table data storage after after a while this being changed is in another physical blocks of memory body.
11, algorithm as claimed in claim 10, it is characterized in that, still include the following step: after the data in the desire change block has been erased, when starting shooting again if take place the situation of upset operation to take place, the mapping table data that control device will be stored in the memory body physical blocks before will be reproduced in the working storage.
12, algorithm as claimed in claim 9 is characterized in that, still includes the following step:
Come identification whether to have the situation of upset operation to take place by the ECC data of the physical blocks that stores the mapping table data.
13, algorithm as claimed in claim 9 is characterized in that, still includes the following step:
Recording the relevant mapping table data that links address of each physical blocks of memory body is to be stored in the physical blocks part paging of memory body, and the address of this part paging is to include a special marking to be beneficial to system can to search this minute page map table data and being reproduced in the working storage immediately when start.
14, algorithm as claimed in claim 9 is characterized in that, the physical blocks quantity in this fast flash memory bank is a plurality of segmentation group for the storage volume that cooperates working storage can be segmented into.
15, algorithm as claimed in claim 13 is characterized in that, the physical blocks of each segment identifier all have one and corresponding partition map table.
16, algorithm as claimed in claim 9 is characterized in that, a character number in this mapping table can write down and shine upon a corresponding memory body block.
17, algorithm as claimed in claim 9 is characterized in that, the memory body physical blocks quantity that a mapping table can shine upon be can select 128 and 256 one of them.
18, algorithm as claimed in claim 9 is characterized in that, the mapping table data after the change also can directly be stored in the mapping table data physical blocks paging that is fixed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031214363A CN1534509A (en) | 2003-03-27 | 2003-03-27 | Flash memory calculating method possessing quick and preventing improper operation function and its control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA031214363A CN1534509A (en) | 2003-03-27 | 2003-03-27 | Flash memory calculating method possessing quick and preventing improper operation function and its control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1534509A true CN1534509A (en) | 2004-10-06 |
Family
ID=34285702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA031214363A Pending CN1534509A (en) | 2003-03-27 | 2003-03-27 | Flash memory calculating method possessing quick and preventing improper operation function and its control system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1534509A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100353337C (en) * | 2005-06-01 | 2007-12-05 | 旺玖科技股份有限公司 | Flash memory system |
| CN100421462C (en) * | 2004-12-23 | 2008-09-24 | 普立尔科技股份有限公司 | Method for storing digital video and audio data |
| CN101364206B (en) * | 2005-06-01 | 2010-06-23 | 旺玖科技股份有限公司 | Flash memory system |
| CN104679672A (en) * | 2013-11-27 | 2015-06-03 | 慧荣科技股份有限公司 | Data storage device and flash memory control method |
| CN105389266A (en) * | 2015-10-16 | 2016-03-09 | 联想(北京)有限公司 | Data management method and apparatus |
| US9329992B2 (en) | 2013-12-04 | 2016-05-03 | Silicon Motion, Inc. | Data storage device and flash memory control method |
| CN107015913A (en) * | 2016-01-28 | 2017-08-04 | 瑞昱半导体股份有限公司 | Memory device and mapping table ensuring method |
| CN109521944A (en) * | 2017-09-18 | 2019-03-26 | 慧荣科技股份有限公司 | data storage device and data storage method |
| US10866850B2 (en) | 2016-01-21 | 2020-12-15 | Raymx Microelectronics Corp. | Memory device for guaranteeing a mapping table and method thereof |
-
2003
- 2003-03-27 CN CNA031214363A patent/CN1534509A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100421462C (en) * | 2004-12-23 | 2008-09-24 | 普立尔科技股份有限公司 | Method for storing digital video and audio data |
| CN100353337C (en) * | 2005-06-01 | 2007-12-05 | 旺玖科技股份有限公司 | Flash memory system |
| CN101364206B (en) * | 2005-06-01 | 2010-06-23 | 旺玖科技股份有限公司 | Flash memory system |
| CN104679672A (en) * | 2013-11-27 | 2015-06-03 | 慧荣科技股份有限公司 | Data storage device and flash memory control method |
| US9218891B2 (en) | 2013-11-27 | 2015-12-22 | Silicon Motion, Inc. | Data storage device and flash memory control method |
| CN104679672B (en) * | 2013-11-27 | 2018-02-23 | 慧荣科技股份有限公司 | Data memory device and method for controlling flash memory |
| US9329992B2 (en) | 2013-12-04 | 2016-05-03 | Silicon Motion, Inc. | Data storage device and flash memory control method |
| CN105389266A (en) * | 2015-10-16 | 2016-03-09 | 联想(北京)有限公司 | Data management method and apparatus |
| US10866850B2 (en) | 2016-01-21 | 2020-12-15 | Raymx Microelectronics Corp. | Memory device for guaranteeing a mapping table and method thereof |
| CN107015913A (en) * | 2016-01-28 | 2017-08-04 | 瑞昱半导体股份有限公司 | Memory device and mapping table ensuring method |
| CN109521944A (en) * | 2017-09-18 | 2019-03-26 | 慧荣科技股份有限公司 | data storage device and data storage method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110908925B (en) | High-efficiency garbage collection method, data storage device and controller thereof | |
| US8214578B2 (en) | Method of storing data into flash memory according to usage patterns of addresses and data storage system using the same | |
| KR20120129895A (en) | Erase command caching to improve erase performance on flash memory | |
| US20130060991A1 (en) | Solid state drive and garbage collection control method thereof | |
| WO1999030239A1 (en) | Memory and access method | |
| CN1959672A (en) | Optimized startup verification of file system integrity | |
| WO2006009322A2 (en) | Memory card, nonvolatile semiconductor memory, and method of controlling semiconductor memory | |
| US11204864B2 (en) | Data storage devices and data processing methods for improving the accessing performance of the data storage devices | |
| US9454475B2 (en) | Control device, storage device, and data writing method | |
| US10606744B2 (en) | Method for accessing flash memory module and associated flash memory controller and electronic device | |
| US10025706B2 (en) | Control device, storage device, and storage control method | |
| CN1447243A (en) | Calculation method executed in quick flash memory fast and not caused abnormal power breakdown as well as its control system | |
| CN111966281A (en) | Data storage device and data processing method | |
| CN1534509A (en) | Flash memory calculating method possessing quick and preventing improper operation function and its control system | |
| US11216381B2 (en) | Data storage devices and data processing methods | |
| CN112099731B (en) | Data storage device and data processing method | |
| JP4888333B2 (en) | Flash disk device | |
| JP2008299455A (en) | Data storage device and data management method | |
| TWI695264B (en) | A data storage device and a data processing method | |
| US11112976B2 (en) | Data storage device that stores multiple values corresponding to multiple keys in a page | |
| TWI697779B (en) | A data storage device and a data processing method | |
| US20240103733A1 (en) | Data processing method for efficiently processing data stored in the memory device by splitting data flow and the associated data storage device | |
| TW202414222A (en) | Data processing method and the associated data storage device | |
| CN1485860A (en) | Non-volatility memory access system and its cycling usage method of access space | |
| TW202414223A (en) | Data processing method and the associated data storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |