CN1499590A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN1499590A CN1499590A CNA2003101045976A CN200310104597A CN1499590A CN 1499590 A CN1499590 A CN 1499590A CN A2003101045976 A CNA2003101045976 A CN A2003101045976A CN 200310104597 A CN200310104597 A CN 200310104597A CN 1499590 A CN1499590 A CN 1499590A
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Abstract
一种半导体器件制造方法,其中包括如下步骤:制备在一个表面上具有布线图案的布线基片;通过倒装片焊接把在一个表面上具有预定元件和一个连接端的电子芯片的连接端接合到该布线基片的布线图案上;在该布线基片上形成第一绝缘膜,该第一绝缘膜第一绝缘膜具有覆盖该电子芯片的膜厚或者暴露该电子芯片的至少另一个表面的膜厚;以及通过研磨该第一绝缘膜和该电子芯片的另一个表面而减小该电子芯片的厚度。
Description
技术领域
本发明涉及一种半导体器件及其制造方法,更加具体来说,涉及一种三维封装半导体芯片等等的半导体器件及其制造方法。
背景技术
作为实现多媒体器件的一种关键技术的LSI技术的发展稳定地向着数据传输的更高速度和更大容量方向发展。由此,作为LSI和电子器件之间的接口的更高密度的封装技术也被发展。
响应更高密度的需求,多个半导体芯片被三维地叠加在基片上并且被封装的多芯片封装(半导体器件)技术已经被开发。作为一个例子,在专利申请公告(特开平)2001-196525(专利文献1)、专利申请公告(特开平)2001-177045(专利文献2)、以及专利申请公告(特开平)2000-323645(专利文献3)中给出多个半导体芯片被叠加在布线基片上的结构。
在最近几年,在这种多芯片封装中,需要减小整体厚度。因此,各个半导体芯片必须被形成为尽可能薄并且被封装。
如给出减薄的半导体芯片的相关技术1中所述,首先例如在第一保护带接合到该半导体晶片的形成有预定元件的元件形成表面上的状态下,通过研磨器研磨该半导体芯片的背表面,把半导体晶片的厚度减小到100μm或更小。然后,该半导体晶片的研磨表面被接合到第二保护带上,然后从该半导体晶片上剥离第一保护带。然后,通过对在第二保护带上的半导体晶片进行切割而获得各个减薄的半导体芯片。
并且,如相关技术2所述,首先把一个刚性玻璃基片接合到该半导体晶片的元件形成表面上,然后通过该研磨器研磨该半导体晶片的背表面而减小该半导体晶片的厚度。然后,把该半导体晶片从玻璃基片上剥离,然后通过对该半导体晶片进行切割而获得各个减薄的半导体芯片。
另外,如相关技术3所述,首先通过凸块等等电连接分别形成有预定元件的两个半导体晶片的元件形成表面,然后通过研磨器研磨该半导体晶片的背表面而减小一个半导体晶片的厚度。然后,通过对两个接合的半导体晶片进行切割而获得各个叠加的半导体芯片。
在上述相关技术1中,保护带没有足够的刚性。因此,当在该半导体晶片接合到第一保护带的状态下运送该减薄的半导体晶片时,或者由于在该半导体晶片上的钝化膜等等的剩余应力造成半导体晶片的弯曲时,该半导体晶片会破裂。因此,在一些情况中,不可能把该半导体晶片运送到储存盒子中。
并且,在上述相关技术2中,由于该刚性玻璃基片被用作为支承体,可以克服在相关技术1中的晶片运送中所造成的缺点。但是在该半导体晶片接合到该玻璃基片的状态下,非常难以从该玻璃基片上剥离减薄的半导体晶片而不使其破裂。
另外,在上述相关技术3中,由于任何一个半导体晶片还被用作为支承基片,因此不需要从该支承基片上剥离该半导体晶片。但是,由于整个半导体晶片的芯片被分为各个块,然后被封装,因此有缺陷的芯片可能与叠加的半导体芯片相混合,因此半导体器件制造的成品率降低。
另外,在上述参考文献1至3中,它们仅仅给出该半导体芯片被三维地叠加在该基片上。但是,没有考虑到这样的结构,即,例如应当通过叠加厚度分别为大约150μm或更小的减薄半导体芯片而减小整个半导体器件的厚度。
发明内容
本发明的一个目的是提供一种半导体器件制造方法,其能够在一个布线基片上封装一个薄的电子芯片(例如,150μm或更小),而不造成任何缺陷,以及提供一种半导体器件。
本发明提供一种半导体器件制造方法,其中包括如下步骤:在一个表面上制备具有布线图案的布线基片;通过倒装片焊接把在一个表面上具有预定元件和一个连接端的电子芯片的连接端接合到该布线基片的布线图案上;在该布线基片上形成第一绝缘膜,其具有覆盖该电子芯片的膜厚或者暴露该电子芯片的至少另一个表面的膜厚;以及通过研磨该电子芯片的另一个表面和该第一绝缘膜而减小该电子芯片的厚度。
在本发明中,被分为各个块的无缺陷电子芯片被通过倒装片安装方法接合到该刚性布线基片,然后该电子芯片被该第一绝缘膜覆盖并且被支承,然后通过研磨该第一绝缘膜和电子芯片而减小该电子芯片的厚度。否则,该电子芯片不被第一绝缘膜良好地覆盖,但是第一绝缘膜可以被形成为具有这样的膜厚,以暴露其他表面的一部分(要被研磨的背表面)或者该电子芯片的侧表面,在减小该电子芯片的厚度的步骤中,可以通过研磨器研磨该电子芯片,或者可以通过研磨器研磨,然后通过CMP进行抛光。
如果执行该操作,则与在相关技术1和2中通过抛光附着到临时支承体的半导体晶片而减小其厚度的方法不同,不会造成该半导体晶片破裂的缺点。并且在本发明中,可以选择无缺陷的电子芯片并且安装到该布线基片上。因此,与在相关技术3中接合两个半导体晶片然后抛光一个半导体晶片以减小厚度的方法不同,本发明不可能把缺陷的电子芯片安装在布线基片上。
并且,在本发明中,被分为各个块的电子芯片被通过倒装片安装方法而接合到该布线基片,然后接地以减小厚度。因此,不需要处理难以处理的减薄的半导体芯片。
另外,该电子芯片被在其侧表面由绝缘膜所支承的状态下接地。因此,不可能在研磨步骤中破坏该电子芯片和布线基片之间的接合,因此可以避免该半导体器件制造的成品率降低。
在上述半导体器件制造方法中,在减小该电子芯片的厚度的步骤中,最好该电子芯片的抛光表面和该绝缘膜的上表面应当被平面化为几乎相同的高度。
可以通过研磨该半导体芯片和第一绝缘膜而使得该电子芯片的研磨表面和该第一绝缘膜的上表面被平面化,以形成一个几乎相同的表面。因此,不但当其他电子芯片被通过倒装片焊接接合到该电子芯片上时该接合的可靠性增加,而且可以接合这些电子芯片而不受到该凸块的影响。结果,可以进一步减小叠加多个半导体芯片的半导体器件的厚度。
按照这种方式,可以容易地把减薄的电子芯片(例如,其厚度为150μm或更小)安装在该布线基片上,而产生任何缺陷。
并且,在本发明的一个优选模式中,在减小该电子芯片的厚度的步骤之后,该半导体器件制造方法进一步包括如下步骤:在该电子芯片中形成具有一个深度的通孔,其从在该电子芯片的另一个表面上的预定部分到达该电子芯片的一个表面上的连接端;在该电子芯片和第一绝缘膜上形成第二绝缘膜;通过蚀刻包含对应于该通孔的一部分的第二绝缘膜的预定部分,形成与该通孔连通的一个布线凹槽;以及通过在该通孔和布线凹槽中填充一种导电膜而形成通过该通孔连接到该连接端的导电膜图案。
相应地,通过形成在该电子芯片中的通孔连接到在一个表面侧上的连接端的导电膜图案被形成在该电子芯片的另一个表面(研磨表面)侧上。然后,覆盖电子芯片的连接端被通过倒装片焊接接合到该电子芯片上的导电膜图案上,然后该电子芯片被接地,并且上述步骤被重复执行,从而多个电子芯片被叠加和封装。按照这种方式,三维地叠加的多个电子芯片被通过贯穿它们的通孔相互连接。
因此,具有任何尺寸的多个半导体芯片可以被设置和叠加,而不受到它们的相互尺寸的限制。结果,可以扩大要被安装的半导体芯片的选择范围,因此可以提高设计上的容限。另外,与通过布线等等连接该半导体的情况不同,可以缩短布线长度,并且该半导体器件可以响应高频应用中的更高信号速度。
否则,该通孔不被在该电子芯片中打开,但是该通孔分别在该电子芯片附近在该绝缘膜中打开。因此,在该电子芯片的一个表面侧上的连接端可以被通过在该绝缘膜中的通孔电连接到该电子芯片的另一个表面侧上的导电膜图案。
附图说明
图1A至图1O为示出根据本发明第一实施例的半导体器件制造方法的截面视图;
图2A至图2E为示出在图1K和1L中的步骤的具体细节的截面视图;
图3A至3O为示出根据本发明第二实施例的半导体器件制造方法的截面视图;
图4A至图4C为示出根据本发明第三实施例的半导体器件制造方法的截面视图;
图5为示出根据本发明第四实施例的半导体器件制造方法的截面视图;
图6A至图6F为示出根据本发明第五实施例的半导体器件制造方法的截面视图;以及
图7A至图7G为示出根据本发明第六实施例的半导体器件制造方法的截面视图。
具体实施方式
下面将参照附图描述本发明的实施例。
(第一实施例)
图1A至图1O为示出根据本发明第一实施例的半导体器件制造方法的截面视图。图2A至图2E为示出在图1K和1L中的步骤的具体细节的截面视图。
在根据本发明第一实施例的半导体器件制造方法中,如图1A中所示,首先制备例如厚度为400μm的一个硅基片10。然后,如图1B中所示,一个光刻胶膜(为示出)被通过光刻方法在该硅基片10上构图,然后通过使用该光刻胶膜作为一个掩膜对该硅基片10进行干法蚀刻而形成具有3至5μm深度的布线凹槽。在此时,分别组合多个半导体芯片的区域被确定在该硅基片10上,并且同时形成用于形成一个对齐标记的凹陷10x。该凹陷10x可以分别形成在多个半导体芯片组合区域附近,或者可以形成在该硅基片10的外围区域中,
然后,如图1C中所示,通过光刻方法对该光刻胶膜(为示出)进行构图,以打开该布线凹槽10a的底表面的预定部分。然后,通过使用该光刻胶膜作为一个掩膜对该硅基片10进行干法蚀刻而形成从一个表面到达另一个表面的通孔10b。按照这种方式,该布线凹槽10a和通过该布线凹槽10a的通孔10b形成在该硅基片10上。
然后,如图1D中所示,例如氧化硅膜等等这样的无机绝缘膜12形成在硅基片10上,其上通过CVD方法而形成布线凹槽10a和通孔10b。相应地,布线凹槽10a和通孔10b的内表面以及硅基片10的上表面被无机绝缘膜12所覆盖。该无机绝缘膜12被形成为通过后处理使得埋在布线凹槽10a和通孔10b中的导体与硅基片10相绝缘。
然后,如图1D中类似地示出,例如氮化钛膜(TiN膜)、氮化钽膜(TaN膜)等等这样的阻挡膜14通过溅射方法或CVD方法而形成在无机绝缘膜12上。然后,由铜所制成的种子膜16通过溅射方法等等形成在阻挡膜14上。然后,填充该通孔10b和布线凹槽10a的具有一定膜厚的铜膜18通过使用阻挡膜14和种子膜16作为电镀电源层而形成。
然后,如图1E中所示,铜膜18、种子膜16和阻挡膜14通过CMP(化学机械抛光)方法而抛光,直到形成在硅基片10上的无机绝缘膜12被暴露。相应地,铜膜18、种子膜16和阻挡膜14被通过所谓的镶嵌方法埋在通孔10b和布线凹槽10a中,以形成填充在通孔10b中的导电插塞18b和连接到导电插塞18b。在此时,铜膜18、种子膜16以及阻挡膜14也被埋在凹陷10x中,用于上述对齐标记,因此一个对齐标记19被同时形成。
按照这种方式,导电插塞18b、布线图案18a等等根据需要形成在硅基片10上,从而获得布线基片11。
在这种情况中,在上述模式中,导电插塞18b和连接到导电插塞18b的布线图案18a通过使用镶嵌方法而形成。但是可以制备导电插塞填充在该通孔中的硅基片,然后可以通过所谓的添加处理或减小处理而形成连接到该导电插塞的铜布线,以形成该布线图案。
然后,如图1F中所示,制备半导体芯片20(电子芯片),其分别包括例如晶体管等等这样的预定元件(未示出)、连接焊盘21(连接端)和连接到一个表面上的连接焊盘的凸块23(连接端)。该半导体芯片20通过普通制造方法在该半导体晶片上形成预定元件之后切割为半导体晶片而形成为芯片,并且其厚度例如大约为500μm。并且,在此所制备的半导体芯片20是通过预定检验的无缺陷单元,并且作为缺陷单元的半导体芯片被排除。在这种情况中,半导体芯片20作为电子芯片的一个例子。可以采用例如电容器元件、电阻器等等这样的半导体芯片的各种电子芯片被提供在一个表面上的各种电子芯片。
然后,如图1F中所示,作为无缺陷单元的半导体芯片20的凸块23被通过倒装片焊接接合到布线基片11的布线图案18a。在此时,多个半导体芯片20被安装在该布线基片11的多个半导体芯片安装区域上,分别使其不形成元件的表面(在下文中称为背表面)分别指向上侧。作为倒装片焊接处理,例如,该焊锡凸块被用作为半导体芯片20的凸块23,并且半导体芯片20的凸块23和布线基片11的布线图案18a然后被焊锡焊接。否则,Au凸块被用作为半导体芯片20的凸块23,然后半导体芯片20的凸块23和布线基片11的布线图案18a可以通过各向异性导电材料(ACF)而接合。
然后,如图1G中所示,孔型树脂22被填充在布线基片11和半导体芯片20之间的空隙中。否则,在接合该半导体芯片20之前,一种绝缘树脂(NCF或NCP)可以被预先覆盖在包括布线基片11的布线图案18a的预定区域上,然后该倒装片焊接可以在该树脂被插入的状态下执行。
接着,如图1G类似地示出,用于覆盖半导体芯片20的第一绝缘膜24形成在半导体芯片20和布线基片11上。另外,如下文所述的第二实施例中所示,第一绝缘膜24可以形成为暴露半导体芯片20的背表面。
在本实施例中,作为第一绝缘膜24的一个例子,可以采用由选自包括环氧树脂、聚亚苯基醚树脂、苯酚树脂、氟树脂等等的热固树脂的材料所制成的树脂膜。首先,在50至1000Pa的真空度和50至160℃温度下,该树脂膜被叠加在半导体芯片20和布线基片11上。然后,通过在被设置为100℃的环境下在熔炉中执行10分钟的退火而固化该树脂膜,从而形成该树脂膜。最好,由于通过后处理而研磨作为第一绝缘膜24的树脂膜,因此应当采用在已经执行退火之后仍然具有刚性的树脂膜。
在这种情况中,除了叠加上述树脂膜的方法之外,可以通过旋涂方法或印刷方法形成作为第一绝缘膜24的树脂膜。并且除了作为第一绝缘膜24的树脂膜之外,可以采用通过CVD方法所形成的氧化硅膜、氮化硅膜等等。
按照这种方式,半导体芯片20进入它们被第一绝缘膜24所覆盖和支承的状态。
然后,如图1H中所示,通过该研磨器研磨第一绝缘膜24,以暴露半导体芯片20的背表面。然后,通过同时研磨该半导体芯片20和第一绝缘膜24而减薄该半导体芯片20。最好应当可以在多级中交换研磨进送速度的研磨器作为用于研磨的研磨器。
在该研磨步骤中,首先通过使用通过玻璃化(玻璃陶瓷)或者树脂接合(有机树脂)接合20至30μm的钻石颗粒而形成的研磨轮(研磨石)研磨该半导体芯片20的厚度到大约100μm。该研磨石主轴的转速被设置为大约3000至5000转/分,并且随着该半导体芯片20的厚度减小到更小,该研磨进送速度被减小到较低速度(例如,第一阶段(5至3μm/秒)、第二阶段(2至0.5μm/秒)、第三阶段(1至0.3μm/秒))。
然后,通过使用通过玻璃化(玻璃陶瓷)或者树脂接合(有机树脂)接合1至10μm的钻石颗粒而形成的研磨轮(研磨石)研磨该半导体芯片20的厚度减小到大约25μm而执行修整研磨。该研磨石主轴的转速被设置为大约3000至5000转/分,并且随着该半导体芯片20的厚度减小到更小,该研磨进送速度被减小到较低速度(例如,第一阶段(1至0.5μm/秒)、第二阶段(0.5至0.2μm/秒)、第三阶段(0.2至0.05μm/秒))。
在这种情况中,在通过研磨器研磨半导体芯片20和树脂膜中,由于研磨碎片造成研磨石的堵塞,然后有时出现半导体芯片20被烧毁的情况。因此,如上文所述,需要选择例如玻璃陶瓷或树脂这样硬而脆的材料作为研磨石的接合剂。
如果采用具有这种接合剂的研磨石,则机件(研磨体)变得难以与该接合剂相接触。因此,出现研磨碎片滴落并且在该研磨石的钻石造成堵塞之前暴露出新的钻石这样的效果(钻石的自生效果)。结果,可以避免研磨石的堵塞。并且,最好使用该研磨石的接合剂的发泡率(foaming rate)相对较高的结构。相应地,由于可以期望该研磨碎片脱离到该研磨石的气穴中,因此可以避免研磨石的堵塞。
然后,如果在该半导体芯片20和第一绝缘膜24的研磨表面上产生的研磨损坏被消除,或者如果执行良好的平面化,则半导体芯片20和第一绝缘膜24被通过CMP方法进一步抛光到大约1至5μm。在这种情况中。半导体芯片20和第一绝缘膜24的研磨表面被通过研磨器的上述研磨而平面化为基本上相同的平面。因此,即使省略抛光步骤,也不会造成问题。
为了消除研磨表面的研磨损坏并且在抛光步骤中执行良好的平面化处理,最好应当采用CMP条件,在该条件下半导体芯片20和第一绝缘膜(树脂膜)24的抛光速率被设置为互为相等。
换句话说,通过使用聚亚安酯抛光布和把硅胶、氧化铈、氮化硅、氧化铁或者氧化铝分散到例如氨水、氢氧化钾等等这样的碱性水溶液中的膏体而执行该抛光。然后,抛光垫和布线基片11被分别以200至500转/分的转速而旋转,然后在使得布线基片11的大约1/2至2/3表面与抛光垫相接触的状态下执行抛光。并且,把膏体溶液分别从设置在该抛光垫的内部的内部喷嘴以及设置在该抛光垫的外部的外部喷嘴施加到该抛光表面。根据这种结构,可以提高抛光效果并且可以提高抛光的共面均匀性。
按照这种方式,由于受到研磨器的研磨的半导体芯片20和第一绝缘膜24的研磨表面被通过CMP方法进一步抛光,因此不但可以消除研磨表面的研磨损坏,而且可以进一步提高半导体芯片20和第一绝缘膜24的抛光表面的平整度。
根据上述研磨步骤和抛光步骤,半导体芯片20的厚度变为大约20μm。当然该半导体芯片20的最终厚度可以被适当地调节。
在本实施例中,被分为各个块的半导体芯片20通过面向下的倒装片焊接安装在布线基片11上,然后由第一绝缘膜24覆盖和支承半导体芯片20,然后第一绝缘膜24和半导体芯片20被研磨,以减薄该半导体芯片20。
按照这种方式,在本实施例中,被分为各个块的半导体芯片20被安装在该刚性布线基片11上,其还被用作为该支承体,然后该半导体芯片20被第一绝缘膜24所支承,然后半导体芯片20被研磨,以减小厚度。因此,与使用研磨接合到暂时支承体的半导体晶片以减小厚度的方法的相关技术1和2不同,不产生导致半导体晶片破裂的缺点。
并且,在本实施例中,仅仅在检查该半导体芯片是否为良好之后,无缺陷芯片被安装在布线基片上。因此,与在接合两个半导体晶片之后使用研磨一个半导体晶片以减小其厚度的方法的相关技术3不同,本发明不可能把有缺陷芯片安装在布线基片11上。
与本实施例不同,当在半导体芯片20仅仅通过孔型树脂22接合的状态中研磨半导体芯片20时,由于在研磨时的损坏,可能在半导体芯片20和布线基片11之间造成有缺陷接合。但是,在本实施例中,当半导体芯片20被研磨时,它们的侧表面被第一绝缘膜24所支承。因此,在研磨过程中不可能损坏半导体芯片20和布线基片11之间的接合,因此可以避免半导体器件的成品率下降。
并且,半导体芯片20和第一绝缘膜24的研磨表面可以被平面化为基本上相同的平面。因此,如下文所述,对于通过倒装片焊接把其他半导体芯片叠加在半导体芯片20上的情况是方便的。
然后,下面将描述如图1H中所示形成把与不形成元件的表面上的连接焊盘21相连接的布线图案形成到半导体芯片20的背表面上的方法。首先,通过光刻方法对在预定部分具有开口的光刻胶膜(未示出)进行构图,该预定部分对应于在减薄的半导体芯片20的背表面上的外围部分中的连接焊盘21。
在此时,如果一个透明薄膜被用作为第一绝缘膜24,则可以通过一个光对齐装置识别上述对齐标记19而执行对齐。相应地,以良好的精度把该光刻胶膜的开口部分对齐在预定位置。
在这种情况中,可以使用通过识别分别形成在多个半导体芯片安装区域附近的对齐标记19而执行对齐的块到块(die-by-die)对齐系统。并且,可以使用通过根据形成在布线基片11的外围区域中的对齐标记19而估计设计的曝光位置以执行对齐的全局对齐系统。
然后,如图1I中所示,通过使用上述光刻胶掩膜作为一个掩膜进行干法蚀刻而腐蚀该半导体芯片20。在此时,该半导体芯片20的蚀刻停止于形成在该元件形成表面上的连接焊盘21处。因此,形成具有从该半导体芯片20的背表面到达在该元件形成表面侧上的连接焊盘21的深度的通孔20a。在这种情况中,通孔20a可以通过使用激光取代干法蚀刻而形成在该半导体芯片20中。
如果一个不透明薄膜被用作为该第一绝缘膜24,则可以通过把X射线或IR(红外线)照射到该半导体芯片20上以透过该芯片,来识别在该元件形成表面侧上的预定图案,而执行对齐。
并且,如果该减薄的半导体芯片20的厚度被设置为10μm或更小,则可以通过把可见光照射到该半导体芯片20上以透过该芯片来识别在该元件形成表面侧上的预定图案。在这种情况中,由于不使用X射线或IR(红外线),因此可以消除使用昂贵的制造系统的必要性。因此,可以获得制造系统成本的下降。
然后,如图1J中所示,第二绝缘膜25形成在该半导体芯片20和第一绝缘膜24上。作为该第二绝缘膜,可以采用以第一绝缘膜24为例的树脂膜相类似的薄膜。在这种情况中,形成在该半导体芯片20中的通孔20a仍然保持为一个空穴。因此,形成由第一绝缘膜24和第二绝缘膜25所构成的一个层间绝缘膜26。
然后,如图1K中所示,通过光刻方法把一个光刻胶膜(未示出)构图于第二绝缘膜25上,以打开包括该半导体芯片20的通孔20a部分的预定区域。然后,通过使用该光刻胶膜作为掩膜蚀刻该第二绝缘膜25。因此,通孔20a被再次暴露,并且形成与该通孔20a相连接的布线凹槽25a。
在这种情况中,作为第二绝缘膜,可以通过在该半导体芯片20和第一绝缘膜24上覆涂一种树脂取代该绝缘膜的接合,然后对该树脂进行退火以使其固化,而形成一个树脂膜。在这种情况中,由于该树脂膜填充在该通孔20a中,因此填充在该通孔20a中的树脂膜被形成该布线凹槽25a的步骤所除去
接着,将在下文参照图2A至2E描述通过在布线凹槽25a中填充铜膜等等而形成布线图案的方法以及图1K中的布线凹槽25a。图2A至2E为以放大的方式示出在图1K中的A部分的放大视图。首先,如图2B中所示,例如氧化硅膜等等这样的一个无机绝缘膜28通过CVD方法形成在图2A中所示该通孔20a和布线凹槽25a的内表面以及第二绝缘膜28的上表面上。该无机绝缘膜28被形成为使得填充在该通孔20a和布线凹槽25a中的导体与半导体芯片20相绝缘。
然后,如图2C中所示,形成在该通孔20a的底部上的无机绝缘膜28被通过激光等等有选择地除去。因此,该连接焊盘21被从该通孔20a的底部暴露出来。
然后,如图2D中所示,由TiN膜、TaN膜等等所制成的阻挡膜30被形成在图2C中的所获得结构上,然后形成由铜膜所制成的种子膜32。接着,通过使用该种子膜32和阻挡膜30作为电镀电源层而把具有埋住该通孔20a和布线凹槽25a的膜厚的铜膜34形成在该种子膜32上。
然后,通过CMP方法对该铜膜34、种子膜32和阻挡膜30进行抛光,直到该无机绝缘膜29的上表面被暴露。因此,该阻挡膜30、种子膜32和铜膜34被埋在该通孔20a和布线凹槽25a中,从而形成导电插塞34b和连接到该导电插塞34b的布线图案34a(导电膜图案)。
在这种情况中,该导电插塞34b和布线图案34a可以通过在该通孔20a和布线凹槽25a中覆涂一种导电膏而埋住它们,然后通过CMP方法对该导电膏进行抛光。
按照这种方式,如图2D中所示,在该半导体芯片20的元件形成表面上的连接焊盘21被通过填充在该通孔20a中的导电插塞34b电连接到在背表面侧上的布线图案34a。
然后,从通过倒装片焊接接合该半导体芯片20(图1F)到在该半导体芯片20的背表面侧上形成布线图案34a(图1L)的一系列步骤被重复执行n次(n为1或更大的整数)。然后,该最上方的半导体芯片20被通过倒装片安装方法而安装,然后该第一绝缘膜24被形成和抛光。结果,多个减薄的半导体芯片20被三维地叠加在该布线基片11上,并且被封装。图1M示出四个半导体芯片20被叠加和封装的模式。
然后,如图1N中所示,由氮化硅膜、聚酰亚胺膜等等所制成的钝化膜36被形成在最上方的半导体芯片20和第一绝缘膜24上。由于由第一绝缘膜24和第二绝缘膜25所构成的上述层间绝缘膜26由该树脂膜所形成,例如这种层间绝缘膜26在该薄膜的剩余应力相对较大的状态下形成。另外,由于由树脂膜所制成的层间绝缘膜26被叠加和形成,因此由这些薄膜的剩余应力而导致在图1M所获得的结构中产生弯曲。
但是,在本实施例中,在图1M中的所获得的结构中产生弯曲时,该弯曲可以通过形成钝化膜36而纠正。例如,如果该层间绝缘膜26的剩余应力是伸张应力,则该钝化膜36被形成为施加压缩应力,以抵消该层间绝缘膜26的剩余应力。
然后,类似地在图1N中所示,通过把焊锡球安装在从不安装半导体芯片20的该布线基片11的表面暴露的导电插塞18b上,而形成凸块38。在这种情况中,可以通过在形成凸块38之前抛光没有安装半导体芯片20的布线基片11的表面而把该布线基片11的厚度减薄到大约50至100μm。
结果,其中叠加和封装多个半导体芯片20的结构体(叠层CSP结构)被顺序地设置在该布线基片11的多个区域上。然后,如图1O中所示,具有根据本实施例的叠层CSP结构的半导体器件1通过把图1N中的多个结构体分离而完成。在这种情况中,该凸块38可以在图1M中的多个结构体被分离之后形成。并且多个结构体可以被分为包括两个或更多的叠层CSP结构。
在本实施例的半导体器件1中,该半导体芯片20通过倒装片安装而安装在该布线基片11上,并且该半导体芯片20的背表面被研磨,以在该半导体芯片20被第一绝缘膜24所支承的状态下减小厚度。该布线图案34a被形成在该半导体芯片20的背表面侧。并且该布线图案34a被通过贯穿该半导体芯片20的通孔20a而电连接到在该元件形成表面上的连接焊盘21。具有这种结构的多个半导体芯片20被埋在该层间绝缘膜26中。
在此,与本实施例不同,例如,提出这样的封装结构,其中父芯片和子芯片被以面向上的方式叠加在该布线基片上和封装,并且这些芯片的连接焊盘被通过线接合方法连接到该布线基片。在这种情况中,由于该子芯片被在保证父芯片的焊接面积的状态下被安装,因此该子芯片的尺寸受到限制。
但是,在本实施例的半导体器件1中,多个半导体芯片20被通过形成在该半导体芯片20中的通孔20a相互接合并且电连接到该布线基片11。因此,可以设置和叠加具有任何尺寸的多个半导体芯片20,而不受到它们的相互尺寸的限制。结果,可以扩大要被安装的半导体芯片的选择范围,因此可以提高设计容限。
并且,由于该布线图案34a通过薄的无机绝缘膜28形成在该半导体芯片20的背表面上,因此可以减小多个半导体芯片20被封装的半导体器件1的厚度。
另外,该上和下半导体芯片20被通过贯穿该半导体芯片20的通孔20a经在垂直方向上提供的布线相互连接。因此,可以缩短布线长度,而与通过接合线连接该半导体芯片的情况或者应用包含在横向方向上的线路由的布线的情况不同。
并且,如果例如CPU和存储器这样的半导体芯片20被相邻封装,则可以缩短布线长度。因此,从可以提高半导体器件1的性能的观点来看,这是方便的。
另外,被分为各个块的半导体芯片20被抛光,以减小它们被通过倒装片安装方法而安装在布线基片11上之后由第一绝缘膜24所支承的状态中的厚度。因此,不需要处理难以处理的减薄的半导体芯片20。由此,可以把该半导体芯片20的厚度减小到大约10μm,而不产生任何缺点。
并且,当研磨该半导体芯片20时,第一绝缘膜24也被同时研磨。因此,厚度被减薄的半导体芯片20和第一绝缘膜24的研磨表面可以被平面化为具有几乎相同的高度。
在本实施例中,举例说明该半导体芯片20的凸块23被接合和安装的模式。由于如上文所述该安装表面被平面化,则该上层半导体芯片20的连接焊盘21可以直接焊接到下层半导体芯片20的背表面侧上的布线图案34a,而不受到该凸块23的影响。另外,由于该布线基片11的布线图案18a通过镶嵌方法而形成,该布线基片11的安装表面还被平面化。因此,可以类似地从焊接到该布线基片11的最下方半导体芯片20省略该凸块23。
按照这种方式,由于可以省略要被安装的多个半导体芯片20的凸块23,因此可以进一步减小该半导体器件1的厚度。
在这种情况中,在第一实施例中,举例说明通过形成在这些半导体芯片20中的通孔20a把多个叠层的半导体芯片20相互连接的模式。类似于在下文中所述的第二实施例,多个半导体芯片20可以通过形成在该半导体芯片附近的第一绝缘膜24中的通孔相互连接。
并且,根据第一实施例的半导体器件可以通过使用玻璃基片来取代硅基片10而制造。在这种情况中,不需要形成无机绝缘膜12。
(第二实施例)
图3A至3O为按照步骤的次序示出根据本发明第二实施例的半导体器件制造方法的截面视图。第二实施例与第一实施例之间的不同点在于该布线基片由绝缘基片所形成,并且多个叠加的半导体芯片通过形成在该半导体芯片附近的绝缘膜中的通孔相互连接。在这种情况中,在此将省略与第一实施例类似的步骤的说明。
在根据本发明第二实施例的半导体器件制造方法中,如图3A中所示,首先制备一个绝缘基片40。作为该绝缘基片40,可以采用选自由FR4、BT等等所制成的树脂基片、玻璃基片、陶瓷基片、蓝宝石基片等等的一种基片。
然后,如图3B和图3C中所示,布线凹槽40a形成在该绝缘基片40上,然后形成从该布线凹槽40a的底表面的预定区域通过的通孔40a。然后,如图3D中所示,该阻挡膜14和种子膜16被顺序地形成在该绝缘基片40上,其中通过与第一实施例相同的方法形成该布线凹槽40a和通孔40b。然后,通过电镀方法形成铜膜18,以具有可以埋住该布线凹槽40a和通孔40b的膜厚。在这种情况中,由于该绝缘基片40被用于第二实施例中,因此不需要在形成阻挡膜14之前形成无机绝缘膜。
然后,如图3E中所示,根据与第一实施例类似的方法,通过CMP方法对该铜膜18、种子膜16和阻挡膜14进行抛光,直到该绝缘基片40的上表面被暴露,相应地,形成填充在该通孔40b中的导电插塞18b和连接到该导电插塞18b的布线图案18a,因此获得一种布线基片11a。
在这种情况中,举例说明通过使用镶嵌方法形成填充在该通孔40b中的导电插塞18b和连接到导电插塞18b的布线图案18a的方式。但是可以制备用于堆积布线(其中通孔铜镀层被形成并且该孔被树脂所填充)底部基片,然后可以通过所谓的添加方法或者消减方法形成布线图案。以形成连接到通孔铜镀层的铜布线。
然后,如图3F中所示,根据类似于第一实施例的方法,多个无缺陷半导体芯片20被通过倒装片焊接而接合到该布线基片11a的布线图案18a上。然后,如图3G中所示,该第一绝缘膜24形成在布线基片11a上,以具有暴露至少该半导体芯片20的背表面的膜厚。作为形成该第一绝缘膜24的方法的一个例子,首先在以大约300转/秒的低速把例如环氧树脂或者聚酰亚胺树脂这样的预定量的覆涂液体滴在该布线基片11a的中部。因此,该覆涂液体在该布线基片11a的整个表面上扩展。然后,形成为覆盖该布线基片11a的背表面的覆涂膜被通过大约3000转/分的高速旋转该布线基片11a而除去。按照这种方式,具有暴露该半导体芯片20的背表面的厚度的覆涂膜形成在该布线基片11a的安装表面上。
然后,通过在设置为150℃的温度下的熔炉中固化该覆涂膜,以形成一个树脂膜。因此,在该半导体芯片20的背表面被暴露的状态下,处于所谓的丝带形式的树脂膜所制成的第一绝缘膜24形成在多个半导体芯片20之间。在第二实施例中,按照这种方式由该第一绝缘膜24支承该半导体芯片20。
然后,如图3H中所示,根据与第一实施例类似的方法,通过利用研磨器研磨该半导体芯片20和第一绝缘膜24,该半导体芯片20的厚度被减薄到大约20μm。在该状态中,与第一实施例相类似,在由该研磨器研磨该半导体芯片20之后,该半导体芯片20可以通过CMP方法而抛光。
然后,如图3I中所示,通过利用激光在该半导体芯片20附近的第一绝缘膜24中打开对应于布线基片11上的布线图案的预定部分的部分而形成通孔24a。否则,感光的聚酰亚胺树脂可以被用作为第一绝缘膜24,然后可以通过对该树脂进行曝光/显影而形成通孔24a。
然后,如图3J中所示,根据与第一实施例相类似的方法,在第一绝缘膜24和半导体芯片20上形成第二绝缘膜。因此,形成由第一绝缘膜24和第二绝缘膜25所构成的层间绝缘膜26。
然后,如图3K中所示,通过腐蚀包括对应于在第二绝缘膜25中的通孔24a的部分的预定区域而形成布线凹槽25a。因此,形成通孔24a和与该通孔24a连通的布线凹槽25a。在该状态中,在第二实施例中,可以采用通过旋涂方法或者通过印刷方法所形成的一个树脂层来取代该树脂膜而作为第二绝缘膜25。
然后如图3L中所示,根据与第一实施例类似的方法,从在图3K的所获得结构的底部顺序地形成阻挡膜、种子膜和铜膜(为示出)。然后,通过对这些层进行抛光而形成该导电插塞34b和连接到该导电插塞34b的布线图案34a。结果,该布线基片11的布线图案18a被通过导电插塞34b电连接到形成在该半导体芯片20的背面侧上的布线图案34a。
然后如图3M中所示,从通过倒装片焊接把该半导体芯片20与布线基片11相接合的步骤(图3F)到在半导体芯片20的背表面侧上形成布线图案34a的步骤(图3L)的一系列步骤被重复n次(n为1或更大的整数)。然后,通过倒装片安装而安装最上方的半导体芯片20,然后第一绝缘膜24被形成和抛光。
结果,多个减薄的半导体芯片20被三维地叠加在该布线基片11上,并且被封装。然后,形成用于覆盖该最上方的半导体芯片20的第二绝缘膜25。在这种情况中,在图3M中,示出四个半导体芯片20被叠加和封装的方式。
然后如图3N中所示,类似于第一实施例,该钝化膜36形成在第二绝缘膜25上,以用于纠正在图3M中所获得结构的弯曲。然后,形成与从不安装半导体芯片20的该布线基片11的表面区域上暴露出来的该导电插塞18b相连接的凸块38。
然后,类似于第一实施例,通过分别分割在图3N中的多个结构体而完成具有叠层CSP结构的半导体器件1a。
在第二实施例的半导体器件1a中,与第一实施例不同,通过该半导体芯片的通孔20a不形成在多个半导体芯片20中,但是该通孔24a分别形成在多个半导体芯片20附近的第一绝缘膜24中。
该最上方的半导体芯片20被通过倒装片安装而安装在该布线基片11的布线图案18a上,并且在这种半导体芯片20被第一绝缘膜24所支承的状态下对该半导体芯片20的背表面进行研磨和减薄。该布线图案形成在该半导体芯片20的背表面上,以与它们接触。该布线图案34a被通过形成在第一绝缘膜24中的通孔24a电连接到在该元件形成表面侧上的连接焊盘21。具有这种结构的多个半导体芯片20在该半导体芯片20被埋在该层间绝缘膜26中的状态下被三维地叠加和相互连接。
该第二实施例的半导体器件1a可以获得与第一实施例相同的优点。另外,在第二实施例中,在该布线图案与该半导体芯片20的背表面相接触的状态下形成该布线图案。因此,可以进一步减小封装多个半导体芯片20的半导体器件1的厚度。
并且,在第二实施例中,该通孔20a不形成在该半导体芯片20中,但是该通孔24a形成在第一绝缘膜24中。因此,通过采用通常使用的激光设备和曝光设备可以容易地形成该通孔24a,而不引入特殊的对齐装置。结果,可以把该半导体器件的制造成本减小到低于第一实施例的成本。
在这种情况中,在第二实施例中,与第一实施例相同,可以使用各种变型和改变。例如,该布线基片11可以通过使用绝缘基片40而形成,并且与第一实施例相同,不是通过在第一绝缘膜24中形成通孔24a而是在该半导体芯片20中形成通孔20a,使得多个半导体芯片相互连接。
(第三实施例)
图4A至4C为示出根据本发明第三实施例的半导体器件制造方法的截面视图。在上述第二实施例中,如果由FR4、BT等等所制成的树脂基片被特别用作为该绝缘基片,则该树脂基片在精细构图特性方面比该硅基片更差。因此,存在这样一种情况,其中在通过镶嵌方法形成精细布线凹槽和通孔的步骤中导致制造成本的增加。该第三实施例可以克服该缺点。在这种情况中,在此将省略与第一和第二实施例相同的步骤的具体描述。
在根据本发明第三实施例的半导体器件制造方法中,如图4A中所示,形成把由铜布线所制成的预定布线图案18a形成在该绝缘基片40的一个表面上的布线基片11b。作为形成该布线图案18a的方法,形成具有开孔部分感光绝缘树脂膜,在该开孔中形成绝缘基片的布线图案18a,然后有选择地通过无电镀方法(添加方法)在该开孔部分中形成铜膜。否则,该铜膜通过无电镀和电镀方法形成在该绝缘基片40的一个表面上,然后通过光刻和腐蚀对该铜膜进行构图(消减方法)。
按照这种方式,该布线图案18a被通过普通的添加方法或消减方法而形成在该绝缘基片40上。因此,不需要通过对该绝缘基片40进行精细构图而形成布线凹槽和通孔的步骤,因此可以抑制布线基片的制造成本的增加。
类似地,如图4A中所示,根据与第二实施例类似的方法,连接到该布线基片11b的布线图案18a的多个半导体芯片20被叠加和封装。
然后,如图4B中所示,在最上方的半导体芯片20上的第二绝缘膜25上形成钝化膜36。然后,通过钻孔、激光等等腐蚀叠加在该布线基片11b的布线图案18a的外侧部分上的层间绝缘膜26和钝化膜36。因此,形成用于暴露该布线基片11b的布线图案18a的一部分的通孔42。
然后,通过在该通孔42等等中填充导电膏而形成与该布线基片11b的布线图案18a相连接的导电插塞44。然后,形成连接到该导电插塞44的凸块38。
然后,类似于第一实施例,通过分别分离在图4B中的各个结构体而完成具有叠层CSP结构的半导体器件1b。
在第一实施例的半导体器件1b中,多个半导体芯片20被相互连接和叠加在该布线基片11b上,以具有与第二实施例相同的结构。该布线基片11b的布线图案18a被通过形成在该叠层的层间绝缘膜26中的通孔42连接到在钝化膜36的表面上的凸块38。
该第三实施例可以获得与第二实施例相同的优点。另外,由于不对该绝缘基片40进行精细构图,因此即使当采用精细构图特性比硅基片更差的树脂基片时,可以容易地制造根据本发明第三实施例的半导体器件,而不增加制造成本。
(第四实施例)
图5为示出根据本发明第四实施例的半导体器件制造方法的截面视图。该第四实施例提供多个半导体芯片分别叠加在该布线基片的两个表面上并且被封装的方式。在图5中,与图3O中所示相同的部件由相同的参考标号所表示,并且在此将省略对它的描述。
如图5中所示,第四实施例的半导体器件示出多个半导体芯片还叠加在第二实施例(图3O)的半导体器件1a中的布线基片11的背表面侧(安装有凸块38的表面)的方式。换句话说,布线图案18c还形成在第四实施例的布线基片11的背表面侧上。这些布线图案18c通过填充在该布线基片11的通孔10b中的导电插塞18b电连接到在该表面侧上的布线图案18a。
然后,该半导体芯片20的凸块23通过倒装片焊接接合到在背面侧上的布线图案18c。另外,该布线图案34a形成在该半导体芯片20的背表面侧上。这些布线图案34a通过形成在第一绝缘膜24中的通孔24a电连接到在该元件形成表面侧上的连接焊盘21。具有这种结构的多个半导体芯片20被在该半导体芯片20埋在层间绝缘膜26中的状态下三维地叠加和相互连接。
根据第四实施例的半导体器件1c,由于多个减薄的半导体芯片20被叠加在该布线基片11的两个表面上并且被分别封装,则可以比第一至第三实施例更高地提高封装密度。
在这种情况中,尽管示出通过应用第二实施例的封装方法把多个半导体芯片20叠加在该布线基片11的两个表面上的方式,但是可以采用通过应用第一实施例的封装方法把多个半导体芯片20叠加在该布线基片11的两个表面上的方式。
并且可以应用这样一种方式,其中在第三实施例的半导体器件1b中(图4C),形成在两个表面上的布线图案被通过通孔相互连接的基片被用作为该布线基片11b,并且电连接到该布线图案的多个半导体芯片20被叠加在不安装有该半导体芯片20的布线基片11b的表面上。
(第五实施例)
图6A至6F为示出根据本发明第五实施例的半导体器件制造方法的截面视图。该第五实施例提供这样的方式,其中其上具有预定布线图案(连接焊盘)的金属片被用作为该布线基片,并且通过使用第一或第二实施例的封装方法叠加和封装连接到该金属片的布线图案的多个半导体芯片,然后仅仅有选择地除去该金属片。在这种情况中,在此将省略与其他实施例相同的部件和相同的步骤。
在根据第五实施例的半导体器件制造方法中,如图6A中所示,首先制备由铜等等所制成的金属片50。然后,通过光刻方法在该金属片50的一个表面上形成在要形成该布线图案的部分处具有开孔部分52a的光刻胶膜52。在此时,用该光刻胶膜52覆盖该金属片50的其他表面。
然后,如图6B中所示,通过使用该金属片50作为电镀电源层并且使用该光刻胶膜52作为一个掩膜,通过电镀在该开孔部分52a中顺序地形成金层54a、镍层54b和金层54c。然后,除去该光刻胶膜52。因此,如图6C中所示,分别由金层54a、镍层54b和金层54c所构成的布线图案(连接焊盘)54被形成在该金属片50上。
然后,如图6D中所示,根据类似于第一实施例的封装方法,电连接到在该金属片50上的布线图案54的多个半导体芯片20被封装。在这种情况中,可以通过使用第二实施例的封装方法而封装该半导体芯片20。
然后,如图6E中所示,形成用于覆盖最上方的半导体芯片20的钝化膜36。然后,该金属片50被相对于该布线图案54和第一绝缘膜24有选择地腐蚀,并且被除去。例如,如果该金属片50由铜所形成,则可以通过使用氯化铁(III)水溶液、氯化铜(II)水溶液、过氧化铵水溶液等等对该布线图案(金层/镍层/金层)54和第一绝缘膜(树脂膜)24进行有选择地腐蚀,并且可以除去。因此,连接到该半导体芯片20的布线图案54从第一绝缘膜24的下表面暴露出来。
然后,形成连接到通过除去该金属片50而暴露的布线图案54的凸块。然后,如图6F中所示,与第一实施例相同,通过分离在图6F中的多个结构体而完成具有叠加CSP结构的第五实施例的半导体器件1d。
在按照这种方式制造的半导体器件1d中,多个叠层的半导体芯片20中的最下方半导体芯片20的凸块23被通过倒装片焊接方法接合到该布线图案54的上表面,该布线图案的下表面被连接到该凸块38,并且被埋在该第一绝缘膜24中。然后,除了最下方半导体芯片20之外的半导体芯片20通过倒装片焊接接合到分别形成在该下层半导体芯片20的背表面侧上的布线图案34a。按照这种方式,三维叠层的多个半导体芯片20通过形成在该半导体芯片20中的通孔20a相互连接。
第五实施例的半导体器件1d可以获得与第一实施例相同的优点。并且,由于不提供该布线基片,可以相应地把该半导体器件的厚度减小到比在其他实施例中具有布线基片的半导体器件更薄。
(第六实施例)
图7A至图7G为示出根据本发明第六实施例的半导体器件制造方法的截面视图。该第六实施例与第五实施例的不同点在于不但该布线图案形成在该金属片上,而且连接到该布线图案的凸块被预先形成在该金属片中。在这种情况中,在此将省略与其他实施例相同的部件和相同的步骤的详细描述。
在根据第六实施例的半导体器件制造方法中,如图7A中所示,根据第五实施例的类似方法,首先对具有用于在由铜所制成的金属片50的一个表面上形成布线图案的开孔部分52a的光刻胶膜52进行构图,并且用该光刻胶膜52覆盖其他表面。
然后,如图7B中所示,使用该光刻胶膜52作为掩膜通过蚀刻该金属片50的暴露部分而形成凹陷部分50a。然后,通过使用该金属片50作为电镀电源层,并且使用该光刻胶膜52作为掩膜,对在该金属片50上的凹陷部分50a的内部部分进行焊锡电镀。因此,形成焊锡层38a。
然后,如图7C中所示,根据与上述电镀相同的方法,由与第五实施例类似的叠层膜(金层/镍层/金层)所制成的布线图案54被形成在该光刻胶膜52的开孔部分52a中。然后,除去光刻胶膜52。相应地,如图7D中所示,该焊锡层38a被填充在该金属片50的凹陷部分50a中,以获得被形成并且连接到该焊锡层38a的布线图案。该焊锡层38a被通过后续步骤形成为凸块。
然后,如图7E中所示,根据类似于第一实施例的封装方法,封装电连接到在该金属片50上的布线图案54的多个半导体芯片20。在这种情况中,可以通过使用类似于第二实施例的封装方法而封装该半导体芯片20。
然后,如图7F中所示,形成用于覆盖最上方的半导体芯片20的钝化膜36。然后,该金属片50被相对于该焊锡层38a和第一绝缘膜24有选择地腐蚀和除去。例如,如果该金属片50由铜所形成,则可以通过使用类似于第五实施例的湿法蚀刻剂而对该焊锡层38a和第一绝缘膜(树脂膜)24有选择地除去该金属片50。结果,该焊锡层38a被暴露,作为该凸块38。
然后,如图7G中所示,与第一实施例相同,通过分离在图7F中的多个结构体而完成具有叠加的CSP结构的第六实施例的半导体器件1e。
第六实施例可以获得与第一实施例相同的优点。并且,由于不象第一实施例那样提供布线基片,因此可以比其他实施例减小该半导体器件的厚度。
在上文中,已经参照第一至第六实施例详细描述本发明。但是本发明的范围不限于在上述实施例中具体示出的方式。应当知道不脱离本发明的思想的上述实施例的变型被包含在本发明的范围内。
例如,在第一实施例中,与第三实施例相同,可以采用由硅基片10所制成的布线基片11的布线图案18a通过在层间绝缘膜26中形成的通孔连接到安装在该钝化膜36上的凸块38的方式。
Claims (23)
1.一种半导体器件制造方法,其中包括如下步骤:
在一个表面上制备包括布线图案的布线基片;
通过倒装片焊接把在一个表面上具有预定元件和一个连接端的电子芯片的连接端接合到该布线基片的布线图案上;
在该布线基片上形成第一绝缘膜,该第一绝缘膜具有覆盖该电子芯片的膜厚或者暴露该电子芯片的至少另一个表面的膜厚;以及
通过研磨该第一绝缘膜和该电子芯片的另一个表面而减小该电子芯片的厚度。
2.根据权利要求1所述的半导体器件制造方法,其中该减小电子芯片的厚度的步骤是通过研磨器研磨的步骤,或者是通过研磨器研磨然后通过化学机械抛光的步骤。
3.根据权利要求1所述的半导体器件制造方法,其中在减小该电子芯片的厚度的步骤中,该电子芯片的抛光表面和第一绝缘膜的上表面被平面化为几乎相同的高度。
4.根据权利要求1所述的半导体器件制造方法,其中在减小该电子芯片的厚度的步骤之后,进一步包括如下步骤:
在该电子芯片中形成具有一个深度的通孔,其从在该电子芯片的另一个表面上的预定部分到达该电子芯片的一个表面上的连接端;
在该电子芯片和第一绝缘膜上形成第二绝缘膜;
通过蚀刻包含对应于该通孔的一部分的第二绝缘膜的预定部分,形成与该通孔连通的一个布线凹槽;以及
通过在该通孔和布线凹槽中填充导电膜而形成通过该通孔连接到该连接端的导电膜图案。
5.根据权利要求4所述的半导体器件制造方法,在形成导电膜图案的步骤之后,进一步包括如下步骤:
根据n次(n为1或更大的整数)重复执行从通过倒装片焊接接合该电子芯片的步骤到形成通过通孔连接到连接端的导电膜图案的步骤之间的一系列步骤,在该布线基片上三维地叠加和封装多个电子芯片。
6.根据权利要求4所述的半导体器件制造方法,其中该布线基片具有与该导电膜图案同时形成的一个对齐标记,以及
在电子芯片中形成通孔的步骤中根据对齐标记的识别而确定形成电子芯片的通孔的一个部分。
7.根据权利要求4所述的半导体器件制造方法,其中在该电子芯片中形成通孔的步骤中,根据通过把X射线、红外线或可见光从该电子芯片的另一个表面透射而执行在该电子芯片的一个表面上的预定图案的识别,确定形成电子芯片的通孔的一个部分。
8.根据权利要求1所述的半导体器件制造方法,其中在减小该电子芯片的厚度的步骤之后,进一步包括如下步骤:
在第一绝缘膜中形成具有一个深度的通孔,其从在该第一绝缘膜的预定部分的上表面到达该布线基片的导电膜图案;
在该电子芯片和第一绝缘膜上形成第二绝缘膜;
通过腐蚀包含对应于该通孔的一部分的第二绝缘膜的预定部分而形成与该通孔相连通的布线凹槽;以及
通过在该通孔和布线凹槽中填充导电膜而形成通过该通孔连接到该布线基片的布线图案的导电膜图案。
9.根据权利要求8所述的半导体器件制造方法,在形成导电膜图案的步骤之后,进一步包括如下步骤:
根据n次(n为1或更大的整数)重复执行从通过倒装片焊接接合该电子芯片的步骤到形成通过通孔连接到该布线基片的布线图案的导电膜图案的步骤之间的一系列步骤,在该布线基片上三维地叠加和封装多个电子芯片。
10.根据权利要求5所述的半导体器件制造方法,其中在该布线基片上三维地叠加和封装多个电子芯片的步骤之后,进一步包括如下步骤:
在多个电子芯片中的最上方的电子芯片上或上方形成一个钝化膜。
11.根据权利要求10所述的半导体器件制造方法,其中在该布线基片中形成连接到该布线图案和填充在贯穿该布线基片的通孔中的一个导电插塞;以及
在布线基片上三维地叠加和封装多个电子芯片的步骤之后,进一步包括如下步骤:
形成连接到从该布线基片的相对表面向着形成有该布线图案的一个表面暴露出来的导电插塞的一个凸块。
12.根据权利要求10所述的半导体器件制造方法,其中在形成该钝化膜的步骤之后,进一步包括如下步骤:
通过腐蚀分别由第一绝缘膜和第二绝缘膜所构成的多个层间绝缘膜和钝化膜,在该布线图案上方的区域上和在不安装该电子芯片的区域上形成一个暴露一部分布线图案的通孔;
在该通孔中形成一个导电插塞;以及
形成连接到该导电插塞的一个凸块。
13.根据权利要求10所述的半导体器件制造方法,其中该布线基片是在一个表面上包括布线图案的金属片;以及
在形成该钝化膜的步骤之后,进一步包括如下步骤:
通过对该布线图案和第一绝缘膜有选择地腐蚀和除去该金属片而暴露出该布线图案;以及
形成连接到该布线图案的凸块。
14.根据权利要求10所述的半导体器件制造方法,其中该布线基片是包括填充在提供到该金属片的凹陷部分中的焊锡层以及形成在该焊锡层上的布线图案的金属片,以及
在形成该钝化膜的步骤之后,进一步包括如下步骤:
通过对该焊锡层和第一绝缘膜有选择地腐蚀和除去该金属片以暴露出该焊锡层而形成一个凸块。
15.根据权利要求11所述的半导体器件制造方法,其中电子芯片被叠加和封装的结构体被形成在该布线基片的多个区域中,以及
在形成凸块的步骤之前或之后,进一步包括如下步骤:
分割该布线基片,以包含预定数目的叠加和封装电子芯片的结构体。
16.根据权利要求1所述的半导体器件制造方法,其中在减小该电子芯片的厚度的步骤中,该电子芯片的厚度大约为150μm或更小。
17.一种半导体器件,其中包括多个电子芯片,其中在该电子芯片的一个表面上包括预定元件和一个连接端,并且在该电子芯片的另一个表面上包括通过穿过该电子芯片的通孔电连接到该连接端的导电膜图案,该电子芯片在与该布线基片的表面方向相垂直的方向上,在该电子芯片被埋在一个层间绝缘膜中的状态下,叠加和封装在包括一个布线图案的布线基片上,
其中该电子芯片的厚度大约为150μm或更小,并且该电子芯片的连接端分别通过倒装片焊接接合到下层布线基片的布线图案或者接合到该电子芯片的导电膜图案,并且多个电子芯片被通过在该电子芯片中的通孔相互连接。
18.根据权利要求17所述的半导体器件,其中进一步包括:
形成在多个电子芯片中的最上方的电子芯片上或上方的一个钝化膜。
19.根据权利要求17所述的半导体器件,其中通过穿过该布线基片的通孔连接到该布线图案的一个凸块被提供在该布线基片的与形成有布线图案的表面相对的一个相对表面上。
20.根据权利要求18所述的半导体器件,其中通过形成在该布线图案上方的区域上和在不安装该电子芯片的区域上的该层间绝缘膜和钝化膜中的通孔电连接到该布线基片的布线图案的凸块被提供到形成有该钝化膜的半导体器件的一个表面上。
21.一种半导体器件,其中包括多个电子芯片,其中在该电子芯片的一个表面上包括预定元件和一个连接端,并且在该电子芯片的另一个表面上包括通过穿过该电子芯片的通孔电连接到该连接端的导电膜图案,该电子芯片在该电子芯片被埋在一个层间绝缘膜中的状态下被三维地叠加和封装,
其中该电子芯片的厚度大约为150μm或更小,并且在多个电子芯片中的最下方电子芯片的连接端分别通过倒装片焊接接合到以暴露该布线图案的下表面的状态中埋在一个绝缘膜内的布线图案的上表面,并且在多个电子芯片中的其他电子芯片的连接端被分别通过倒装片焊接接合到下层的电子芯片的导电膜图案,从而多个电子芯片被通过在该电子芯片中的通孔相互连接。
22.根据权利要求21所述的半导体器件,其中该凸块被连接到与最下方电子芯片的连接端相接合的布线图案的下表面。
23.根据权利要求17所述的半导体器件,其中形成在该电子芯片的另一个表面侧上的该导电膜图案被形成为与该电子芯片的另一个表面相接触。
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Also Published As
Publication number | Publication date |
---|---|
JP4056854B2 (ja) | 2008-03-05 |
KR20040040352A (ko) | 2004-05-12 |
EP1801866A3 (en) | 2007-12-19 |
US20040119166A1 (en) | 2004-06-24 |
EP1418617A3 (en) | 2004-05-26 |
TW200414495A (en) | 2004-08-01 |
EP1418617B1 (en) | 2008-10-29 |
US7507602B2 (en) | 2009-03-24 |
DE60327721D1 (de) | 2009-07-02 |
DE60324376D1 (de) | 2008-12-11 |
US6958544B2 (en) | 2005-10-25 |
EP1801866A2 (en) | 2007-06-27 |
US20050212126A1 (en) | 2005-09-29 |
EP1418617A2 (en) | 2004-05-12 |
EP1801866B1 (en) | 2009-05-20 |
JP2004158537A (ja) | 2004-06-03 |
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