CN1484288A - Method for making semiconductor device with ultra-shallow and ultra-gradient reverse surface channel by boron fluoride compound doping - Google Patents

Method for making semiconductor device with ultra-shallow and ultra-gradient reverse surface channel by boron fluoride compound doping Download PDF

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CN1484288A
CN1484288A CNA031423477A CN03142347A CN1484288A CN 1484288 A CN1484288 A CN 1484288A CN A031423477 A CNA031423477 A CN A031423477A CN 03142347 A CN03142347 A CN 03142347A CN 1484288 A CN1484288 A CN 1484288A
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channel doping
doping layer
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CN1243372C (en
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孙容宣
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SK Hynix Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

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Abstract

This invention relates to a method for fabricating a semiconductor device with the epi-channel structure, which is adapted to overcome an available energy limitation and to improve the productivity by providing the method of SSR epi Channel doping by boron-fluoride compound ion implantation without using ultra low energy ion implantation and a method for fabricating the semiconductive device with epi-channel structure adapted to prevent the crystal defects caused by the epitaxial growth on ion bombarded and fluorinated channel doping layer. The method for forming the epi-channel of a semiconductor device includes the steps of: forming a channel doping layer below a surface of a semiconductive substrate by implanting boron-fluoride compound ions containing boron; performing an annealing process to remove fluorine ions, injected during above ion implantation, within the channel doping layer; performing the surface treatment process to remove the native oxide layer formed on the surface of the channel doping layer and simultaneously to remove remaining fluorine ions within the channel doping layer; and growing epitaxial layer on the channel doping layer using the selective epitaxial growth method.

Description

By the compound doped method of making semiconductor device of boron fluoride with super shallow super steep reflecting surface raceway groove
Technical field
The present invention relates to a kind of method of making semiconductor device, more particularly, the present invention relates to have the gate signal width (gate length) less than the manufacture method of the semiconductor device of the super shallow super steep reflecting surface raceway groove (super-steep-retrograde epi-channel) of 100nm.
Background technology
In general, in transistor such as mos field effect transistor (MOSFET) or metal insulatioin semiconductor field effect transistor (MISFET), the effect that is configured in the surf zone of the semiconductive substrate below grid (gate electrode) and the gate oxide is owing to be applied to the electric field of source electrode (source) and/or drain electrode (drain), under the state that is applied to above the voltage that triggers on the grid, make current flowing.Therefore, this surf zone is called as raceway groove (channel).
Above-mentioned transistorized performance also depends on the concentration of dopant of raceway groove, and accurately doped channel is extremely important, because concentration of dopant has determined multiple performance such as transistorized threshold voltage (V T), drain current (I d) etc.
As the doping method of raceway groove, use the channel ion implantation (channel ion implantation) (or critical voltage is adjusted the ion implantation) of ionic-implantation (ion implantation method) to be used widely.The smooth raceway groove (flat channel) that uses the formed channel structure of above-mentioned ionic-implantation to comprise in raceway groove, to have constant density in its degree of depth, form the buried channel (buried channel) of raceway groove at desired depth place and have low surface concentration and reverse raceway groove (retrograde channel) that its concentration in raceway groove increases fast along depth direction etc. away from the surface.
In above-mentioned raceway groove, oppositely raceway groove is widely used in high-performance microprocessor, and its channel length is 0.2 μ m or littler.Reverse raceway groove is implanted the heavy ion of In (indium), As (arsenic), Sb (antimony) etc. and is formed.Has high surface migration because of the low surface dopant concentration of reverse raceway groove, so it has been applied in the high performance device with high drive current characteristic.
Yet along with channel length reduces, required channel depth must be more shallow.And when being used to form its channel depth and being 50nm or littler reverse raceway groove, ion embedding technology is restricted.
In order to meet these demands, proposed a kind of surface channel (epi-channel) structure, wherein go up and form epitaxial loayer (epitaxial layer) in channel doping layer (channel doping layer).
Figure 1A is the drawing in side sectional elevation with semiconductor device of conventional surface channel structure.
With reference to Figure 1A, on Semiconductor substrate 11, form gate dielectric 12 and grid 13, comprise that the surface channel of epitaxial loayer 14 and channel doping layer 15 is formed on the Semiconductor substrate 11, substrate 11 is configured in below the gate dielectric 12.On two sides of surface channel, also form source/drain extension area (source/drain extension) (back is called SDE) 16 and the source/drain regions (source/drain area) 17 of high concentration (high-concentration).
Yet, owing to form the technology and the subsequent thermal technology of epitaxial loayer, be difficult to the diffusion of loss of controlled doping thing and channel doping layer 15, be problematic so enforcement has the needed ON/OFF of improvement of high performance device (ON/OFF) current characteristics of surface channel structure.
In order to address this problem, a kind of method has been proposed, carry out the surface channel that triangle (delta) mixes to form, shown in Figure 1B by the doped epitaxial layer of stepped doping and two epitaxial loayers that doped epitaxial layer was not constituted.
Figure 1B is illustrated in before the surface channel that forms delta doped, and doping curve (doping profile) is with the variation diagram of transient state enhanced diffusion (transient enhanced diffusion) (back is called TED) or heat balance (thermal budget).With reference to Figure 1B, because the stepped delta doped curve of the surface channel under gate dielectric (Gox) is because TED or heat balance and do not keep desirable delta doped curve (P1), thereby widen (P2) of doping curve taken place.
Thereby, under the situation of using the surface channel that forms delta doped by two epitaxial loayers that doped epitaxial layer and unadulterated epitaxial loayer constituted, because can not deposit 1 * 10 19Atom/cm 3(atoms/cm 3) or low concentration epitaxial layer still less, owing to TED or heat balance make the diffusion (D) of alloy excessive, make when the enforcement channel depth is the surface channel of 30nm or littler delta doped, to be restricted.
In order to improve these problems, a kind of method is proposed, wherein after implanting the delta doped n-channel doping layer that forms the concentration with accurate control with ultra-low calorie boron ion, instantaneous enforcement LASER HEAT annealing (laser thermal annealing) (LTA) technology prevents the diffusion (with reference to Fig. 2 A and 2B) of the n-channel doping layer of delta doped.
Fig. 2 A and 2B represent to have with ultra-low energy ion and implant and with the drawing in side sectional elevation of the manufacture method of the semiconductor device of the formed surface channel of LASER HEAT annealing (LTA) technology.
Shown in Fig. 2 A, have the shallow slot ditch isolate (shallow trench isolation) (STI) field oxide of structure (field oxide layer) 22 be formed on the Semiconductor substrate 21, and P-type dopant ions is implanted in the Semiconductor substrate 21, thereby forms P-type trap (well) 23.Subsequently, form the channel doping layer 24 of delta doped at the following boron implant ion of ultra-low calorie (1kev).
Then, directly carry out 0.36J/cm 3To 0.44J/cm 3LASER HEAT annealing (LTA) technology, and need not any amorphization in advance (preamorphization) make the surperficial amorphization of Semiconductor substrate 21.By Fig. 2 B as seen, the LASER HEAT annealing process suppresses the redistribution of boron in channel doping layer 24, and change channel doping layer 24 becomes chemically stable channel doping layer 24A.
Shown in Fig. 2 B, epitaxial loayer 25 is in optionally growth on channel doping layer 24A under 600 ℃ to 800 ℃ the temperature, thus super steep oppositely (SSB) surface channel structure of formation.
Simultaneously, can use rapid thermal annealing (RTA) technology and LASER HEAT annealing process to prevent the TED of the channel doping layer of delta doped.
Fig. 3 A and 3B are illustrated respectively on the boron doped sample that the 1KeV ion is implanted or the 5KeV ion is implanted the optionally doping curve of the formed SSR surface channel of epitaxial growth.
From Fig. 3 A and 3B as can be seen, using ultra-low energy ion to implant in the doping curve of the SSR surface channel that forms, because ion implantation energy becomes lower, so the distribution of delta doped becomes narrower.Because the delta doped of this narrow distribution shown in Fig. 3 A can significantly reduce the junction capacitance (junotion capacitance) of device and the leakage current of node (junction), so be the basic fundamental of making low power consumption and high efficiency semiconductor device.
Yet the shortcoming that ultra-low energy ion is implanted is the available energy quantitative limitation, because be difficult to extract enough ion beam currents in this ultra-low calorie scope, and manufacturing time is longer.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of manufacture method with semiconductor device of surface channel structure, it implants and need not use the method for the doping SSR surface channel that ultra-low energy ion implants to be fit to overcome the available energy quantitative limitation by providing with the boron fluoride compound ions, and is used to improve productivity ratio.
In addition, another object of the present invention provides a kind of manufacture method with semiconductor device of surface channel structure, is applicable to prevent in ion bombardment (ion bombarded) and fluoridize the crystal defect that epitaxial growth on the channel doping layer causes.
In one aspect of the invention, provide a kind of method that forms the surface channel of semiconductor device, may further comprise the steps: a), under the surface of Semiconductor substrate, formed channel doping layer by implanting the boron fluoride compound ions of boracic; B) carry out annealing process, the fluorine ion that removes in channel doping layer to be injected; C) carry out surface treatment, removing formed local oxide layer (native oxide layer) on the channel doping laminar surface, and remove simultaneously in the channel doping layer residual fluorine ion; And d) use selective epitaxial growth method (selective epitaxial growth method) at the channel doping layer growing epitaxial layers.
In another aspect of this invention, provide a kind of manufacture method of semiconductor device, may further comprise the steps: a), under the surface of Semiconductor substrate, formed channel doping layer by implanting the boron fluoride compound ions of boracic; B) carry out first annealing process, remove the fluorine ion that during above-mentioned channel doping is implanted, is infused in the channel doping layer; C) carry out process of surface treatment, remove the local oxide layer that forms on the surface of channel doping layer, and remove simultaneously on the channel doping layer residual fluorine ion; D) at the channel doping layer growing epitaxial layers; E) on epitaxial loayer, form gate dielectric and gate electrode successively; F) be formed on the source/drain extension area of the edge configuration of gate electrode, wherein the source/drain extension area is more shallow than channel doping layer; G) form the dividing plate (spacer) that contacts the gate electrode both sides; H) formation is configured in the source/drain regions of the edge of gate electrode dividing plate, and wherein source/drain regions is than channel doping layer depth; And i) carries out second annealing process, under the temperature that suppresses the channel doping layer diffusion, be used to activate the alloy that is comprised in source/drain extension area and the source/drain regions.
Description of drawings
With reference to the explanation of accompanying drawing to embodiment, other purpose of the present invention and aspect will become more apparent according to the summer literary composition, wherein:
Figure 1A is the drawing in side sectional elevation with semiconductor device of conventional surface channel;
Figure 1B is that the interior doping curve of surface channel is with TED or thermally equilibrated variation diagram;
Fig. 2 A and 2B are the figure of the method for semiconductor device with surface channel of (LTA) technology manufacturing of describing that ion with ultra-low calorie injects and LASER HEAT is annealed;
Fig. 3 A is the coordinate figure that is illustrated in the doping curve of the SSR surface channel that forms by use selective epitaxial growth method on the sample of implanting with 1keV boron ion;
Fig. 3 B is the coordinate figure that is illustrated in the doping curve of the SSR surface channel that forms by use selective epitaxial growth method on the sample of implanting with 5keV boron ion;
Fig. 4 works as B +Ion or 49BF 2 +The distribution map of ion boron concentration respectively in the implanted silicon substrate time;
Fig. 5 A to 5F illustrates the drawing in side sectional elevation of making the method for NMOSFET according to first embodiment of the invention;
Fig. 6 A to 6F illustrates the drawing in side sectional elevation of making the method for CMOSFET according to second embodiment of the invention;
Fig. 7 is the drawing in side sectional elevation according to the CMOSFET of third embodiment of the invention;
Fig. 8 is the drawing in side sectional elevation according to the CMOSFET of four embodiment of the invention;
Fig. 9 is the drawing in side sectional elevation according to the CMOSFET of fifth embodiment of the invention;
Figure 10 is the drawing in side sectional elevation according to the CMOSFET of sixth embodiment of the invention;
Figure 11 is the drawing in side sectional elevation according to the CMOSFET of seventh embodiment of the invention;
Figure 12 is wherein 49BF 2 +Ion is implanted the distribution map of the interior boron concentration of SSR surface channel of channel region.
Embodiment
Hereinafter with reference to the accompanying drawings the preferred embodiments of the invention are elaborated.
The invention provides a kind of method that the ion that is used to form channel doping layer (channel doping layer) is implanted energy that when forming the surface channel structure, increases, wherein use the molecular ion beam (molecular ion beam) that contains dopant ions.
The embodiment that hereinafter will describe is used from BF 3Extract in the gas 49BF 2 +Or 30BF +As the molecular ion beam that forms channel doping layer.
With boron (B +) ion implants and to compare, 49BF 2 +Ion is implanted has the same ion implantation depth of implanting energy at 4.5 times of ions.In addition, because can under 4.5 times of higher-energy, implant by ion, so manufacturing process can use general low energy ion implanted device to carry out, and need not any ultra-low energy ion implanted device.Further, implant under the energy in same ion, compare with the situation of boron ion, the ion implantation depth is more shallow, so the narrower delta doped of width has the characteristic that more can adjust.
Further, from BF 3Other kind ion of gas extraction is 30BF + 30BF +Ion is via using BF 3The ion beam quality analysis of gas and to select quality be 30 ions that extract. 30BF +Fluorine bond close number and be 49BF 2 +Half of ion.And, because 30BF +The fluorine implantation amount of ion is 49BF 2 +Half of ion is so can prevent that the fluorine compounds of finding because too much fluorine implants from precipitating and the generation of fluorine gas bubble (fluorine bubbles) after the subsequent thermal annealing process.
In addition, 30BF +It is identical that the ion implantation depth that ion is implanted and boron ion are implanted, and advantage is, 30BF +Ion is implanted can use than boron ion and is implanted high 2.7 times ion implantation energy.
Even the advantage that the ion of the molecular ion that extracts from fluorine compounds is implanted is to use the energy higher than boron ion, but the boron ion is implanted with fluorine ion inevitably, because 30BF +Ion is implanted and to be comprised fluorine ion, thus the fluorine-containing crystal defect that causes at follow-up outer layer growth of non-expectation, and can be owing at gate dielectric or the fluorine ion of accumulation at the interface between gate dielectric and Semiconductor substrate and civilian dress is put deterioration in characteristics.
Thereby, following embodiment is used the fluorine compounds ion, it is when forming channel doping layer, can use than macroion implantation energy and form shallow junction (shallow junction), and a kind of method is described, be used for being released in the fluorine ion that injected during the fluorine compounds ion is implanted to outside through following annealing process and process of surface treatment.
Fig. 4 represents to work as B +Ion or 49BF 2 +The boron concentration profile of Semiconductor substrate in the time of in the ion implanted silicon substrate.
In Fig. 4, trunnion axis is represented the degree of depth in the substrate, and vertical axis is represented boron concentration.Curve P3 and P4 represent B respectively +Or 49BF 2 +Situation.At this, the boron ion is implanted the acceleration energy and 1 * 10 with 5KeV 14Atom/cm 3Dosage carry out and BF 2 +Ion is implanted the acceleration energy and 1 * 10 with 5KeV 14Atom/cm 3Dosage carry out.
With reference to Fig. 4, in the boron ion was implanted, the boron ion was implanted to the substrate depths, and the peak Distribution of curve is in the position that is deeper than 10nm. 49BF 2 +Situation under, the peak Distribution of curve is at about 3nm place, and boron concentration reduces fast in darker position.
Curve P3 and P4 represent different decline curve mutually.Curve P4 has narrower boron and distributes.Comparison curves P3 and curve P4, the peak value of curve P4 is higher than P3.This means, 49BF 2 +Ion is implanted and is used less than boron (B +) the more small ion implantation amount of ion dose, can obtain identical or higher peak concentration.
The drawing in side sectional elevation of the method for NMOSFET is made in Fig. 5 A to 5F explanation according to first embodiment of the invention.
Shown in Fig. 5 A, the field oxide layer 32 that is used for the device isolation uses shallow slot ditch isolation STI technologies or silicon selective oxidation (LOCOS) technology to be formed at the predetermined portions of Semiconductor substrate 31.Then, P-type alloy is implanted to and forms dark P-type trap 33 in the Semiconductor substrate 31.Subsequently, implant P-type alloy, thereby form the P-type field stop layer (field stop layer) 34 more shallow than P-type trap 33.At this, boron (B) is used to form P-type trap 33 and P-type field stop layer as P-type alloy.
Then, as P-type alloy, such as 49BF 2 +Or 30BF +The molecular ion of fluorine compounds implanted, thereby form shallow P-type n-channel doping layer 35, its degree of depth is 10nm to 50nm apart from the surface of Semiconductor substrate 31.
At this moment, when implementing to be used to form the ion implantation of P-type n-channel doping layer 35, implant from BF 3Gas extraction 49BF 2 +Or 30BF +Molecular ion. 30BF +The implantation of molecular ion have and 49BF 2 +The similar effectiveness of molecular ion.In other words, its advantage is to use with the boron ion implants the same high ion implantation energy, makes to have the same ion implantation depth.In addition, the fluorine ion of being implanted be reduced to and 49BF 2 +The identical implantation amount of molecular ion 49BF 2 +Half of molecular ion.
Then, shown in Fig. 5 B, implement recovery annealing technology (recovery annealing process).Recovery annealing technology is replied the crystal defect (crystal defect) in the surface of Semiconductor substrate 31, and it is by being caused by ion bombardment in the ion that is used to form P-type n-channel doping layer 35 is implanted.And recovery annealing technology stably combines the alloy that is implanted in the P-type n-channel doping layer 35 with intracrystalline adjacent silicon atom, and discharges as SiF 4The fluorine of volatilization gas (F) ion is to outside.
For recovery annealing technology, implement (SRTA) technology of rapid thermal annealing (RTA) technology or peak value rapid thermal annealing (spike rapid thermal annealing) with the temperature below 1414 ℃ (fusing points of silicon), it can reply crystal defect, so that prevent to implant the alloy diffusion in the P-type n-channel doping layer 35.
At this, peak value rapid thermal annealing (SRTA) technology is represented a kind of annealing process (heating rate (rampingrate): 150 ℃/second or higher, time of delay (delay time): 1 second or littler), it is elevated to target temperature in the short time from room temperature, then without any lingeringly directly dropping to room temperature from target temperature.
Preferably, rapid thermal annealing (RTA) technology is implemented under 600 ℃ to 1050 ℃ temperature, and peak value rapid thermal annealing (SRTA) technology is implemented under 600 ℃ to 1100 ℃ temperature,
As a result, by recovery annealing technology, P-type n-channel doping layer 35 in conjunction with the alloy implanted and the silicon ion of Semiconductor substrate 31, and is improved the layer that becomes not have crystal defect by stably.In other words, fluorine (F) ion is released out during annealing process, and boron (B) is ion stabilizedly in conjunction with silicon (Si) ion.
As mentioned above, by recovery annealing technology, 35 activation of P-type n-channel doping layer are chemically stable very shallow P-type n-channel doping layer 35A.
Shown in Fig. 5 C, in nitrogen atmosphere, carry out surface treatment, so that remove local oxide layer (the native oxide layer) (not shown) that on shallow P-type n-channel doping layer 35A, is forming after the recovery annealing technology.Simultaneously, if in nitrogen atmosphere, carry out surface treatment, hydrogen (H 2) and local oxide layer (SiO 2) reaction and as H 2The O volatilization, thus remove the local oxide layer.And, it is desirable to, the surface-treated temperature is the temperature (as 600 ℃ to 950 ℃) that can prevent the alloy diffusion of existence in P-type n-channel doping layer 35.
In the above-mentioned surface treatment of carrying out under nitrogen atmosphere, fluorine (F) ion of staying after recovery annealing technology in the P-type n-channel doping layer 35A discharges as the HF form in addition.Simultaneously, exist 30BF +Molecular ion is implanted under the situation in the P-type n-channel doping layer 35, the fluorine ion of implantation be reduced to and 49BF 2 +Molecular ion has identical implantation amount 49BF 2 +Half of molecular ion, feasible easier removal fluorine ion.
As a result, when forming channel doping layer, implant with bigger relatively implantation amount and to have less fluorine content 30BF +Molecular ion, it is very effective to remove fluorine ion.
Shown in Fig. 5 D, epitaxial loayer 36 preferably on P-type n-channel doping layer 35, uses selective epitaxial growth (SEG) to grow to thickness and is 5nm to 30nm on the Semiconductor substrate 31 that does not have the local oxide layer.
As mentioned above, because P-type n-channel doping layer 35 activates into chemically stable very shallow P-type n-channel doping layer 35A via recovery annealing technology, even, also form the SSR surface channel structure that makes dopant loss and redistribute the minimized SSR of having delta doped curve so under nitrogen atmosphere, carry out the growing period of surface treatment and epitaxial loayer 36.
Shown in Fig. 5 E, gate dielectric layer 37 is formed on the SRR surface channel structure with 650 ℃ to 750 ℃ temperature, as is distributed on the epitaxial loayer 36 of bottom of P-type n-channel doping layer 35A.Simultaneously, the temperature range that is used to form gate dielectric layer 37 is very low, so that prevent the redistribution and the diffusion of the alloy that exists in P-type n-channel doping layer 35A.
Therefore, the stack layer (stack layer) of low temperature oxide (LTO) layer that forms at low temperature, silicon oxynitride (silicon oxynitride) layer, high dielectric substance layer or oxide skin(coating)/high dielectric substance layer is as gate dielectric layer 37.Owing to form the low thermal process of gate dielectric layer 37 at low temperatures, so can keep SSR doping curve by the redistribution and the diffusion of the alloy that prevents from P-type n-channel doping layer 35A, to exist.
For example, low temperature oxide layer (that is silicon thermal oxidation thing layer) forms under 650 ℃ to 750 ℃ temperature.Under 650 ℃ to 750 ℃ temperature, form silicon thermal oxidation thing layer (silicon thermal oxide layer) afterwards, by on silicon thermal oxidation thing layer, carrying out the nitride plasma or ammonia plasma treatment forms silicon oxynitride layer.High dielectric substance layer forms by following technology: carry out depositing operation under 300 ℃ to 650 ℃ temperature, under 400 ℃ to 700 ℃ temperature, carry out furnace annealing technology (furnaceannealing process) then, or under 300 ℃ to 650 ℃ temperature, carry out depositing operation, under 600 ℃ to 800 ℃ temperature, carry out rapid thermal anneal process then.Under the situation of using high dielectric substance layer, the maximum temperature when carrying out annealing process is restricted to 300 ℃ to 700 ℃, so that improve the layer quality (layer quality) of dielectric substance layer.
Then, the conductive layer deposition that is used for gate dielectric layer is in gate dielectric layer 37, and the conductive layer that patterning deposited, thereby forms gate electrode 38.At this, the conductive layer that is used to form gate electrode 38 can be polysilicon layer (polysilicon layer), the stack layer of polysilicon layer/metal level or the stack layer of polysilicon layer/silicide layer.
Then, utilize other photoresist mask (photoresist mask) (not shown) and gate electrode 38 to implant mask,, thereby form N-type source/drain extension area 39 with the N-type alloy of low-yield implantation implantation amount greatly as ion.Simultaneously, the N-type alloy that is used to form N-type source/drain extension area 39 is phosphorus (P) or arsenic (As).
Subsequently, be used to contain the insulating barrier of whole lip-deep dividing plate of gate electrode 38 in deposition after, the insulating barrier that is used for dividing plate by deep etch (etch back) to form the dividing plate 40 that contacts with the sidewall of gate electrode 38.At this, dividing plate uses nitride layer or oxide skin(coating).
Then, use other photoresist mask, gate electrode 38 and dividing plate 40 to implant mask as ion, the N-type alloy of implanting big implantation amount is to form N-type source/drain regions 41, and it is electrically connected to N-type source/drain extension area 39.Simultaneously, N-type source/drain regions 41 has the darker ion implantation depth of comparison N-type source/drain extension area 39.
Shown in Fig. 5 F, carry out activation annealing technology (activation annealing process) in N-type source/drain regions 41 and N-type source/drain extension area 39 so that the alloy that the electricity activation exists.Simultaneously, under predetermined temperature, carry out activation annealing technology, suppress the junction depth of P-type n-channel doping layer 35A diffusion and N-type source/drain regions 41 and N-type source/drain extension area 39 simultaneously and deepen.
Preferably, activation annealing technology is selected from: 600 ℃ to 1000 ℃ rapid thermal annealing (RTA) technology, 300 ℃ to 750 ℃ furnace annealing technology, 600 ℃ to 1100 ℃ peak value rapid thermal annealing (SRTA) technology and combination thereof.
Simultaneously, undertaken by low temperature process, then can keep wherein suppressing the SSR surface channel structure of alloy diffusion with low heat balance if form the technology of gate electrode 38 and N-type source/drain regions 41.
In the above-described embodiment, P-type n-channel doping layer 35A also as prevent short-channel effect only wear the layer (a punch stop layer).In addition, by forming the maximum doping depth of the P-type n-channel doping layer 35A more shallow, and reduce the junction capacitance (junctioncapacitance) and the junction leakage (junction leakage current) of NP knot than N-type source/drain regions 41.
Fig. 6 A to 6F is a drawing in side sectional elevation of making the method for CMOSFET according to second embodiment of the invention.
As shown in Figure 6A, use shallow trench isolation on the predetermined portions of Semiconductor substrate 51, to be formed for the field oxide layer 52 of device isolation from (STI) technology or silicon selective oxidation (LOCOS) technology.Then, use exposure and developing process is coated on photoresist on the Semiconductor substrate 51 and with its patterning, thereby form first mask 53, the zone (hereinafter being called " PMOS " zone) that is used to expose and will form PMOSFET.
Then, in the implanted Semiconductor substrate 51 of N-type alloy such as phosphorus (P), thereby form dark N-type trap 54 by mask 53 exposures.Implant N-type alloy successively and form the N-type field stop layer 55 more shallow than N-type trap 54.
Then, implant the energy implantation N-type alloy of energy to be lower than the ion that forms N-type field stop layer 55, and form shallow N-type p-channel doping layer 56, its degree of depth is 10nm to 50nm from the surface of Semiconductor substrate 51.Simultaneously, use phosphorus (P) or arsenic (As) as N-type alloy.
Shown in Fig. 6 B, after removing first mask 53, re-use exposure and developing process is coated on photoresist on the Semiconductor substrate 51 and with its patterning, thereby form second mask 57, the zone (hereinafter being called " NMOS " district) that is used to expose and will form NMOSFET.
Then, P-type alloy is implanted in the Semiconductor substrate 51 of exposing by second mask 57, thereby forms dark P-type trap 58.Implant P-type alloy successively to form the P-type field stop layer 59 more shallow than P-type trap 54.At this moment, boron (B) is used as P-type alloy.
Then, implant fluorine compounds such as 49BF 2 +Or 30BF +Molecular ion, thereby form shallow P-type n-channel doping layer 60, its degree of depth is 10nm to 50nm apart from Semiconductor substrate 51 surfaces.
Shown in Fig. 6 C, after removing second mask 57, carry out recovery annealing technology.Recovery annealing technology is replied the crystal defect in Semiconductor substrate 51 surfaces, and the ion bombardment during this defective is implanted by the ion that is used to form N-type p-channel doping layer 56 and P-type n-channel doping layer 60 is caused.And, recovery annealing technology stably combines the alloy that is implanted in N-type p-channel doping layer 56 and the P-type n-channel doping layer 60 with intracrystalline adjacent silicon atom, and fluorine (F) ion that will be implanted in the P-type n-channel doping layer 60 is discharged into the outside.
For recovery annealing technology, under the temperature that is lower than 1414 ℃ (fusing points of silicon), carry out rapid thermal annealing (RTA) technology or peak value rapid thermal annealing (SRTA) technology, it can reply crystal defect, so that avoid being implanted to the alloy diffusion in N-type p-channel doping layer 56 and the P-type n-channel doping layer 60.Preferably, rapid thermal annealing (RTA) technology is carried out under 600 ℃ to 1050 ℃ temperature, and peak value rapid thermal annealing (SRTA) technology is carried out under 600 ℃ to 1100 ℃ temperature.
As mentioned above, by recovery annealing technology, N-type p-channel doping layer 56 and P-type n-channel doping layer 60 are improved the layer that becomes not have defective by the silicon ion in conjunction with the alloy implanted and Semiconductor substrate stably.Especially, in P-type n-channel doping layer 60, during annealing process, discharge fluorine (F) ion, and boron (B) ion combines ion stabilizedly with silicon (Si).
As a result, after recovery annealing technology, N-type p-channel doping layer 56 and 35 activation of P-type n-channel doping layer are very shallow N-type p-channel doping layer 56A and very shallow P-type n-channel doping layer, and their chemical property is stable.
Shown in Fig. 6 D, after recovery annealing technology, in nitrogen atmosphere, carry out surface treatment, so that remove formed local oxide layer (not shown) on N-type p-channel doping layer 56A that does not have crystal defect during the recovery annealing technology and P-type n-channel doping layer 60A.Simultaneously, if in nitrogen atmosphere, carry out surface treatment, hydrogen (H 2) and local oxide layer (SiO 2) reaction is with as H 2The O volatilization makes the local oxide layer be removed.In addition, even after recovery annealing technology, fluorine (F) ion of staying in the P-type n-channel doping layer 60A is released out in addition.
Shown in Fig. 6 E, use selective epitaxial growth (SEG) on N-type p-channel doping layer 56A that does not have the local oxide layer and P-type n-channel doping layer 60A, epitaxial loayer 61 and 62 side by side to be grown to the thickness of 5nm to 30nm.
As indicated above, because N-type p-channel doping layer 56 and P-type n-channel doping layer 60 become stable very shallow N-type p-channel doping layer 56A of chemical property and very shallow P-type n-channel doping layer 60A by the recovery annealing activation processes, even so growing period of the surface treatment under nitrogen atmosphere and epitaxial loayer 61 and 62, formation has the SSR surface channel structure that the SSR delta doped distributes, and wherein dopant loss and the redistribution in nmos area and PMOS district minimizes.
Shown in Fig. 6 F, gate dielectric layer 63 is formed at SSR surface channel structure under 650 ℃ to 750 ℃ temperature, on N-type p-channel doping layer 56A and P-type n-channel doping layer 60A.At this moment, the temperature range that is used to form gate dielectric layer 63 is lower, thereby is suppressed at the diffusion of existing alloy in the P-type n-channel doping layer 60A.
Therefore, the stack layer of low temperature oxide (LTO) layer, silicon oxynitride layer, high dielectric substance layer or oxide skin(coating)/high dielectric substance layer is as gate dielectric layer 63.Because in the low thermal process of low temperature formation gate dielectric layer 63, can keep the SSR dopant profiles by redistribution and the diffusion that prevents existing alloy in N-type p-channel doping layer 56A and the P-type n-channel doping layer 60A.
For example, under 650 ℃ to 750 ℃ temperature, form silicon thermal oxidation thing layer.After forming silicon thermal oxidation thing layer, by on silicon thermal oxidation thing layer, carrying out the nitride plasma or ammonia plasma treatment forms silicon oxynitride layer with 650 ℃ to 750 ℃ temperature.High dielectric substance layer forms by following technology: carry out depositing operation under 300 ℃ to 650 ℃ temperature, carry out furnace annealing technology under 400 ℃ to 700 ℃ the temperature then, or under 300 ℃ to 650 ℃ temperature, carry out depositing operation, carry out rapid thermal anneal process 600 ℃ to 800 ℃ temperature then.Under the situation of using high dielectric substance layer, maximum temperature is limited in 300 ℃ to 700 ℃ when carrying out annealing process, so that improve the layer quality of dielectric substance layer.
Then, the conductive layer deposition that is used for gate dielectric layer is in gate dielectric layer 63, and the conductive layer that patterning deposited, thereby forms gate electrode 64.Then, to PMOS district and nmos area, use other photoresist mask (not shown) and gate dielectric layer 64 to implant mask, implant in the PMOS district, thereby form P-type source/drain extension area 65 with low-yield P-type alloy with implantation amount greatly as ion separately.Be implanted in the nmos area with low-yield N-type alloy, thereby form N-type source/drain extension area 66 implantation amount greatly.
At this, the conductive layer that forms gate electrode 64 can be the stack layer of polysilicon layer, polysilicon layer/metal level or the stack layer of polysilicon layer/silicide layer.In addition, the N-type alloy that is used to form N-type source/drain extension area 66 is phosphorus (P) or arsenic (As), and the P-type alloy that is used to form P-type source/drain extension area 65 is boron (B), BF 2Or the boron compound ion of boracic.
Sequentially, after containing on the whole surface of gate electrode 64 deposition and being used for the insulating barrier of dividing plate, the insulating barrier that is used for dividing plate by deep etch to form the dividing plate 67 that contacts with gate electrode 64 sidewalls.Herein, dividing plate uses the combination of nitride layer, oxide skin(coating) or nitride layer and oxide skin(coating).
Then, use other photoresist mask, gate electrode 64 and dividing plate 67 to implant mask as ion, the P-type alloy (boron or boron compound) of implantation amount greatly is implanted in the PMOS district, forms P-type source/drain regions 68, it is electrically connected on the P-type source/drain extension area 65.
In addition, use other photoresist mask, gate electrode 64 and dividing plate 67 to implant mask as ion, it is interior to form N-type source/drain regions 69 that the N-type alloy (phosphorus or arsenic) of implantation amount is greatly implanted nmos area, and it is electrically connected on the P-type source/drain extension area 66.
At this moment, N-type source/drain regions 69 and P-type source/drain regions 68 have the ion implantation depth darker than N-type source/drain extension area 66 and P-type source/drain extension area 65 respectively.
Then, carry out activation annealing technology, so that the electricity activation is implanted to the alloy in N-type source/drain regions 69, N-type source/drain extension area 66, P-type source/drain regions 68 and the P-type source/drain extension area 65.
Simultaneously, under predetermined temperature, carry out activation annealing technology, suppress P-type source/ drain regions 68 and 65 intensifications of P-type source/drain extension area simultaneously.
Reason is, P-type source/drain regions 68 and P-type source/drain extension area 65 have than N-type source/drain regions 69 and the 66 more serious diffusions of N-type source/drain extension area and change.
Preferably, activation annealing technology is selected from: 600 ℃ to 1000 ℃ rapid thermal annealing (RTA) technology, 300 ℃ to 750 ℃ furnace annealing technology, 600 ℃ to 1100 ℃ peak value rapid thermal annealing (SRTA) technology and combination thereof.
Simultaneously, carry out the SSR surface channel structure that then can keep wherein alloy diffusion to be suppressed by low temperature process with low heat balance if form the technology of gate electrode 64, P-type source/drain extension area 65, N-type source/drain extension area 66, P-type source/drain regions 68 and N-type source/drain regions 69.
In above-mentioned second embodiment, N-type p-channel doping layer 56A and P-type n-channel doping layer 60A also only wear layer as what prevent short-channel effect.In addition, by forming, reduce the junction capacitance and the junction leakage current of coming PN junction and NP knot than shallow N-type p-channel doping layer 56B of P-type source/drain regions 68 and N-type source/drain regions 69 and the maximum separately doping depth of P-type n-channel doping layer 60A.
Fig. 7 is the drawing in side sectional elevation according to the CMOSFET of third embodiment of the invention.The CMOSFET of Fig. 7 except a N-type only wear the layer the 70, the 2nd a N-type only wear the layer the 72, the one a P-type only wear the layer the 71 and the 2nd a P-type only wear the layer 73, have the structure identical with second embodiment.Hereinafter, in Fig. 7, use with Fig. 6 F in identical label, and the detailed description of its same section omission.
According to the above-mentioned second embodiment same way as, in the PMOS district, form the surface channel structure.Surface channel comprises by implanting phosphorus or the formed N-type of arsenic ion only to be worn layer 70 and only wears the epitaxial loayer 61 of growth on the layer 70 in a N-type.Simultaneously, on nmos area, form surface channel.Surface channel comprises by implanting the P-type that the fluorine compounds ion forms only to be worn layer 71 and only wears the epitaxial loayer 62 of growth on the layer 71 in a P-type.
Then, the 2nd N-type is only worn layer the 72 and the 2nd a P-type and is only worn layer and 73 be respectively formed on the lower part of P-type source/drain extension area 65 and N-type source/drain extension area 66.At this moment, only wear layer 70 equal N-type alloys (phosphorus or arsenic) formation the 2nd a N-type by an implantation and a N-type and only wear layer 72.Simultaneously, be different from a P-type that forms by boron implant-fluorine compounds and only wear layer 71, form the 2nd P-type by boron implant or boron compound and only wear layer 73.
At this, only wear layer the 72 and the 2nd a P-type and only wear layer 73 in order on the lower part of P-type source/drain extension area 65 and N-type source/drain extension area 66, to form the 2nd N-type respectively, before forming P-type source/drain regions 68 and N-type source/drain regions 69, carry out ion implantation technology.
The one P-type is only worn layer the 71 and the one N-type and is only worn layer 70 as preventing the channel doping layer of short-channel effect and only wearing layer.
As a result, the CMOSFET according to the 3rd embodiment of the present invention has two layer structure of only wearing.Competitive list is only worn a layer structure, twoly only wears break-through (punch-through) characteristic that layer structure has improvement.
Fig. 8 is the drawing in side sectional elevation according to the CMOSFET of the 4th embodiment of the present invention.The CMOSFET of Fig. 8 has the structure identical with the 3rd embodiment except the source/drain regions that raises.Hereinafter, use the label identical among Fig. 8 with Fig. 6 F, and the detailed description of omitting relevant same section.
With reference to Fig. 8, according to the mode identical with the 3rd embodiment, have a N-type that is included in the PMOS district according to the CMOSFET of the 4th embodiment and only wear floor 70 and the 2nd N-type and only wear the two of floor 72 and only wear floor structure, and a P-type that is included on the nmos area is only worn two layer structure of only wearing that layer the 71 and the 2nd P-type only worn layer 73.In addition, epitaxial loayer growth on P-type source/drain regions 68 and N-type source/drain regions 69 respectively, thus form the source/ drain regions 74 and 75 that raises.
In the 4th embodiment of Fig. 8, improve the break-through characteristic by two layers of only wearing of implanting via the ion of boron fluorine compounds are provided, and prevent the increase of the junction resistance of source/drain by the source that rising is provided.
Fig. 9 is the drawing in side sectional elevation according to the CMOSFET of the 5th embodiment of the present invention.
With reference to Fig. 9, N-type trap 83 and P-type trap 84 form in the Semiconductor substrate 81 with field oxide layer 82 defined PMOS districts and nmos area respectively.N-type field stop layer 85 forms on the part more shallow than N-type trap 83, and P-type field stop layer 86 forms on the part more shallow than P-type trap 84.
Gate dielectric layer 87, polysilicon layer 88, metal level 89 and hard mask 90 sequentially are formed on the PMOS and nmos area in Semiconductor substrate 81 districts, thereby form stacked gate architectures.Then, on the two side of the polysilicon layer 88 that constitutes grid structure, form side wall layer 88 respectively.On the two side of grid structure, form dividing plate 92.
The gate dielectric layer of surface channel in the PMOS district with N-type p-channel doping layer 93 and epitaxial loayer 94 forms for 87 times, and has the gate dielectric layer 87 time formation of the surface channel of P-type n-channel doping layer 93 and epitaxial loayer 96 at nmos area.
P-type source/drain extension area 97 forms on the both sides of the surface channel in PMOS district, and the P-type source/drain regions 98 that contacts with P-type source/drain extension area 97 is forming than P-type source/drain extension area 97 darker junction depth places.N-type source/drain extension area 99 forms on the both sides of the surface channel of nmos area, and the P-type source/drain regions 100 that contacts with N-type source/drain extension area 99 is forming than N-type source/drain extension area 99 darker junction depth places.
In Fig. 9, the metal level 89 that forms on polysilicon layer 88 is applicable to the resistance (resistivity) and the high speed operation of gate electrode, and uses tungsten and tungsten silicide usually.In addition, diffusion barrier (diffusion barrier layer) can be inserted between polysilicon layer 88 and the metal level 89.
The sidewall oxide layer 91 that forms on the two side of polysilicon layer 88 utilizes gate re-ox technology to come oxidation polysilicon layer 88 and form, and is used to reply the gate dielectric layer 87 that is damaged during the etch process of grid structure being used to form.As everyone knows, carry out gate re-ox technology so that improve reliability, described improvement is to be undertaken by the thickness that the microflute ditch (microtrench) of replying the gate dielectric layer 87 that causes when the etch-gate electrode and loss, oxidation are stayed gate dielectric layer 87 lip-deep etch residue materials (etching remaining material) and be increased in the gate dielectric layer 87 of gate electrode edge formation.
Carry out gate re-ox technology, so that prevent to be implanted to the alloy in the P-type n-channel doping layer 95 because excessively thermal process (excessive thermal process) spreads the SSR doping curve destruction of causing.Simultaneously, if utilize rapid thermal oxidation (RTO) to carry out thermal oxidation technology such as reoxidizing technology, its maximum temperature is limited in 750 ℃ to 950 ℃.Simultaneously, if utilize furnace annealing technology to carry out thermal oxidation technology, then its maximum temperature is limited in 650 ℃ to 800 ℃.
As mentioned above, if utilize the low temperature process with low heat balance to carry out gate re-ox technology, then can keeping wherein, alloy spreads downtrod SSR surface channel structure.
In the 5th embodiment of Fig. 9, N-type p-channel doping layer 93 and P-type n-channel doping layer 95 are also only worn layer as what prevent short-channel effect.In addition, by forming than the more shallow N-type p-channel doping layer 93 of P-type source/drain regions 98 and N-type source/drain regions 100 and each maximum doping depth of P-type n-channel doping layer 95, the junction capacitance and the junction leakage current of PN junction and NP knot are reduced.
Figure 10 is the drawing in side sectional elevation according to the CMOSFET of the 6th embodiment of the present invention.
The CMOSFET of Figure 10 has a N-type that is included in the PMOS district and only wears floor 93 and the 2nd N-type and only wear the two of floor 101 and only wear floor structure, comprises that the P-type on the nmos area is only worn two layer structure of only wearing that layer the 95 and the 2nd P-type only worn layer 102.The CMOSFET of other structure and Fig. 9 is identical.
Figure 11 is the drawing in side sectional elevation according to the CMOSFET of seventh embodiment of the invention.
The CMOSFET of Figure 11 has a N-type that is included in the PMOS district and only wears floor 93 and the 2nd N-type and only wear the two of floor 101 and only wear floor structure, and a P-type that is included on the nmos area is only worn two layer structure of only wearing that layer the 95 and the 2nd P-type only worn layer 102.In addition, epitaxial loayer is grown in respectively on P-type source/drain regions 98 and the N-type source/drain regions 100, thereby forms the source/drain regions 103 and 104 that raises.Other structure is identical with the CMOSFET of Fig. 9 and Figure 10.
When first to the 7th embodiment is made NMOSFET and CMOSFET according to the present invention, in order to prevent that SSR doping curve is owing to the diffusion of the alloy in the channel doping layer destroys, alloy diffusion is to be caused by the excessive thermal process that forms during the subsequent technique that SSR surface channel structure carries out afterwards, so the maximum temperature in follow-up rta technique is limited in 600 ℃ to 1000 ℃.In addition, the maximum temperature in follow-up peak value rapid thermal anneal process is limited in 600 ℃ to 1100 ℃, and is limited in 300 ℃ to 750 ℃ in the maximum temperature of follow-up furnace annealing technology.
Simultaneously, though in the present invention's first to the 5th embodiment, the semiconductor device with source/drain extension area has been described, the present invention also can be applicable to have light dope (lightly doped) drain electrode (LDD) structure semiconductor device.
Figure 12 is implanted at channel region 49BF 2 +The boron concentration profile of the SSR surface channel of ion.Figure 12 is illustrated in to finish and makes the required whole thermal process of semiconductor device such as the gate oxidation after forming source/drain and the result of peak value rapid thermal anneal process.Trunnion axis is illustrated in the degree of depth in the substrate, and vertical axis is represented boron concentration.Curve P5 is with 2 * 10 13Atom/cm 3Dosage and 5KeV acceleration energy are implanted 49BF 2 +The result that ion obtained, and curve P6 is with 2 * 10 13Atom/cm 3Dosage and 10KeV acceleration energy implant 49BF 2 +The result that ion obtained.
With reference to Figure 12, implanting 49BF 2 +During ion, the peak value of concentration is positioned at about 30nm, and boron concentration reduces apace in dark position.
Curve P5 and P6 have different reduction curve mutually.Curve P5 has narrower boron diffusion, and the peak value of curve P5 is higher than the peak value of curve P6.
Because the present invention can easily implement to have the super shallow SSR channel structure of the narrow width of delta doped curve, so can realize high speed device by the junction capacitance that reduces inferior 100nm level device.
In addition, compare, use the low-energy boron ion to implant and to improve productivity, so can low-costly make high performance device with the SSR doping method.The present invention can prevent because alloy is induced (induced) and the change of the limit voltage that causes and prevent the short-channel effect of inferior 10nm grid length simultaneously at random, thereby improves the productivity ratio of device.
Compare with the Cmax of channel doping layer, the concentration of dopant of channel surface area can be reduced to 1/100 or lower, thereby has improved surface migration and drive current characteristic.
In addition, owing to carry out super shallow SSR channel structure easily, realize having the voltage devices of low critical voltage and low energy consumption easily.
Though only certain preferred embodiments has been described in detail the present invention relatively, under the situation that departs from claims spirit and scope required for protection, can make other change and modification to the present invention.

Claims (17)

1. method that forms the surface channel of semiconductor device comprises the following step:
A) by implanting the boron fluoride compound ions of boracic, under the surface of Semiconductor substrate, form channel doping layer;
B) carry out annealing process to remove the fluorine ion that during above-mentioned ion is implanted, is injected in this channel doping layer;
C) carry out process of surface treatment to remove formed local oxide layer on the channel doping laminar surface, remove institute's remaining fluorine ions in this channel doping layer simultaneously; And
D) utilize the selective epitaxial growth method, at this channel doping layer growing epitaxial layers.
2. method as claimed in claim 1, wherein the fluorine compounds ion of this boracic comprises 49BF 2 +Or 30BF +
3. method as claimed in claim 1, wherein step b) is a kind of in rapid thermal anneal process or the peak value rapid thermal anneal process.
4. method as claimed in claim 3, wherein rapid thermal anneal process carries out under 600 ℃ to 1050 ℃ temperature, and this peak value rapid thermal anneal process carries out under 600 ℃ to 1l00 ℃ temperature.
5. method as claimed in claim 1, wherein step c) is carried out in the atmosphere of hydrogen.
6. method of making semiconductor device comprises the following step:
A) by implanting the boron fluoride compound ions of boracic, under the surface of Semiconductor substrate, form channel doping layer;
B) carry out first annealing process to remove the fluorine ion that during above-mentioned ion is implanted, in this channel doping layer, injects;
C) carry out process of surface treatment to remove the local oxide layer that on the surface of channel doping layer, forms, remove institute's remaining fluorine ions in this channel doping layer simultaneously;
D) at this channel doping layer growing epitaxial layers;
E) on epitaxial loayer, sequentially form gate dielectric and gate electrode;
F) be formed on the source/drain extension area that gate electrode edge aligns, wherein this source/drain extension area is more shallow than channel doping layer;
G) dividing plate of formation and gate electrode contact both sides;
H) be formed on the source/drain regions of the separator edge place alignment of gate electrode, wherein the source/drain extension area is than channel doping layer depth; And
I) carry out second annealing process, under the temperature of restraining the channel doping layer diffusion, contained alloy in activation source/drain extension area and the source/drain regions.
7. method as claimed in claim 6 further comprises: after step f), form the step of only wearing doped layer under the source/drain extension area, its termination is worn doped layer and is contacted with channel doping layer.
8. method as claimed in claim 7 wherein forms by the boron implant ion and only wears doped layer.
9. method as claimed in claim 6, wherein step b) is a kind of in rapid thermal anneal process or the peak value rapid thermal anneal process.
10. method as claimed in claim 9, wherein rapid thermal anneal process carries out under 600 ℃ to 1050 ℃ temperature, and the peak value rapid thermal anneal process carries out under 600 ℃ to 1100 ℃ temperature.
11. method as claimed in claim 6, wherein the boron fluoride compound ions of boracic comprises 49BF 2 +With 30BF +
12. method as claimed in claim 6, wherein the second activation annealing technology is selected from 600 ℃ to 1000 ℃ rapid thermal anneal process, 300 ℃ to 750 ℃ furnace annealing technology, 600 ℃ to 1100 ℃ peak value rapid thermal anneal process and combination thereof.
13. method as claimed in claim 6 further comprises: in this step I) step of the source/drain regions that selective growth raises on source/drain regions afterwards.
14. method as claimed in claim 6, wherein step e) further comprises: after forming gate electrode, and the step that the gate dielectric of exposure is reoxidized.
15., wherein use maximum temperature to be limited in the step that quick method for oxidation in 750 ℃ to 950 ℃ the scope reoxidizes gate dielectric as the method for claim 14.
16. as the method for claim 14, the step that wherein reoxidizes gate dielectric is to be undertaken by the thermal oxidation process of using maximum temperature to be limited in 750 ℃ to the 950 ℃ stoves in the scope.
17. method as claimed in claim 6, wherein step c) is carried out under the atmosphere of hydrogen.
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