JPH0415950A - Complementary field-effect semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a complementary field effect semiconductor device in which a leakage current is suppressed by disposing a crystal defect layer generated upon recrystallization of an amorphous layer at a deeper position than a depleted layer extended from a PN junction between a P-well or N-well and a substrate into the substrate. CONSTITUTION:A depleted layer of a junction between a P-well 5, an N<+> type buried diffused layer 2 and an N-well 6, a junction between a source and a drain is extended, but since the depleted layer of the source, drain is disposed in the P-well, a crystal defect layer 7 generated upon formation of amorphous state does not exist therein, and does not affect an influence to the junction characteristics of the source, the drain. The depleted layer of the well junction is extended into the well 5, the well 6 and the layer 2, but the depth W1 of the layer 7 is set deeper than the depth (depth of the deeper depleted layer end) W2 of the depleted layer end extended from the well junction into the layer 2. The layer 7 does not exist in the depleted layer of a well junction and does not affect the junction characteristics of the well junction.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a complementary field-effect semiconductor device having a reverse slope well (retrograde well) structure and a current-voltage characteristic with suppressed leakage current, and a complementary field effect semiconductor device thereof. This relates to a manufacturing method.

[Prior Art] In recent years, research on further miniaturization of LSIs has been progressing toward higher integration and higher performance. Among MO3LSIs that are superior in terms of high integration, complementary MOSLSIs (CMOSLSIs), which have extremely low power consumption, are mainstream. In CMO8, N channel MO3FET and P
Since it is necessary to manufacture the channel MO3FET on the same silicon substrate, island-like regions (wells) of different conductivity types are formed on the silicon substrate. High integration.

As miniaturization advances toward higher performance, a parasitic bipolar effect via the well, a so-called latch-up phenomenon, occurs, causing the LSI to stop operating. For this reason, a CMOS device with high latch-up resistance is used as a highly integrated CMOS device.
This is important in realizing LSI. In order to increase the latch-up resistance, it is effective to use a reverse slope well (retrograde well) structure in which the impurity concentration increases from the surface toward the back. This retrograde well structure is obtained by introducing impurities by ion implantation at high energy so that the peak concentration is located deep.

[Problems to be Solved by the Invention] However, when ion implantation is performed, damage is introduced into the silicon substrate, so depending on the ion implantation conditions, a crystal defect layer is generated at a slightly shallower depth than the depth that provides the peak concentration. When such a crystal defect layer occurs, it affects the characteristics of the MOS FET manufactured in the well, and particularly causes an increase in leakage current at the source and drain junctions. For this reason, it is necessary to set ion implantation conditions such that crystal defect layers do not occur, and it is not possible to freely control the impurity concentration distribution, which is the original purpose of ion implantation, and it is necessary to design the concentration distribution necessary for device characteristics. The problem was that it was not possible.

Therefore, an object of the present invention is to solve the problem of the conventional reverse tilt well M design and to provide a complementary field effect semiconductor device with suppressed leakage current and a method of manufacturing the same.

[Means for Solving the Problems] In order to solve these problems, a complementary field effect semiconductor device according to the present invention includes an N-channel field effect transistor formed in a P-well and a P-channel field-effect transistor formed in an N-well. In a complementary field effect semiconductor device consisting of a field effect transistor, a crystal defect layer generated due to recrystallization of an amorphous layer is formed at a position deeper than a depletion layer extending into the substrate from a PN junction between the P well or N well and the substrate. This is what was placed.

Other complementary field effect semiconductor devices according to the present invention include an N channel field effect transistor formed in a P well and a P channel field effect transistor formed in an N well. An amorphous layer occurs due to recrystallization at a position shallower than the depletion layer extending into the well from the PN junction between the PN junction and the substrate, and deeper than the depletion layer extending into the well from the source and drain junctions of the field effect transistor formed in the well. A crystal defect layer is arranged.

The method for manufacturing a complementary field effect semiconductor device according to the present invention includes:
A first method of ion-implanting inert first ions that do not affect the electrical characteristics of the semiconductor to form an amorphous layer before or after ion implantation for forming a well of a complementary field-effect semiconductor device. a second step of ion-implanting electrically active second ions for well formation, and recrystallization of the amorphous layer and activation of the impurity introduced by the second ion implantation. and a third step of performing chemical heat treatment.

Another method of manufacturing a complementary field effect semiconductor device according to the present invention includes implanting an inert material that does not affect the electrical characteristics of the semiconductor before or after ion implantation for forming a well of the complementary field effect semiconductor device. A first step of implanting first ions to form an amorphous layer, a second step of implanting electrically active second ions for forming a well, and a second step of implanting the amorphous layer. a third step of performing recrystallization and heat treatment for activating the impurities introduced by the second ion implantation, and the implantation energy of the first ion implantation is:
When the depth of the crystal defect layer generated when the amorphous layer formed by the ion implantation is recrystallized matches the depth of the depletion layer extending into the substrate from the PN junction between the well and the substrate. This is greater than the implantation energy.

[Function] In the present invention, at least a portion of the region to become a well is made amorphous before or after the ion implantation of impurities for well formation, so that retrofitting without the influence of crystal defect layers can be achieved. Achieving a grade well structure,
Prevents crystal defects from occurring at depths that affect device characteristics.

[Example] Embodiments of the present invention will be described in detail below using one drawing.

FIGS. 1(a) to 1(f) are cross-sectional views illustrating the structure of an embodiment of a complementary field effect semiconductor device according to the present invention using a complementary MO3LSI manufacturing method. In the figure, ■ is an N-type Si substrate, 2 is an N1 buried diffusion layer, 3 is an N-3i layer formed by epitaxial growth, 4 is an amorphous layer, 5 is a P well, 6 is an N well, and 7 is a A crystal defect layer accompanying ion implantation for forming the amorphous layer 4,
8 is a field oxide film, 9 is a gate oxide film, 1° is a low resistance polycrystalline silicon gate electrode, 11 is a high concentration N type (N+
) layer (source and drain of NMO3FET), 12 is a high concentration P type (P+) layer (source and train of PMO8FET), 13 is an insulating film between the eyebrows, and 14 is an A1 electrode.

First, as shown in FIG. 1(a), an N+
A buried diffusion layer 2 is formed by a thermal oxidation method. In this example, a diffusion layer of arsenic (As) was formed. Next, an N-5i layer 3 having a thickness of 13 μm is formed by epitaxial growth. Next, as shown in FIG. 1(b), prior to ion implantation for well formation, Si ions are implanted, and N S
The entire region of the i-layer 3 and a portion of the N+ buried diffusion layer 2 are made amorphous to form an amorphous layer 4. In this example, S
The i-ion implantation conditions are as follows: 150KeV 2x10"cm"2,5
00KeV, 3x ], O"cm -21MeV, 4x
Ion implantation was performed under the condition of l()15 cm-2. Under these conditions, the amorphous layer 4 can be formed over the entire region from the surface to a depth of 1.5.4 zm. That is, the interface between the amorphous layer 4 and the single crystal exists in the N″″ buried diffusion layer 2. Of course, if the desired region to be amorphized is shallow, a single ion implantation with a predetermined implant energy and implantation violet may be used. When performing ion implantation using two or more types of implantation energies (multistage ion implantation) as in this example,
The maximum implantation energy determines the depth of the amorphous layer from the Si surface. Furthermore, many types of ions may be used in multi-stage ion implantation. Next, as shown in FIG. 1(c), ion implantation is performed to form a well. NMOS
A P well 5 is formed by boron (B) ion implantation in the region where the FET is to be formed, and an N well 6 is formed by phosphorus (P) ion implantation in the region where the PMO3FET is to be formed.
form. The ion implantation conditions may be freely selected in consideration of the desired impurity concentration distribution. In this embodiment, for example, B is set at 500 KeV.

5x10"cm-2, P at 900KeV, 5x101
Ions were implanted at 3 cm-2 to form a retrograde well with a peak concentration at a depth of 1 m from the surface. After the ion implantation, annealing is performed at 900° C. for 30 minutes in a nitrogen atmosphere, for example, to activate the implanted impurities for well formation and recrystallize the amorphous layer 4. Through this annealing, the amorphous layer 4 becomes a single crystal layer, and a crystal defect layer 7 is formed near the interface between the original amorphous layer and the single crystal due to ion implantation to form the amorphous layer. Ru. In this example, since the interface between the amorphous layer and the single crystal is located in the N buried diffusion layer 2, the crystal defect layer 7 caused by ion implantation to form the amorphous layer is is located in the N+ buried diffusion layer 2. This crystal defect layer 7
The influence on device characteristics will be explained in detail later. In this example, the case where ion implantation for well formation is performed after amorphization with Si ions has been described, but ion implantation for well formation is performed first, and then Si ion implantation is performed. A similar effect can be obtained by making it amorphous. Next, as shown in FIG. 1(d), after forming a field oxide film 8 with a thickness of 5000, B is ionized into the P well and P is ionized into the N well in order to adjust the impurity concentration in the channel region. inject. The ion implantation conditions are determined based on the characteristics such as the threshold voltage of the MOSFET to be obtained. After that, in a nitrogen atmosphere, 900
After annealing at 30° C. for 30 minutes, oxidation is performed in a dry oxygen atmosphere to form a gate oxide film 9. In this example, the thickness of gate oxide film 9 was 100. Thereafter, as shown in FIG. 1(e), low-resistance polycrystalline silicon to be used as a gate electrode is deposited to a thickness of 3000 nm, and a gate electrode 10 is formed using ordinary photolithography or electron beam lithography. Next, in order to form an N+P junction and a P''N junction to be used as a source/drain, for example, a photoresist is used as a mask for ion implantation, and As is applied to the NMOSFET part at 40 KeV and 4
B is ion-implanted into the PMOSFET part under the conditions of
By performing annealing for 0 minutes, high concentration N type (N1)
layer 11 (source and drain of NMOSFET), high concentration P type (P+) layer 12 (source of PMO3FET).

train) is formed. Thereafter, as shown in FIG. 1(f), an interlayer insulating film 1B and an AI electrode 14 are formed according to the usual MO3LSI manufacturing process, and a complementary field effect semiconductor device is manufactured.

When an amorphous layer is formed by ion implantation as shown in FIGS. 1(e), (d), (e), and (f), after annealing,
A crystal defect layer 7 is generated near the interface between the amorphous layer and the single crystal. When this crystal defect layer 7 is in the depletion layer, it acts as a production recombination center, resulting in an increase in leakage current in the reverse direction of the PN junction. In the present invention, by preventing the crystal defect layer 7 caused by this amorphization from existing in the depletion layer of the PN junction, deterioration of characteristics such as an increase in leakage current is prevented from occurring.

FIG. 2 is an enlarged view of the cross-sectional structure of the NMOSFET portion formed by the method described in the first embodiment. In the figure, 11□ is the source of the NMOSFET, and 112 is the NMOSFET.
In the MOSFET train, 15 is the depletion layer end of the well junction (junction between the P well, the N'' buried layer and the N well), and 16 is the depletion layer end of the drain. The depletion layer at the junction between the well, the N+ buried diffusion layer, and the N well 2 and the junction between the source and drain extends, but since the depletion layer for the source and drain is in the P well, the crystal defect layer 7 due to amorphization is The depletion layer of the well junction does not exist in the P well 5, the N well 6, and the N+ buried layer 2, as shown in the figure. However, in the present invention, the depth W of the crystal defect layer 7
Since l is set to be deeper than W2, the depth of the edge of the depletion layer extending from the well junction to the N+ buried layer 2 (the depth of the edge of the deeper depletion layer), the crystal defect layer 7 is formed in the depletion layer of the well junction. is not present and does not affect the junction characteristics of the well junction. The above explained the NMO3FET section, but the PM
Also in the OSFET section, the depletion layer at the source/drain junction does not reach the crystal defect layer 7, and good junction characteristics can be obtained. In this embodiment, a case has been described in which an N+ layer is used as the buried diffusion layer, but the same effect can be obtained even if a P+ layer is used. Alternatively, if a Si substrate with a relatively high impurity concentration is used so that the depletion layer does not extend much, there is no need to use a buried diffusion layer.

3 IN(a) to (e) are cross-sectional views showing steps of a second embodiment of the method for manufacturing a complementary field effect semiconductor device according to the present invention. In the figure, reference numeral 17 denotes an isolation groove filled with an insulator. As shown in FIG. 3(a), an N-Si layer 3 with a thickness of 1.3 μm is formed on the N-type Si substrate 1 by epitaxial growth. Next, as shown in FIG. 3(b), a well is formed. Prior to the ion implantation for this purpose, Si ions are implanted to make a portion of the N-Si layer 3 amorphous, thereby forming an amorphous layer 4. In this example, the ion implantation conditions for Si ions are as follows: 150 KeV, 2X1015 cm-2,500 KeV,
Ion implantation was performed under the conditions of 3×10 15 cm −2 . Under these conditions, the amorphous layer 4 can be formed over the entire region from the surface to a depth of about 1 μm, and the interface between the amorphous layer and the single crystal exists in the N-Si layer 3. Next, Figure 3 (
Ion implantation for well formation is performed as shown in C). A P well 5 is formed by B ion implantation in the region where the NMO3FET is to be formed, and an N well 6 is formed by P ion implantation in the region where the PMO3FET is to be formed. In this example, B is 500KeV, 5X10"cm
~2, P to 900, eV, 5x l O”cm-2
Ions are implanted at a peak concentration of about 1) t m from the surface.
A retrograde well was formed at a depth of . After the ion implantation, annealing is performed at 900° C. for 30 minutes in a nitrogen atmosphere, for example, to activate the implanted impurity for well formation and recrystallize the amorphous layer 4. Due to this anil, the amorphous layer 4 becomes a single crystal layer, and a crystal defect layer 7 is formed near the interface between the original amorphous layer and the single crystal due to ion implantation for forming the amorphous layer. . In this example, since the interface between the amorphous and single crystal is located in the N-3i layer 3, the crystal defect layer 7 caused by ion implantation to form the amorphous layer is As shown in the figure, P well 5
and will be located in the N well 6. Then the third
As shown in Figure (d), after forming a trench 17 filled with an insulator to a depth of 1.5 μm using a conventional method for isolation between wells, P was
B is ion-implanted into the well, and P is ion-implanted into the N-well. After this, a complementary field effect semiconductor device (not shown in FIG. 3(e)) is manufactured in exactly the same manner as in the first embodiment.

FIG. 4 is an enlarged view of the cross-sectional structure of the NMO3FET portion formed by the manufacturing method described in the second embodiment of the present invention. In the figure, 18 is the end of a depletion layer extending into the well from the junction between the P well 5 and the Si substrate. As shown in the figure, in the operating state, a P well 5 and an N type Si substrate 1 are connected to each other.
However, in this embodiment, the crystal defect layer 7 due to amorphization is depleted in order to prevent an increase in the leakage current of the PN junction. Made it not exist in the layer. That is, as shown in the figure, the depth Wl of the crystal defect layer 7 due to amorphization is the depth of the edge 1 of the depletion layer extending into the P well 5 from the junction between the P well 5 and the N type S1 substrate 1. It is made to be shallower than W3 and deeper than the depth W4 of the drain depletion layer. However, in this second embodiment, it is necessary to prevent crystal defects associated with well ion implantation from being located deeper than the amorphous layer, and there are some restrictions on the well ion implantation conditions. That is, the method described in the first embodiment has a greater degree of freedom in determining the well impurity concentration distribution. By doing as described above, the crystal defect layer 7 caused by the amorphization does not affect the characteristics of the well junction and the junction characteristics of the source and drain, and good junction characteristics can be obtained in both cases. Although the NMOSFET section has been described above, the depletion layer at the source/drain junction in the PMOSFET section is also set to a depth that does not reach the crystal defect layer 7, so that good junction characteristics can be obtained. According to the embodiments described above, the impurity concentration distribution of the retrograde well can be freely designed without deteriorating other characteristics such as leakage current.

In addition, in the above-mentioned embodiment, the case where Si was used as the ion species for ion implantation for amorphization was explained.
Other materials such as Ge and Ar may also be used as long as they do not ultimately affect the electrical characteristics. In addition, although the case of B and P has been explained as the ion species for well formation, of course, BF2 or Ga may be ion-implanted as a P-type impurity, and As or the like may be used as an N-type impurity. Also good. Furthermore, although we have explained the case of using electric furnace annealing as heat treatment, other annealing methods,
It goes without saying that, for example, lamp annealing, electron beam annealing, laser annealing, etc. may be used.

[Effects of the Invention] As explained above, according to the present invention, since the ion implantation is made amorphous before or after the ion implantation for well formation, the portions that affect the device characteristics are It is possible to eliminate the presence of a crystal defect layer, and it is possible to obtain an extremely excellent effect that the impurity concentration distribution of the well can be freely designed without deteriorating the current-voltage characteristics of a transistor or the like.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention, FIG. 2 is an enlarged sectional view showing an NMOSFET portion of a complementary field effect semiconductor device shown in the first embodiment of the present invention, and FIG. 4 is a sectional view showing the second embodiment of the present invention, and FIG.
FIG. 3 is an enlarged cross-sectional view showing the OS FET portion. ■...N-type Si substrate, 2...N+ buried layer,
3... N-5i formed by epitaxial growth
Layer, 4...Amorphous layer, 5...P well, 6...
N well, 7...Crystal defect layer accompanying ion implantation for forming an amorphous layer, 8...Feed oxide film, 9...
・Gate oxide film, 10...Low resistance polycrystalline silicon gate electrode, 11...High concentration N-type (N+) layer, 1.1
1... NMOSFET source, 11°...
・Drain of NMOSFET, 12,..., high concentration P type (P+) layer, 13... interlayer insulating film, 14...A
I electrode, 15... Depletion layer end of well junction, 16...
...Drain depletion layer end, 17...Isolation layer filled with insulator, 18...Drain depletion layer end extending into the well from the junction between the P well and the Si substrate. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (6)

[Claims] (1) In a complementary field-effect semiconductor device consisting of an N-channel field-effect transistor formed in a P-well and a P-channel field-effect transistor formed in an N-well, from the PN junction between the P-well or N-well and the substrate to the inside of the substrate. A complementary field effect semiconductor device characterized in that a crystal defect layer generated as a result of recrystallization of an amorphous layer is disposed at a deeper position than a depletion layer extending into the amorphous layer. (2) In an N-channel field-effect transistor formed in a P-well and a complementary field-effect semiconductor device for a P-channel field-effect transistor formed in an N-well, a PN junction between the P-well or the N-well and the substrate extends into the well. A crystal defect layer generated as a result of recrystallization of an amorphous layer is placed at a position shallower than the depletion layer and deeper than the depletion layer extending from the source/drain junction of the field effect transistor formed in the well into the well. Complementary field effect semiconductor device. (3) Prior to or after ion implantation for forming a well of a complementary field effect semiconductor device, inert first ions that do not affect the electrical characteristics of the semiconductor are implanted to form an amorphous layer. a second step of ion-implanting electrically active second ions for well formation, and recrystallization of the amorphous layer and impurities introduced by the second ion implantation. A method for manufacturing a complementary field effect semiconductor device, comprising: a third step of performing activation heat treatment. (4) In claim 3, the depth of the crystal defect layer generated when the amorphous layer is recrystallized in the third step is determined by the depth of the crystal defect layer generated when the amorphous layer is recrystallized in the third step. A complementary field effect semiconductor comprising the step of forming an amorphous layer by selecting the amount of ion implantation in the first step so as to form an amorphous layer deeper than the depth of a depletion layer extending from the junction into the substrate. Method of manufacturing the device. (5) Prior to or after ion implantation for forming a well of a complementary field effect semiconductor device, inert first ions that do not affect the electrical characteristics of the semiconductor are implanted to form an amorphous layer. a second step of ion-implanting electrically active second ions for well formation, and recrystallization of the amorphous layer and impurities introduced by the second ion implantation. and a third step of performing activation heat treatment, and the implantation energy of the first ion implantation is set to a depth of a crystal defect layer generated when recrystallizing the amorphous layer formed by the ion implantation. A method for manufacturing a complementary field effect semiconductor device, characterized in that the implantation energy is greater than the implantation energy when the depth matches the depth of a depletion layer extending into the substrate from a PN junction between the well and the substrate. (6) In claim 5, the depth of the crystal defect layer generated when the amorphous layer is recrystallized in the third step is determined by the PN between the well and the substrate of the complementary field effect semiconductor device. A complementary field effect semiconductor comprising the step of forming an amorphous layer by selecting the amount of ion implantation in the first step so as to form an amorphous layer deeper than the depth of a depletion layer extending from the junction into the substrate. Method of manufacturing the device.