CN1293494C

CN1293494C - Communication interface of master-slave type processor system

Info

Publication number: CN1293494C
Application number: CNB991168542A
Authority: CN
Inventors: 严学强; 薛盛勇
Original assignee: Alcatel Lucent Shanghai Bell Co Ltd
Current assignee: Nokia Shanghai Bell Co Ltd
Priority date: 1999-09-09
Filing date: 1999-09-09
Publication date: 2007-01-03
Anticipated expiration: 2019-09-09
Also published as: CN1288201A

Abstract

The present invention relates to a communication interface in a master/slave multiprocessor system, which comprises a read-write control unit, an address decoding unit, an alternative unit and an interrupting and readying unit, wherein the read-write control unit obtains addresses and data information from a master processor, and gives an access order according to the access requirements of a host computer interface; the address decoding unit obtains address information from the read-write control unit, and maps the register address of the host computer interface of each slave processor onto the corresponding address field of the master processor; the alternative unit obtains enabling signals, the addresses and data validity signals from the address decoding unit, the read-write control unit and the master processor so as to output the data validity signals to a plurality of salve processors. The interrupting and readying unit selects a corresponding route of a readying signal and an interrupting signal from the slave processors for the master processor.

Description

Communication interface in the master-slave mode multiprocessor system

The present invention relates to the communication interface in a kind of master-slave mode multiprocessor system.

Large-scale calculations problem or real-time control problem often need be finished dealing with jointly by a plurality of processors.When a plurality of processors are handled a problem, the exchange of information or data must be arranged between them, that is to say between the processor and must communicate.Master-slave mode multiprocessor system is the special case of multicomputer system, and it is made up of a primary processor and a plurality of communication interface between processor and principal and subordinate processor.For needing a large amount of communication between this master and slave processor, and from not needing the communication interface of direct communication between the processor, generally be to utilize the bus bridge technology to add that bus arbitration or switch logic form.Annexation between master and slave processor and the communication interface as shown in Figure 1, the memory expansion mouth that is primary processor 1 links to each other with first bus bridge 13 and arbitration unit 12, join directly butt joint between two bus bridges from the memory expansion mouth of processor 11 and second bus bridge 14 and arbitration unit 12.

Mainly there is following shortcoming in such system, that is:

1) the bus bridge circuit promptly the logic of first bus bridge 13 and second bus bridge 14 need realize bus protocol, logic is very complicated, generally is difficult to design voluntarily, need be realized by the bridging chip of special use;

2) owing to the existence of two bus bridges, make and when processor 11 conducts interviews, introduced extra time delay, influenced the efficient of visit 1 pair of primary processor;

3) more logic has increased design complexities, has also taken the area of more printing board PCB.

The object of the present invention is to provide a kind of make between the principal and subordinate processor can be efficiently and the communication interface in the master-slave mode multiprocessor system that communicates easily.

The object of the present invention is achieved like this, communication interface in a kind of master-slave mode multiprocessor system, it is connected primary processor and a plurality of between the processor, it is characterized in that, described have the host interface from processor, this host interface comprises address register and data register, the memory expansion mouth of one termination primary processor of described communication interface, another termination is respectively from the host interface of processor, this communication interface comprises read-write control unit, address decoding unit, multiselect Unit one and the ready unit of interruption, wherein: read-write control unit, obtain address and data message from primary processor, by will visiting of choosing by address decoding unit and multiselect Unit one being provided access order from processor from the host interface accessing sequential requirement of processor, promptly at first the destination address from processor is given the address register of host interface, read and write the data of the data register of host interface then, and in primary processor and certain when processor communicates, read-write control unit obtains address and data message from primary processor, directly by data bus with carry out address and exchanges data from processor; Address decoding unit obtains address information from read-write control unit, and the register address from processor host interface respectively is mapped on the corresponding address field of primary processor; Multiselect Unit one obtains enable signal from address decoding unit, obtains low order address information from read-write control unit then, obtains the data useful signal from primary processor simultaneously, to one choose export this data useful signal from processor; Interrupt ready unit, give primary processor from a plurality of corresponding ready signal, look-at-me routes from processor, selected.

Owing to adopted above-mentioned technical solution, promptly with a kind of very simple interface between software and hardware logic, a plurality of addressing spaces that are mapped to primary processor from the storage space of processor indirectly, owing to utilize the data useful signal to select difference is conducted interviews from processor, therefore saved originally the bus arbitration and the switch logic of the complexity that need bring by bus interconnection; In addition,, therefore do not introduce extra time delay, improved primary processor, simultaneously, when specific implementation, saved valuable printing board PCB area yet efficient from processor access owing to do not adopt bus bridge.

The present invention is further illustrated below in conjunction with embodiments of the invention and accompanying drawing.

Fig. 1 is the functional block diagram of the communication interface in the existing master-slave mode multiprocessor system;

Fig. 2 is the functional block diagram of the communication interface in the master-slave mode multiprocessor system of the present invention.

By shown in Figure 2, the communication interface in the master-slave mode multiprocessor system of the present invention, the memory expansion mouth of its a termination primary processor, a plurality of host interface HPI (Host PortInterface) of another termination from processor.Primary processor generally can be selected Intel 80960RD, generally select the TMS320C6x of TexasInstruments company or the digital signal processor of TMS320C5x model (DigitalSignal Processor) from processor, be called for short DSP, it all has the host interface.Is its several address mapping formula registers from the HPI mouth of processor concerning primary processor, and these registers comprise address register HPIA, data register HPID and control register HPIC.

Communication interface in the master-slave mode multiprocessor system of the present invention comprises:

Read-write control unit 3, obtain address and data message from primary processor 1, by 21 visiting demands of HPI mouth will visiting of choosing by address decoding unit and multiselect Unit one provided access order from processor, promptly at first give HPIA the destination address from processor 2 that will visit, read and write the data of HPID then.And in primary processor 1 and certain when processor 2 communicates, it obtains address and data message from primary processor 1, directly by data bus with carry out address and exchanges data from processor, generally adopt corresponding software to reach;

Address decoding unit 6 obtains address information from read-write control unit, the register address from processor HPI mouth 21 respectively is mapped on the corresponding address field of primary processor 1,

Multiselect one unit 5 obtains enable signal from address decoding unit 6, obtains low order address information from read-write control unit then, obtains the data useful signal from primary processor 1 simultaneously, to one choose from processor 2 output data useful signals;

Interrupt ready unit 4, give primary processor 1 from a plurality of corresponding ready signal, look-at-me routes from processor 2, selected.This is all must carry out indirectly by register the visit from processor memory because of any, and therefore the 21 pairs of primary processors 1 of HPI mouth from processor 2 are relative equipment at a slow speed.Therefore be necessary to provide ready and look-at-me to primary processor 1.Interruption and ready unit are responsible for selecting corresponding HPI mouth 21 ready signals to give primary processor 1 from processor 2 from a plurality of, and look-at-me are connected to the corresponding interrupt pin of primary processor 1.

In general, address decoding unit 6, multiselect one unit 5 and interrupt ready unit 4 and adopt programming devices to realize.

Describedly respectively link together from HPI mouth 21 data lines of processor, any moment has only the data from processor effective, other be high resistant, effectively directly driving data transmission of data.

By described communication interface, can allow primary processor 1 its all storage space of visit from the HPI mouth 21 of processor, but the corresponding operating of several registers that primary processor 1 can only be by HPI realizes that it is to asking operation from the storer of processor 2.Its process is: utilize the interrupt mechanism of HPI mouth to give 1 interruption of primary processor from processor 2, have data to give primary processor 1 to represent it, have no progeny during primary processor 1 is received by interrupt service routine at predetermined address reading data.And 1 pair of primary processor respectively from the browsing process of processor 2 is: initialization HPIC, the address of needs visit is write corresponding HPIA from processor, and visit corresponding HPID.

Claims

1. the communication interface in the master-slave mode multiprocessor system, it is connected primary processor and a plurality of between the processor, it is characterized in that, described have the host interface from processor, this host interface comprises address register and data register, the memory expansion mouth of one termination primary processor of described communication interface, another termination is respectively from the host interface of processor, this communication interface comprises read-write control unit, address decoding unit, multiselect Unit one and interrupts ready unit, wherein:

Read-write control unit, obtain address and data message from primary processor, by will visiting of choosing by address decoding unit and multiselect Unit one being provided access order from processor from the host interface accessing sequential requirement of processor, promptly at first the destination address from processor is given the address register of host interface, read and write the data of the data register of host interface then, and at primary processor with when processor communicates, read-write control unit obtains address and data message from primary processor, directly by data bus with carry out address and exchanges data from processor;

Address decoding unit obtains address information from read-write control unit, and the register address from processor host interface respectively is mapped on the corresponding address field of primary processor;

Multiselect Unit one obtains enable signal from address decoding unit, obtains low order address information from read-write control unit then, obtains the data useful signal from primary processor simultaneously, to one choose export this data useful signal from processor;

Interrupt ready unit, give primary processor from a plurality of corresponding ready signal, look-at-me routes from processor, selected.