CN1281559A - Method of emulating shift register using RAM - Google Patents

Method of emulating shift register using RAM Download PDF

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Publication number
CN1281559A
CN1281559A CN 98810664 CN98810664A CN1281559A CN 1281559 A CN1281559 A CN 1281559A CN 98810664 CN98810664 CN 98810664 CN 98810664 A CN98810664 A CN 98810664A CN 1281559 A CN1281559 A CN 1281559A
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China
Prior art keywords
shift register
ram
register
word
pointer
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Granted
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CN 98810664
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Chinese (zh)
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CN1119745C (en
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阿卡迪·摩勒夫－施特伊曼
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I C Com Ltd
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I C Com Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/104—Delay lines

Abstract

A method using a RAM (10) and a short shift register (20) to emulate a long shift register to store a stream of incoming bits. A pointer points to one of the RAM registers. To store an incoming bit, the contents of the RAM register pointed to by the pointer are written to the shift register (20) and shifted by one bit, the incoming bit is stored in the location in the shift register (20) freed up by the shift operation, the updated contents of the shift register (20) are written back to the RAM register pointed to by the pointer, and the pointer is incremented.

Description

Utilize the method for RAM emulating shift register
The present invention relates to digital computation, be specifically related to a kind of method with a random access register (RAM) and a shift register of growing very much of a short shift register emulation.
In many application, need to handle in real time an incoming bit stream.For example, may need for an incoming bit stream provides a finite impulse response filter, its each coefficient is an independent position.The k-factor of wave filter is expressed as { C k(k=0～K-1), the bit table of incoming bit stream (indefinite length) be shown Xn}, and the output that this means wave filter be one the set of Yn} is shown below: Y n = Σ k = 0 K - 1 C k X n - k
The computing of expression is the XOR computing.
Realize that the direct method of this wave filter provides a register-stored coefficient { C that the K position is long k, the shift register storage input bit sequence { X that the K position is long k.When each new bit arrival, the content of shift register moves one to accept new input position.Note automatically having deleted the old input position of K position before, new input position here.Between each new input position arrives, the content in coefficient register and the shift register is carried out inner product calculation, so that get filtering output to the end.
This direct method defective is wave filter for length available, and (for example, K=1024), the shift register of a respective length of structure is too expensive and infeasible in processor chips.Therefore, generally believing needs a kind of method of using expensive storage device such as RAM emulating shift register, and will bring huge benefit.
According to the present invention, a kind of method of handling continuous input bit is provided, comprise step: (a) provide: (ⅰ) RAM with a plurality of registers, word of each register-stored, all words are isometric, (ⅱ) one is waited the shift register of being longer than several words at least, (ⅲ) pointer; (b) with a register among the pointer initialization sensing RAM; (c) for each j position input group: (ⅰ) word that will deposit the register of pointer indication in writes shift register, (ⅱ) with word mobile j position in shift register, (ⅲ) input group in j position is write shift register, produce the register that word after a word (ⅳ) that is positioned at the renewal of shift register will upgrade deposits the pointer indication in thus.(ⅴ) increase progressively pointer.
RAM is made up of one group of register that can independently address, and each register has different addresses, and wherein the word of length-specific (special in 8,16,32 or 64) is also searched in storage subsequently.Key of the present invention be to use one by the storer of word addressing so that realize efficient storage when independently input bit arrives continuously.This point is also by providing a shift register and the pointer to the ram register geocoding of lacking (word length) relatively to realize.Pointer is initialised and points to a ram register.When each input position arrives, be stored in by the word in the ram register of pointer indication and be written into shift register, moving one is that the position is abdicated in new input position, and writes back to its searched ram register.Pointer increases progressively to point to next ram register.Note " increasing progressively and " define circularly at this: a pointer that points to last ram register is increased progressively and will make first ram register of pointed of pointer.Notice that the input bit backward is stored among the RAM, as hereinafter describing in detail.
The present invention is described with reference to the drawings in this mode with example, as shown in the figure:
The FIG.1 explanation is in the RAM that begins to locate of an input bit memory cycle;
N-bit shift register of FIG.2A and 2B explanation is in two different stages of input bit memory cycle.
The FIG.3 explanation is in the RAM of the ending phase of input bit memory cycle.
The present invention is a kind of method with a shift register of growing very much of RAM emulation.Especially, the present invention can be used for providing a finite impulse response filter to a sequence bits, and the order of inverted sequence bit.
Describe with reference to the accompanying drawings and accordingly, may be easier to understand the principle and the operation of shift register emulation of the present invention.
Referring to diagram, Fig. 1 represents a RAM10 that M ram register arranged, from R 0To R M-1, each can store the N position, and total volume is the NM position, at this moment NM position X nTo X N-NM+1Incoming bit stream be stored according to the present invention.The input bit of Dao Daing earlier, X N-NM-1Be stored in ram register R 0(N-1) position, the input bit X of Dao Daing next N-NM+2Be stored in ram register R 1(N-1) position, by that analogy.The bit X of up-to-date arrival n, be stored in ram register R M-1The 0th position.Pointer P points to ram register R 0, wherein and arrive also stored input bit X the earliest in (N-1) location storage N-NM+1
Next input bit X N+1Arrive, begin the next input bit memory cycle.The first step is with the ram register R by pointer P indication 0Content write N-bit shift register 20.Fig. 2 A represents the state of N-bit shift register 20 when this EOS.Second step was that the bit with N-bit shift register 20 moves one, delete bit X N-NM+1, be new input bit X N+1Vacate the 0th position of N-bit shift register 20.The 3rd step was to be positioned at the new input bit X of the 0th position N+1Deposit N-bit shift register 20 in.The state of N-bit shift register 20 when Fig. 2 B represents this EOS.The 4th step was that the content with N-bit shift register 20 writes among the ram register R0 by pointer P indication.At last, increase progressively pointer P, point to ram register R 1, R 1The input bit X that arrive its (N-1) location storage the earliest this moment N-NM+2The state of RAM when Fig. 3 represents this EOS.
During the input bit memory cycle, the content of RAM10 can be read in the mode of routine and operate.For example, in order to produce the next one output Y of limited input response filter (supposing K=NM) mentioned above N+1, M the word that is stored among the RAM10 read continuously, and with coefficient { C kDifferent (XOR), coefficient { C kAlso be stored in M the word in the different storage unit.Attention is in order correctly to work coefficient { C kMust store with backward: C K-1, C K-M-1, C K-2M-1... C 2M-1, C M-1, C K-2, C K-M-2, C K-2M-2... C 2M-2, C M-2... C K-M-1, C K-2M+1, C K-3M+1... C M+1, C 1, C K-M, C K-2M, C K-3M... C M, C 0This backward is contraposition { C kUse method of the present invention, with bit { C kProduce as the input bit string.
The typical value of M and N is respectively 32 and 32.
Increasing progressively of pointer P cycle.Therefore, in the memory cycle, pointer P initial directional is the register R of high mark at input bit M-1, " increasing progressively " pointer P means the change of pointer P value to point to the register R of minimum mark 0
Principle of the present invention also can be applicable to handle at one time an incoming bit stream rather than one.For example, using length is the ram register of 3 multiple, and incoming bit stream at one time can processed three bits, imported for 3 bit storage cycles at each the content of shift register is moved 3.Shift register must the same with ram register at least length; If shift register only is used for unloading and loads ram register, and the output of shift register is not used further to other processing, then the length of shift register needs not to be 3 multiple position.The restriction of unique reality is if bit is handled in the mode of j group, and j is the typical word length of a conventional RAM (for example 8,16 or 32), processing procedure will be a unit with word rather than bit so, for example prior art is described in people's such as Dixon U.S. Patent No. 5,568,443.
Although the present invention describes with a limited number of embodiment, its variation, other application of modification also will make the present invention have more value.

Claims (6)

1. method of handling continuous input bit.System comprises:
(a) provide:
(ⅰ) RAM who comprises a plurality of registers, word of each described register-stored, all words are isometric,
(ⅱ) one is waited the shift register of being longer than several described words at least,
(ⅲ) pointer;
(b) with a described register among the described pointer initialization sensing RAM; And
(c) for each j position input group:
(ⅰ) word that will deposit in the described shift register of described pointer indication writes described shift register,
(ⅱ) with described word mobile j position in described shift register,
(ⅲ) described j position input group is write described shift register, produces a word that is positioned at the renewal of described shift register thus,
(ⅳ) word after the described renewal is deposited in the described register of described pointer indication,
(ⅴ) increase progressively described pointer.
2. according to the process of claim 1 wherein that j equals 1.
3. according to claim 1, the register among wherein all RAM and described each word are isometric.
4. according to claim 1, wherein said shift register and described each word are isometric.
5. according to claim 1, also comprise step:
(d) read and handle at least some described words in the described register that is stored in described RAM continuously.
6. according to claim 5, the described word in wherein all registers that is stored in described RAM is read continuously and is handled.
CN 98810664 1997-10-09 1998-09-18 Method of emulating shift register using RAM Expired - Fee Related CN1119745C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US94746797A 1997-10-09 1997-10-09
US08/947,467 1997-10-09

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CN1281559A true CN1281559A (en) 2001-01-24
CN1119745C CN1119745C (en) 2003-08-27

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EP (1) EP1027649A4 (en)
JP (1) JP2001520429A (en)
KR (1) KR20010024466A (en)
CN (1) CN1119745C (en)
AU (1) AU9402098A (en)
WO (1) WO1999019798A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110888601A (en) * 2019-11-14 2020-03-17 中国电子科技集团公司第五十四研究所 Shift register based on RAM IP core and implementation method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733049A (en) * 2015-03-27 2015-06-24 中国电子科技集团公司第二十研究所 Shifting register realized by using random access memory (RAM) unit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3755788A (en) * 1972-05-01 1973-08-28 Honeywell Inf Systems Data recirculator
US4393482A (en) * 1979-11-08 1983-07-12 Ricoh Company, Ltd. Shift register
US5153846A (en) * 1990-07-30 1992-10-06 At&T Bell Laboratories Digital shift register using random access memory
US5406518A (en) * 1994-02-08 1995-04-11 Industrial Technology Research Institute Variable length delay circuit utilizing an integrated memory device with multiple-input and multiple-output configuration
US5479128A (en) * 1994-03-16 1995-12-26 Industrial Technology Research Institute Single ram multiple-delay variable delay circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110888601A (en) * 2019-11-14 2020-03-17 中国电子科技集团公司第五十四研究所 Shift register based on RAM IP core and implementation method thereof
CN110888601B (en) * 2019-11-14 2023-05-19 中国电子科技集团公司第五十四研究所 Shifting register implementation method based on RAM IP core

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JP2001520429A (en) 2001-10-30
EP1027649A1 (en) 2000-08-16
WO1999019798A1 (en) 1999-04-22
CN1119745C (en) 2003-08-27
KR20010024466A (en) 2001-03-26
EP1027649A4 (en) 2004-08-04
AU9402098A (en) 1999-05-03

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