CN117834755A - Interface circuit between protocol layer and adapter layer facing core particle interconnection interface and chip - Google Patents
Interface circuit between protocol layer and adapter layer facing core particle interconnection interface and chip Download PDFInfo
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Abstract
The invention discloses a protocol layer and adapter interlayer interface circuit and a chip facing a core interconnection interface, which comprises a sending interface circuit and a receiving interface circuit, wherein the sending interface circuit comprises a credit management module, a data micro-packet generation module, a link management module, a power management module and a multi-path arbiter, wherein the credit management module and the data micro-packet generation module are positioned on the protocol layer, and the link management module, the power management module and the multi-path arbiter are positioned on the adapter layer; the receiving end interface circuit comprises a decoder, a credit management module, a data micro-packet analysis module, a link management module and a power management module, wherein the decoder, the link management module and the power management module are positioned on an adapter layer, and the credit management module and the data micro-packet analysis module are positioned on a protocol layer. The invention aims to promote the more thorough standardization of a core interconnection interface adapter layer and a physical layer and realize a protocol layer and adapter interlayer interface with better compatibility, stronger decoupling and higher multiplexing degree.
Description
Technical Field
The invention belongs to the field of high-speed interconnection interfaces between chips (chiplets), and particularly relates to a protocol layer and adapter interlayer interface circuit and a chip for a chip interconnection interface.
Background
As the demand for computing power is continuously expanded and the transistor process approaches to a physical limit, the conventional way of improving the performance of the whole System on Chip (SoC) by increasing the number of transistors is faced with the problems of limited size of a mask, reduced yield and the like due to the continuous expansion of the size of a Die. Meanwhile, due to significant increase in chip manufacturing cost and research and development cost caused by process improvement, integration of a plurality of smaller core particles in a package is an industry trend. The method can package the bare chips (called as core grains) with standard interconnection interfaces by adopting different processes, and the core grains communicate with each other through the bare chip-to-bare chip (D2D) interconnection interfaces, so that on one hand, the design space of the chip is enriched, and a designer can adjust the process adopted by each core grain according to the requirement, thereby reducing the cost of customization and optimization, and leading the design cost of advanced technology to be shared; on the other hand, the designed core particle can be conveniently reused in the package, so that the design time of the whole chip can be reduced, and the NRE cost in the research and development process of the chip can be reduced. However, the premise of integrating a large number of die in the same package is that the interconnect bandwidth between die and die is high enough to meet the high-speed communication between the entire die, otherwise comparable performance to that of a conventional SoC cannot be achieved. Therefore, inter-core interconnection technology is one of the key technologies for the wide range of applications of core architecture. And wherein compatibility and efficiency of inter-die interconnect interface standards are an important component in inter-die interconnect technology. At present, important companies and group units in the chip design industry push out the standard of the chip interconnection interface, and the chip interconnection interface is expected to take a dominant position in ecology. For example, the UCie standard proposed by the industry huge head Intel, the BoW standard proposed by the open organization OCP, the group standard of the small chip interface bus technical requirement proposed by the China computer interconnect technology Union, the core particle interconnect interface standard proposed by the China Chiplet industry Union, and the like.
Typically, the inter-die interconnect interface is defined as three layers, a protocol layer, an adaptation layer, and a physical layer, respectively. In general, the protocol layer is mainly responsible for specific protocol flow, virtual channel management, flow control, etc., and the adaptation layer is mainly responsible for error detection and correction, retransmission, link and power consumption management. The physical layer is responsible for signal transmission over the link and will generally vary significantly depending on the type of package and the circuit implementation. Virtual channel management in a protocol layer mainly gathers and packages messages (packages) from different virtual channels at a sending end, generates a basic unit which can be identified and transmitted by an adapter layer, namely a micro packet (Flit), unpacks the micro packet at a receiving end and distributes the unpacked micro packet to a corresponding virtual channel, and realizes one-to-one corresponding message transmission from each virtual channel of the sending end to each virtual channel of the receiving end. The flow control of the protocol layer is to match the sending rate of the message in each virtual channel of the sending end with the receiving rate of the message in each virtual channel of the receiving end, prevent the overflow of the message buffer zone of the receiving end and improve the bandwidth utilization of the sending end as much as possible. The error detection and correction mechanism of the adapter layer is to maintain the correctness of the data packet in the transmission process, and a common way is to add a CRC check code, an ECC check code, etc. at the end of the data micro packet. Error correction mechanisms generally divide errors into two types, detectable but uncorrectable errors and detectable and correctable errors, respectively. For the former, the receiving end will always discard the data packet directly. In order to ensure data integrity, the transmitting end needs to retransmit the micro packet which is not received by the receiving end. The retransmission generally adopts an Ack/Nak mechanism, namely, a transmitting end maintains a micro-packet buffer zone, the buffer zone empties the corresponding micro-packet in the buffer zone when receiving an Ack message transmitted by a receiving end, and the corresponding micro-packet is retransmitted when receiving a Nak message. The adapter layer also has specialized link management and power management logic that generates link management micro-packets (Link Management Flit, LMF) and power management micro-packets (Power Management Flit, PMF) that will share the physical link with Data micro-packets (Data Flit, DF) from the protocol layer. The LMF is mainly used for link initialization, link state switching and link retransmission information transmission; the PMF is mainly used for power consumption state initialization and power consumption state switching. Currently, in inter-chip interconnect bus protocols, such as PCIE and CXL Protocol layers, the hierarchy of inter-chip interconnect interfaces is divided into Protocol Layers (PL), transaction layers (Transaction Layer, TL), data Link Layers (DLLs), and physical layers. The protocol layer in the die interconnect interface contains the functions of PL and TL in the chip interconnect interface, and the adapter layer corresponds to a DLL.
Fig. 1 is a circuit configuration diagram of a conventional chip interconnection interface circuit. As shown in fig. 1, the protocol layer packages protocol layer messages (Protocol Layer Package, PLP) from different virtual channels into a micro-packet format, and adds a message type field in the micro-packet format to distinguish between PLPs from different virtual channels and different types. After the protocol layer packet is packed into a data micro-packet (DF), the "credit and management information retention fields" reserved for the adapter layer in the micro-packet are filled by "credit and management information attachment logic" at the adapter layer, the credit information comes from the "credit management logic" at the protocol layer, and the link and power consumption management information comes from the "link management" and "power consumption management" logic at the adapter layer. The data micro-packet (DF) filled with credit and management information in the "credit and management information retention field" will enter the multi-path arbiter, arbitrating with independent link management micro-packets (LMF) and power management micro-Packets (PMF) from "link management" and "power management". If there is an LMF or PMF waiting to send, stopping DF sending after a complete DF sending is finished, and inserting the LMF or PMF. The transmission priority of the LMF or PMF is higher than that of the DF. Since the LMF and PMF transmissions occupy normal link bandwidths, the DF transmission efficiency is reduced. To solve the issue of transmission efficiency, the adapter layer generally supports a mechanism for carrying the link management information in the data micro packet for transmission. As long as there are data micro-packets transmitted to each other at the sender and the receiver, it is not necessary to separately generate LMF and PMF micro-packets for the transmission of these information, but credit and management information is appended to the data micro-packets at the sender. At the receiving end, after the adapter layer receives the micro-packet from the physical layer, the "management micro-packet" (management Flit) and the "data micro-packet" (data Flit) will be parsed according to the micro-packet type. Separate "management flits" are fed into the "link management" and "power management" logic for link and power consumption state management. The "data Flit" will continue to be fed into the "credit and management information extraction logic", where the "credit information" and the "link and power consumption management information" in the "credit and management information retention field" are extracted, the former being fed into the "credit management" logic of the protocol layer, and the latter being fed into the "link management" and "power consumption management" logic. The above conventional manner has the following problems: there is a need to reserve locations in the data micro-packet format for transmission credits and link management information that cannot be occupied by messages at the protocol layer. Since different protocols define different rule definitions for message generation and parsing of the protocol layer, the micro packet formats between the protocol layer and the adapter layer are difficult to unify. In particular, the different protocols have different regulations on which domains are used in the micro-packet format to store credit and management information, and the "credit and management information attachment logic" and "credit and management information extraction logic" of the adapter layer need to be adapted according to different micro-packet format definitions to work, so that the cost of the adapter layer for being compatible with the different protocols is significantly increased, and once the logic is solidified, the adapter layer cannot be modified and expanded. In addition, the mechanism encounters an obstacle when the micro-packet and the protocol which do not accord with the current micro-packet format definition in the future self-defined protocol are expanded, so that the flexibility of the self-defined protocol design and the reusability of an adapter layer are reduced.
The definition of the micro-packet format for the interface between the protocol layer and the adapter in the conventional core interconnect interface standard varies, as does the definition of the reserved locations in the data micro-packet format for the transfer of link management information. For example, in the definition of the micro packet format in the uci protocol standard and the chiplet interface bus technical requirements (hereinafter referred to as "chiplet") protocol standard, the protocol standard specifies fields for link management, but the location definitions of these fields in the micro packet format are different.
As shown in fig. 2, in the 256-bit micro packet format defined by the uci protocol, the protocol layer needs to reserve the last 20 bytes (236 th to 255 th bytes) of the micro packet to the adaptation layer, the protocol layer is pre-filled with 0, and the adaptation layer is responsible for filling new data, including a micro packet header (FlitHdr) field, a data link micro packet (DLP), a Reserved field (10B Reserved), and a CRC check field.
Fig. 3 is a 256-bit micro-packet format for PCIe 6.0, although the last 20 bytes (236 th to 255 th bytes) of the micro-packet are reserved for the adaptation layer as well, the reserved 20-byte inner field includes a data link layer micro-packet field (DLLP) field and a CRC check field whose location and content definition in the micro-packet are different from those in the uci protocol micro-packet. When the UCIe and PCIe 6.0 micro-packet formats need to be compatible at the same time, the adapter layer needs to identify different protocol micro-packets and fill different contents in the last 20 bytes of the micro-packets.
Fig. 4 is a specific format of a packet header (Flit Hdr) field in a 256-bit packet format specified by the uci protocol. The micro-header field contains a total of 16 bits, including several fields that the adapter layer needs to fill, such as Sequence Number (Sequence Number), acknowledgement, or non-acknowledgement information (Ack or Nack).
Fig. 5 is a specific format of a data link management header (DLLP Hdr) field in a 256-bit micro-packet format specified by the PCIe 6.0 protocol. The data link management header field contains a total of 16 bits, including a Reply Command (Reply Command) field and a Sequence Number (Sequence Number) field for link management that the adapter layer needs to populate.
Flit Hdr in fig. 4 and DLLP Hdr in fig. 5 both occupy 16 bits (2 bytes) and are in the same location (236 th to 237 th bytes) in the micro-packet, but the internal format is quite different.
Fig. 6 shows a micro packet format defined in the protocol of the "chiplet interface bus technical requirements" (referred to as the "chiplet" protocol for short). Bytes 240 to 245 are used in the protocol to hold data link layer information (DLLP [0:5 ]), while several fields for carrying adapter layer link management information are defined in the 4 byte ID fields of bytes 0 to 3. The 4 byte ID field requires protocol layer padding in part, while the definition of the 0-3 bytes in UCIe and PCIe protocols is data for the transport protocol layer. Therefore, the "chiplet" protocol standard is not fully compatible with the uci standard and the adapter layer circuitry of the die interconnect interface cannot be reused.
Uci proposes the concept of the original (RAW) micro-packet format in order to provide higher compatibility with different protocols. The RAW micro-packet does not define the format of the RAW micro-packet and the micro-packet, all contents in the micro-packet are determined by a protocol layer, and the protocol layer does not reserve a domain for the adapter layer for storing link management and power consumption management information, and meanwhile, no related domain stores micro-packet type information for identifying the protocol layer micro-packet and the adapter layer management micro-packet, so that the adapter layer cannot analyze the micro-packet format, namely, management information cannot be inserted in a DF, and cannot share a physical link between an LMF or a PMF and the DF. Intel specifies that when using the RAW micro-packet format, the adapter layer is configured in Bypass (Bypass) mode, all functions of the adapter layer are bypassed, and the RAW micro-packets from the protocol layer to the adapter layer go directly into the physical layer. In order to use the RAW micro packet format, the protocol layer is required to implement additional data link layer functions instead of the adapter layer, i.e. in this mode the user needs to provide an additional data link layer to implement all functions of the adapter layer. As shown in fig. 7 (a), in order for uci to implement a core interconnect interface compatible with early PCIe1.0-4.0 protocols or custom protocols in RAW micro-packet format, the adapter layer needs to be set to bypass mode, and two levels of complete PCIe TL and DLL must be implemented on top of the adapter. The Interface micro-packets of the DLL and the adapter layer are in a 'micro-packet related inter-core-particle Interface (FDI)' format, and the Interface of the adapter layer and the physical layer is in a 'RAW mode inter-core-particle Interface (RAW-to-inter-particle Interface, RDI)' format. The formats of the FDI and the RDI are identical, so that when the RAW micro-packet format is used by the FDI interface, the micro-packet in the FDI format directly bypasses to generate the micro-packet in the RDI format, the whole functions of the adapter layer are bypassed, and the link management is realized by the DLL layer of PCIe. As shown in fig. 7 (b), when uci is compatible with the CXL protocol in the standard micro packet format, the uci adapter layer implements a link management function. While the original (RAW) micro-packet format proposed by uci provides a degree of protocol compatibility, at the expense of the functionality of the uci's adapter layer, the user must additionally design the data link layer to implement basic link management functionality.
It follows that the current core interconnect interface either suffers from poor compatibility with different protocols due to differing packet format definitions, or from the two types of problems that sacrifice adapter layer multiplexing to improve compatibility and require additional provision of the data link layer.
Disclosure of Invention
The invention aims to solve the technical problems: aiming at the problems in the prior art, a protocol layer and adapter interlayer interface circuit and a chip for a core interconnection interface with better compatibility, stronger decoupling and higher multiplexing degree are provided, so that the more thorough standardization of the core interconnection interface adapter layer and a physical layer is promoted, and the protocol layer and adapter interlayer interface with better compatibility, stronger decoupling and higher multiplexing degree is realized.
In order to solve the technical problems, the invention adopts the following technical scheme:
a protocol layer and adapter interlayer interface circuit for a core interconnect interface, comprising a transmit end interface circuit, the transmit end interface circuit comprising:
the credit management module is positioned at the protocol layer and used for generating credit information;
the data micro-packet generating module is positioned on the protocol layer and is used for receiving the messages of the N channels, the credit information of the credit management module, the link management information and the power consumption management information from the adapter layer, packaging the messages from the channels according to the set message packaging rule to generate a data micro-packet, filling the credit information, the link management information and the power consumption management information into a reserved field in the data micro-packet when the credit information, the link management information and the power consumption management information need to be added to the data micro-packet, and notifying an information sender;
The link management module is positioned at the adapter layer and used for generating link management information to initialize a link and manage the state of the link, the link management information comprises retransmission control information to control the reliable transmission of the data micro-packet between the sending end and the receiving end, and the link management information is generated to be independent management micro-packet output when the data micro-packet generation module cannot attach the link management information;
the power management module is positioned on the adapter layer and used for generating power consumption management information to manage the power consumption state of the link, and generating independent management micro-packets for outputting the power consumption management information when the data micro-packet generation module cannot attach the power consumption management information;
and the multi-path arbiter is positioned on the adapter layer, and the input end of the multi-path arbiter is respectively connected with the output ends of the data micro-packet generating module, the link management module and the power management module and is used for carrying out arbitration on the data micro-packets output by the data micro-packet generating module, the link management module and the power management module and then sharing the physical link for transmission.
Optionally, the retransmission control information includes allocating a request sequence number ReqNo to each micro packet at the transmitting end, generating a response sequence number AckNo or a non-response sequence number NAckNo at the receiving end according to whether the micro packet is correctly received, where the response sequence number AckNo indicates that the micro packet identified as the request sequence number ReqNo has been correctly received; the non-reply sequence number, NAckNo, indicates that a micro packet identified as request sequence number, reqNo, has been received, but the data is checked for errors, and the micro packet needs to be retransmitted.
Optionally, the power consumption management information includes two types, namely pm_adp_tx and pm_adp_rx, where the pm_adp_tx is the power management information that the adapter layer needs to send to the opposite terminal, including request information for requesting to enter a certain power consumption state and response information for returning to be in a certain power consumption state; the PM ADP RX type is the power management information that the adapter layer receives from the peer.
Optionally, the protocol layer and adapter interlayer interface circuit further includes a receiving end interface circuit, the receiving end interface circuit including:
the decoder is positioned at the adapter layer and is used for analyzing the micro-packet from the physical link to determine whether the type of the micro-packet is a management micro-packet or a data micro-packet, if the type of the micro-packet is the management micro-packet, the micro-packet is sent to the power management module and the link management module of the receiving end, and if the type of the micro-packet is the data micro-packet, the micro-packet is sent to the data micro-packet analysis module;
the credit management module is positioned on the protocol layer and used for realizing the flow control of each channel from the transmitting end to the receiving end;
the data micro-packet analysis module is positioned on the protocol layer and used for analyzing the data micro-packet, sending the analyzed messages of the N channels into the corresponding channels respectively, if the data micro-packet contains credit information, sending the credit information to the credit management module, if the data micro-packet contains link management information, sending the link management information to the link management module, and if the data micro-packet contains power consumption management information, sending the power consumption management information to the power management module;
The link management module is positioned at the adapter layer and used for carrying out link state management according to the received link management information;
the power management module is positioned on the adapter layer and is used for managing the power consumption state of the link according to the received power consumption management information;
the output end of the decoder is respectively connected with the data micro-packet analysis module, the link management module and the power management module, and the output end of the data micro-packet analysis module is respectively connected with the credit management module, the link management module and the power management module.
Optionally, the data transmission format between the protocol layer and the adaptation layer of the transmitting end interface circuit and the receiving end interface circuit includes the following field fields:
the micro-packet type field is used for uniformly encoding a data micro-packet of the protocol layer, a link management micro-packet LMF of the adapter layer and a power consumption management micro-packet PMF of the adapter layer so as to distinguish different types of micro-packets at the protocol layer and the adapter layer, wherein the link management micro-packet LMF is used for transmitting link management messages, and the power consumption management micro-packet PMF is used for transmitting power consumption management micro-messages;
the micro-packet data field is used for storing data generated after the protocol layer of the transmitting end packs the messages of all channels to be transmitted according to a given rule, and the protocol layer of the receiving party obtains the micro-packet data from the field and unpacks the micro-packet data to the messages of all channels; at the transmitting end, the adapter layer transmits the link management information and the power consumption management information which are added into the data micro-packets of the protocol layer to the protocol layer through an interface between layers, and at the receiving end, the protocol layer transmits the link management information and the power consumption management information which are analyzed from the data micro-packets to the adapter layer through the interface between layers;
The link and power management information field is used for respectively storing link management information and power management information from different directions at a sender and a receiver;
other interface signal fields for clock, clock gating requests and replies, inter-layer micro-packet flow control and transmission of error states between the protocol layer and the adapter layer.
In addition, the invention also provides a chip, which comprises a plurality of core grains through a core grain interconnection interface, wherein the core grain interconnection interface comprises a protocol layer facing the core grain interconnection interface and an adapter interlayer interface circuit.
Optionally, the core interconnection interface is a core interconnection interface compatible with pcie1.0-4.0 protocol, the core interconnection interface multiplexes the protocol layer facing the core interconnection interface and the adapter layer of the interface circuit between adapter layers, and the lower layer of the adapter layer is connected with the physical layer circuit, and the upper layer of the adapter layer is sequentially connected with the transaction layer circuit PCI TL of pcie1.0-4.0 protocol and the protocol layer circuit PCI PL of pcie1.0-4.0 protocol so as to support pcie1.0-4.0 protocol and a custom protocol compatible with pcie1.0-4.0 protocol. Or, the core interconnection interface is a core interconnection interface compatible with the PCIE5.0-6.0 protocol, the core interconnection interface multiplexes the protocol layer facing the core interconnection interface and the adapter layer of the interface circuit between the adapter layers, and the lower layer of the adapter layer is connected with the physical layer circuit, and the upper layer of the adapter layer is connected with the UCIe protocol layer circuit of the PCIE5.0-6.0 protocol so as to support the PCIE5.0-6.0 protocol. Or, the core interconnection interface is a core interconnection interface compatible with CXL.io protocol, the core interconnection interface multiplexes the protocol layer facing the core interconnection interface and the adapter layer of the interface circuit between the adapter layers, and the lower layer of the adapter layer is connected with a physical layer circuit, and the upper layer of the adapter layer is connected with a UCie protocol layer circuit of CXL.io protocol so as to support the CXL.io protocol. Or, the core interconnection interface is a core interconnection interface compatible with a given custom protocol, the core interconnection interface multiplexes the protocol layer facing the core interconnection interface and the adapter layer of the interface circuit between the adapter layers, and the lower layer of the adapter layer is connected with the physical layer, and the upper layer of the adapter layer is connected with the custom protocol layer circuit of the given custom protocol so as to support the given custom protocol.
Compared with the prior art, the invention has the following advantages:
1) Compatibility with different protocols is achieved in a better way. Firstly, a circuit for attaching link management information and power consumption management information to a protocol layer data micro-packet is moved from an adapter layer to a protocol layer, so that a greater degree of freedom is given to protocol layer packing and unpacking logic, various different definitions of a micro-packet format on the management information domain position are supported, the support degree of an existing protocol is improved, and meanwhile, more flexible selection is provided for future protocol support. Secondly, the problem that a user needs to additionally design a data link layer to replace all functions of an adapter layer when Intel realizes compatibility by using a RAW mode in UCIe protocol standard is solved, and the design complexity of different protocols by using a core particle interconnection interface circuit is reduced.
2) A deeper decoupling of the protocol layer from the adapter layer is achieved. The invention can realize that the adaptation layer does not need to care how and where other domains of the data micro-packet from the protocol layer except the micro-packet type are defined, but rather care the function design of the adapter layer, such as reliability transmission (encoding and decoding of data check codes, error retransmission), link management and power consumption management. When the protocol layer is designed, the positions of link management and power consumption management information in the data micro-packets do not need to be reserved according to fixed rules, the definition of the domains can be reserved based on the target protocol to be compatible, the compatibility of the target protocol is realized, the reservation can be performed according to a self-defining mode, and the self-defining protocol is realized. The protocol layer and the adapter achieve complete decoupling in terms of the management information location in the micro-packet format.
3) Complete multiplexing of the adapter layer is achieved. Intel's UCIe implements multi-protocol support by completely bypassing the adapter layer, multiplexing only the physical layer, in order to achieve compatibility with third party (other than CXL, PCIe) protocols or custom protocols. The invention improves the multi-protocol compatible scheme of UCIe and can realize the support of multi-protocols under the condition of further multiplexing an adapter layer. The adapter layer can support protocol layers of different protocols and custom protocols, and a user does not need to additionally design a data link layer to replace and realize all functions of the adapter layer, so that the complete multiplexing of the adapter layer when the core interconnection interface supports multiple protocols is realized.
The advantages can promote more thorough standardization of the adapter layer and the physical layer in the core particle interconnection interface, and have better compatibility, stronger decoupling and higher multiplexing degree. Wherein compatibility refers to not only supporting the mainstream protocol standard, but also supporting new protocols that may appear in the future; decoupling means that the designs of the protocol layer and the adaptation layer can be separated from each other and developed independently. The normal operation of the adapter layer does not need to pay attention to the micro-packet format between the protocol layer and the adapter layer, and the protocol layer can flexibly select and is not constrained when the protocol layer performs position reservation on management information from the adapter layer in a message format; the degree of multiplexing refers to a protocol layer in which an adapter layer can support different protocols and can be multiplexed when supporting existing protocols and future protocols, without requiring a user to additionally design a data link layer to replace and implement the entire functions of the adapter layer.
Drawings
Fig. 1 is a circuit block diagram of a prior art die interconnect interface.
Fig. 2 is a 256-bit micro packet format defined by the uci protocol in the related art.
Fig. 3 is a 256-bit micro packet format defined by the pcie6.0 protocol in the prior art.
Fig. 4 is a specific format of FlitHdr field in 256-bit micro packet format of uci protocol in the prior art.
Fig. 5 is a specific format of DLLPHdr field in 256-bit micro packet format of pcie6.0 in the prior art.
Fig. 6 shows a 256-bit micro-packet format defined by the "chiplet" protocol in the prior art.
Fig. 7 is a schematic diagram of an interlayer link communication principle between a pcie1.0-4.0 protocol layer compatible with a uci physical layer and a uci protocol layer adopting CXL/cie5.0-6.0 protocol in the prior art.
Fig. 8 is a schematic diagram of an interface circuit between a protocol layer and an adapter layer in an embodiment of the invention.
Fig. 9 is a schematic diagram of an interface format between a protocol layer and an adapter layer in an embodiment of the present invention.
Fig. 10 is a schematic diagram of link management information and power management information according to an embodiment of the present invention.
Fig. 11 is an optimized schematic diagram of the interface hierarchy when the interface format and the circuit are compatible with the protocols in the embodiment of the present invention.
Detailed Description
As shown in fig. 8, the protocol layer and adapter interlayer interface circuit of the present embodiment for a Die to Die (D2D) interface includes a transmitting end interface circuit, which includes:
The credit management module is positioned at the protocol layer and used for generating credit information;
the data micro-packet (Flit) generating module is positioned on the protocol layer and is used for receiving messages of N channels (N is a natural number), credit information of the credit management module, link management information and power consumption management information from the adapter layer, packaging the messages from a plurality of channels according to a set message packaging rule to generate a data micro-packet, and filling the message into a reserved field in the data micro-packet when the credit information, the link management information and the power consumption management information are required to be added to the data micro-packet, and notifying an information sender; it should be noted that, which bits in the format of the data micro packet need to be reserved, are determined by the protocol layer according to the specification of the protocol to be compatible, and may also be determined according to the customized specification if the protocol does not need to be compatible with the existing protocol; at the protocol layer of the transmitting end, if the link and the power consumption management information are carried and transmitted by the data micro-packet, notifying the link management module and the power management module (transmitting party) of the adapter layer that the information is transmitted;
the link management module is positioned at the adapter layer and used for generating link management information to initialize a link and manage the state of the link, the link management information comprises retransmission control information to control the reliable transmission of the data micro-packet between the sending end and the receiving end, and the link management information is generated to be independent management micro-packet output when the data micro-packet generation module cannot attach the link management information;
The power management module is positioned on the adapter layer and used for generating power consumption management information to manage the power consumption state of the link, and generating independent management micro-packets for outputting the power consumption management information when the data micro-packet generation module cannot attach the power consumption management information;
and the multi-path arbiter is positioned on the adapter layer, and the input end of the multi-path arbiter is respectively connected with the output ends of the data micro-packet generating module, the link management module and the power management module and is used for carrying out arbitration on the data micro-packets output by the data micro-packet generating module, the link management module and the power management module and then sharing the physical link for transmission.
As shown in fig. 10, the retransmission control information in this embodiment includes allocating a request sequence number ReqNo to each micro packet at the transmitting end, and generating a response sequence number AckNo or a non-response sequence number NAckNo at the receiving end according to whether the micro packet is correctly received, where the response sequence number AckNo indicates that the micro packet identified as the request sequence number ReqNo has been correctly received; the non-reply sequence number, NAckNo, indicates that a micro packet identified as request sequence number, reqNo, has been received, but the data is checked for errors, and the micro packet needs to be retransmitted.
As shown in fig. 10, the power management information in this embodiment includes two types, i.e., pm_adp_tx and pm_adp_rx, where the pm_adp_tx is the power management information that the adapter layer needs to send to the opposite terminal, and includes request information for requesting to enter a certain power consumption state and response information for returning to be in a certain power consumption state; the PM ADP RX type is the power management information that the adapter layer receives from the peer.
On the one hand, the link management information and the power consumption management information are sent to a protocol layer at an adapter layer of a transmitting end, and are added into a data micro packet through a data micro packet generating module to be transmitted to a receiving party; on the other hand, an independent management micro packet (management Flit) is generated, and the management micro packet and the data micro packet are arbitrated by a multi-path arbiter and then share the physical link transmission. When the protocol layer cannot carry the link management information and the power consumption management information for transmission within a certain time due to the lack of the data micro-packet, the link management information and the power consumption management information are independently transmitted by generating the management micro-packet according to a certain rule.
As shown in fig. 8, the interface circuit between the protocol layer and the adapter layer further includes a receiving end interface circuit, and the receiving end interface circuit includes:
the decoder is positioned at the adapter layer and is used for analyzing the micro-packet from the physical link to determine whether the type of the micro-packet is a management micro-packet or a data micro-packet, if the type of the micro-packet is the management micro-packet, the micro-packet is sent to the power management module and the link management module of the receiving end, and if the type of the micro-packet is the data micro-packet, the micro-packet is sent to the data micro-packet analysis module;
the credit management module is positioned on the protocol layer and used for realizing the flow control of each channel from the transmitting end to the receiving end;
The data micro-packet analysis module is positioned on the protocol layer and used for analyzing the data micro-packet, sending the analyzed messages of the N channels into the corresponding channels respectively, if the data micro-packet contains credit information, sending the credit information to the credit management module, if the data micro-packet contains link management information, sending the link management information to the link management module, and if the data micro-packet contains power consumption management information, sending the power consumption management information to the power management module;
the link management module is positioned at the adapter layer and used for carrying out link state management according to the received link management information;
the power management module is positioned on the adapter layer and is used for managing the power consumption state of the link according to the received power consumption management information;
the output end of the decoder is respectively connected with the data micro-packet analysis module, the link management module and the power management module, and the output end of the data micro-packet analysis module is respectively connected with the credit management module, the link management module and the power management module.
At the adapter layer of the receiving party, the decoder module is responsible for analyzing and managing two types of management micro-packets and data micro-packets according to the micro-packet type field in the micro-packets. The management micro-packet is sent to a link management module and a power consumption management module, and needed link and power consumption management information is further obtained through analysis. At the protocol layer of the receiving party, the data micro-packet analysis module is responsible for obtaining link management information and power consumption management information which are added in the data micro-packet from the data micro-packet, and the link management information and the power consumption management information are sent to the link management module and the power management module of the adapter layer from the protocol layer. The data micro-packet analysis module also analyzes the messages sent to each channel and sends the messages to the corresponding receiving channels. The data micro-packet analysis module also analyzes the credit information loaded in the data micro-packet and sends the credit information into the credit management module. The credit management module realizes the flow control of each channel from the transmitting end to the receiving end.
As shown in fig. 9, the data transmission formats between the protocol layers and the adaptation layer of the transmitting end interface circuit and the receiving end interface circuit in this embodiment include the following field fields:
a micro packet type field for uniformly encoding a Data micro packet (Data Flit, DF) of a protocol layer, a link management micro packet (LMF) of an adapter layer, and a power management micro packet PMF (Power Management Flit, PMF) to distinguish different types of micro packets at the protocol layer and the adapter layer, wherein the link management micro packet LMF is used for transmitting a link management message, and the power management micro packet PMF is used for transmitting a power management micro message;
the micro-packet data field is used for storing data generated after the protocol layer of the transmitting end packs the messages of all channels to be transmitted according to a given rule, and the protocol layer of the receiving party obtains the micro-packet data from the field and unpacks the micro-packet data to the messages of all channels; at the transmitting end, the adapter layer transmits the link management information and the power consumption management information which are added into the data micro-packets of the protocol layer to the protocol layer through an interface between layers, and at the receiving end, the protocol layer transmits the link management information and the power consumption management information which are analyzed from the data micro-packets to the adapter layer through the interface between layers;
The link and power management information field is used for respectively storing link management information and power management information from different directions at a sender and a receiver;
other interface signal fields for clock, clock gating requests and replies, inter-layer micro-packet flow control and transmission of error states between the protocol layer and the adapter layer.
The field domain is an interface format between the protocol layer and the adapter layer, and also refers to a data organization format of the protocol layer and the adapter layer in a inter-core interconnection (D2D) interface, where the interface format includes, besides a data micro packet without any domain definition, link management information and power consumption management information from the adapter layer to the protocol layer, which need to be packed into the data micro packet to be sent, and link management information and power consumption management information from the protocol layer to the adapter, which are parsed from the received data micro packet. The protocol layer and adapter layer circuit refers to a packet packing and unpacking circuit of a protocol layer in a chip inter-particle interconnection (D2D) interface, a data path between the protocol layer and the adapter layer, and a generation and analysis circuit of a link management micro packet and a power consumption management micro packet of the adapter layer. At the sender, the circuit that attaches the link management information and the power consumption management information to the protocol layer data micro packet is moved from the adapter layer to the protocol layer, and is merged with the protocol layer packaging circuit. At the receiving side, the circuit for resolving the link management information and the power consumption management information from the data micro-packet is moved from the adapter layer to the protocol layer and is fused with the protocol layer unpacking circuit.
As shown in fig. 10, the interface between the protocol layer and the adapter layer includes link management information and power management information. The link management information includes link retransmission protocol related signals including request sequence number (ReqNo), acknowledgement sequence number (AckNo), and non-acknowledgement sequence number (NAckNo). The power management related signals include PM_ADP_TX and PM_ADP_RX. The PM_ADP_TX is power management information (which is sent by protocol layer packaging) which needs to be sent to the opposite end by the adapter layer, and comprises request information for requesting to enter a certain power consumption state and response information for returning to the certain power consumption state; pm_adp_rx receives power management information (obtained by protocol layer unpacking) from the peer for the adapter layer.
In addition, the embodiment also provides a chip, which comprises a plurality of core grains passing through a core grain interconnection interface, wherein the core grain interconnection interface comprises a protocol layer facing the core grain interconnection interface and an adapter interlayer interface circuit.
Fig. 11 (a) shows that in order for the uci protocol to implement the earlier PCIe1.0-4.0 protocol or custom protocol for core interconnect interface compatibility, the adapter layer needs to be set to bypass mode, and two layers of complete PCIe TL and DLL must be implemented on top of the adapter.
As shown in fig. 11 (b), as an alternative implementation manner, the core interconnect interface of this embodiment is a core interconnect interface compatible with pcie1.0-4.0 protocol, the core interconnect interface multiplexes the protocol layer facing the core interconnect interface and the adapter layer of the interface circuit between the adapter layers, and the lower layer of the adapter layer is connected to the physical layer circuit, and the upper layer of the adapter layer is sequentially connected to the transaction layer circuit PCI TL of pcie1.0-4.0 protocol and the protocol layer circuit PCI PL of pcie1.0-4.0 protocol to support pcie1.0-4.0 protocol and a custom protocol compatible with pcie1.0-4.0 protocol. After the protocol layer facing the core interconnection interface and the interface circuit between the adapter layers of the embodiment are adopted, when the protocol layer is compatible with PCIE1.0-4.0 or a custom protocol, the adapter layer provided by the invention can be multiplexed, and a DLL layer for link management is not required to be additionally added.
As shown in (c) of fig. 11, as an alternative embodiment, the core interconnect interface is a core interconnect interface compatible with pcie5.0-6.0 protocol, the core interconnect interface multiplexes the protocol layer facing the core interconnect interface and the adapter layer of the interface circuit between the adapter layers, and the lower layer of the adapter layer is connected to the physical layer circuit, and the upper layer of the adapter layer is connected to the uci protocol layer circuit of pcie5.0-6.0 protocol to support pcie5.0-6.0 protocol. After the protocol layer facing the core interconnection interface and the interface circuit between the adapter layers are adopted, compatibility of PCIE5.0-6.0 protocols specified in UCIe protocol is realized by multiplexing the adapter layer provided by the invention.
As shown in (c) of fig. 11, as an alternative embodiment, the core interconnection interface is a core interconnection interface compatible with the cxl.io protocol, the core interconnection interface multiplexes the protocol layer facing the core interconnection interface and the adapter layer of the interface circuit between the adapter layers, and the lower layer of the adapter layer is connected to the physical layer circuit, and the upper layer of the adapter layer is connected to the uci protocol layer circuit of the cxl.io protocol to support the cxl.io protocol. After the protocol layer facing the core interconnection interface and the interface circuit between the adapter layers are adopted, compatibility of CXL.io protocol specified in UCIe protocol is realized by multiplexing the adapter layer provided by the invention.
As shown in (d) of fig. 11, as an alternative embodiment, the core interconnection interface is a core interconnection interface compatible with a given custom protocol, the core interconnection interface multiplexes the protocol layer facing the core interconnection interface and the adapter layer of the interface circuit between the adapter layers, and the lower layer of the adapter layer is connected to the physical layer, and the upper layer of the adapter layer is connected to the custom protocol layer circuit of the given custom protocol to support the given custom protocol. After the protocol layer facing the core interconnection interface and the interface circuit between the adapter layers are adopted, the support of the custom protocol can be realized by multiplexing the adapter layer provided by the invention, the reusability of the adapter layer is improved, the complexity of adding an extra data link layer is reduced, and the more thorough standardization of the adapter layer and the physical layer in the core interconnection interface is promoted.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (10)
1. A core interconnect interface oriented protocol layer and adapter interlayer interface circuit comprising a transmit end interface circuit, the transmit end interface circuit comprising:
the credit management module is positioned at the protocol layer and used for generating credit information;
the data micro-packet generating module is positioned on the protocol layer and is used for receiving the messages of the N channels, the credit information of the credit management module, the link management information and the power consumption management information from the adapter layer, packaging the messages from the channels according to the set message packaging rule to generate a data micro-packet, filling the credit information, the link management information and the power consumption management information into a reserved field in the data micro-packet when the credit information, the link management information and the power consumption management information need to be added to the data micro-packet, and notifying an information sender;
The link management module is positioned at the adapter layer and used for generating link management information to initialize a link and manage the state of the link, the link management information comprises retransmission control information to control the reliable transmission of the data micro-packet between the sending end and the receiving end, and the link management information is generated to be independent management micro-packet output when the data micro-packet generation module cannot attach the link management information;
the power management module is positioned on the adapter layer and used for generating power consumption management information to manage the power consumption state of the link, and generating independent management micro-packets for outputting the power consumption management information when the data micro-packet generation module cannot attach the power consumption management information;
and the multi-path arbiter is positioned on the adapter layer, and the input end of the multi-path arbiter is respectively connected with the output ends of the data micro-packet generating module, the link management module and the power management module and is used for carrying out arbitration on the data micro-packets output by the data micro-packet generating module, the link management module and the power management module and then sharing the physical link for transmission.
2. The interface circuit between the protocol layer and the adapter layer for the core interconnection interface according to claim 1, wherein the retransmission control information comprises a request sequence number ReqNo allocated to each micro packet at the transmitting end, and a response sequence number AckNo indicating that the micro packet identified as the request sequence number ReqNo has been correctly received is generated at the receiving end according to whether the micro packet is correctly received or not, or a non-response sequence number nackn; the non-reply sequence number, NAckNo, indicates that a micro packet identified as request sequence number, reqNo, has been received, but the data is checked for errors, and the micro packet needs to be retransmitted.
3. The interface circuit between the protocol layer and the adapter layer for the core interconnection interface according to claim 2, wherein the power consumption management information includes two types, pm_adp_tx and pm_adp_rx, the pm_adp_tx being power management information that the adapter layer needs to send to the opposite terminal, including request information for requesting to enter a certain power consumption state and response information for returning to be in a certain power consumption state; the PM ADP RX type is the power management information that the adapter layer receives from the peer.
4. The core interconnect interface oriented protocol layer and adapter interlayer interface circuit of claim 3, further comprising a receiving end interface circuit, the receiving end interface circuit comprising:
the decoder is positioned at the adapter layer and is used for analyzing the micro-packet from the physical link to determine whether the type of the micro-packet is a management micro-packet or a data micro-packet, if the type of the micro-packet is the management micro-packet, the micro-packet is sent to the power management module and the link management module of the receiving end, and if the type of the micro-packet is the data micro-packet, the micro-packet is sent to the data micro-packet analysis module;
the credit management module is positioned on the protocol layer and used for realizing the flow control of each channel from the transmitting end to the receiving end;
The data micro-packet analysis module is positioned on the protocol layer and used for analyzing the data micro-packet, sending the analyzed messages of the N channels into the corresponding channels respectively, if the data micro-packet contains credit information, sending the credit information to the credit management module, if the data micro-packet contains link management information, sending the link management information to the link management module, and if the data micro-packet contains power consumption management information, sending the power consumption management information to the power management module;
the link management module is positioned at the adapter layer and used for carrying out link state management according to the received link management information;
the power management module is positioned on the adapter layer and is used for managing the power consumption state of the link according to the received power consumption management information;
the output end of the decoder is respectively connected with the data micro-packet analysis module, the link management module and the power management module, and the output end of the data micro-packet analysis module is respectively connected with the credit management module, the link management module and the power management module.
5. The interface circuit between the protocol layer and the adapter layer for a core interconnect interface according to claim 4, wherein the data transmission formats between the protocol layer and the adapter layer of the transmitting end interface circuit and the receiving end interface circuit comprise the following field fields:
The micro-packet type field is used for uniformly encoding a data micro-packet of the protocol layer, a link management micro-packet LMF of the adapter layer and a power consumption management micro-packet PMF of the adapter layer so as to distinguish different types of micro-packets at the protocol layer and the adapter layer, wherein the link management micro-packet LMF is used for transmitting link management messages, and the power consumption management micro-packet PMF is used for transmitting power consumption management micro-messages;
the micro-packet data field is used for storing data generated after the protocol layer of the transmitting end packs the messages of all channels to be transmitted according to a given rule, and the protocol layer of the receiving party obtains the micro-packet data from the field and unpacks the micro-packet data to the messages of all channels; at the transmitting end, the adapter layer transmits the link management information and the power consumption management information which are added into the data micro-packets of the protocol layer to the protocol layer through an interface between layers, and at the receiving end, the protocol layer transmits the link management information and the power consumption management information which are analyzed from the data micro-packets to the adapter layer through the interface between layers;
the link and power management information field is used for respectively storing link management information and power management information from different directions at a sender and a receiver;
other interface signal fields for clock, clock gating requests and replies, inter-layer micro-packet flow control and transmission of error states between the protocol layer and the adapter layer.
6. A chip comprising a plurality of die through a die interconnect interface, wherein the die interconnect interface comprises the protocol layer and adapter interlayer interface circuit for a die interconnect interface of any of claims 1-5.
7. The chip of claim 6, wherein the die interconnect interface is a die interconnect interface compatible with pcie1.0-4.0 protocol, the die interconnect interface multiplexes the protocol layer facing the die interconnect interface and an adapter layer of an adapter interlayer interface circuit, and a lower layer of the adapter layer is connected to a physical layer circuit, and an upper layer of the adapter layer is sequentially connected to a transaction layer circuit PCI TL of pcie1.0-4.0 protocol and a protocol layer circuit PCI PL of pcie1.0-4.0 protocol to support a pcie1.0-4.0 protocol and a custom protocol compatible with pcie1.0-4.0 protocol.
8. The chip of claim 6, wherein the die interconnect interface is a die interconnect interface compatible with pcie5.0-6.0 protocols, the die interconnect interface multiplexes the protocol layer facing the die interconnect interface and an adapter layer of an adapter interlayer interface circuit, and a lower layer of the adapter layer is connected to a physical layer circuit, and an upper layer of the adapter layer is connected to a uci protocol layer circuit of pcie5.0-6.0 protocols to support pcie5.0-6.0 protocols.
9. The chip of claim 6, wherein the die interconnect interface is a cxl.io protocol compliant die interconnect interface that multiplexes the protocol layer facing the die interconnect interface with an adapter layer of an adapter layer interface circuit, and wherein the adapter layer is connected to a physical layer circuit at a lower layer and to a uci protocol layer circuit of the cxl.io protocol at an upper layer to support the cxl.io protocol.
10. The chip of claim 6, wherein the die interconnect interface is a die interconnect interface compatible with a given custom protocol, the die interconnect interface multiplexes the protocol layer facing the die interconnect interface with an adapter layer of an interface circuit between adapter layers, and the adapter layer connects a physical layer below and a custom protocol layer circuit of the given custom protocol above to support the given custom protocol.
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Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007022694A1 (en) * | 2005-08-26 | 2007-03-01 | Huawei Technologies Co., Ltd. | An user plane protocol stack and a lossless movement method |
| US7346707B1 (en) * | 2002-01-16 | 2008-03-18 | Advanced Micro Devices, Inc. | Arrangement in an infiniband channel adapter for sharing memory space for work queue entries using multiply-linked lists |
| CN102394732A (en) * | 2011-09-06 | 2012-03-28 | 中国人民解放军国防科学技术大学 | Multi-micropacket parallel processing structure |
| US20140006670A1 (en) * | 2012-06-27 | 2014-01-02 | Mahesh Wagh | Controlling A Physical Link Of A First Protocol Using An Extended Capability Structure Of A Second Protocol |
| CN111104775A (en) * | 2019-11-22 | 2020-05-05 | 核芯互联科技(青岛)有限公司 | Network-on-chip topological structure and implementation method thereof |
| WO2020125839A1 (en) * | 2018-12-18 | 2020-06-25 | GRID INVENT gGmbH | Electronic element and electrically controlled display element |
| US20220222198A1 (en) * | 2021-12-22 | 2022-07-14 | Narasimha Lanka | Sideband interface for die-to-die interconnects |
| US20220342841A1 (en) * | 2021-12-22 | 2022-10-27 | Swadesh Choudhary | Die-to-die adapter |
| CN115563046A (en) * | 2022-09-29 | 2023-01-03 | 奇异摩尔(上海)集成电路设计有限公司 | High-speed interface, method and system suitable for Chiplet Chiplet interconnection |
| CN115794731A (en) * | 2023-01-29 | 2023-03-14 | 北京超摩科技有限公司 | Decoupling control method for transmission of multi-channel data link between core particles |
| CN116325706A (en) * | 2020-08-31 | 2023-06-23 | 美光科技公司 | Network credit return mechanism |
| CN117331881A (en) * | 2023-10-07 | 2024-01-02 | 北京微电子技术研究所 | Data transmission system suitable for aerospace chip interconnection protocol |
| CN117544433A (en) * | 2023-10-24 | 2024-02-09 | 海光信息技术股份有限公司 | Core particle, low-power consumption control method, chip and computer equipment |
-
2024
- 2024-03-04 CN CN202410241558.2A patent/CN117834755B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7346707B1 (en) * | 2002-01-16 | 2008-03-18 | Advanced Micro Devices, Inc. | Arrangement in an infiniband channel adapter for sharing memory space for work queue entries using multiply-linked lists |
| WO2007022694A1 (en) * | 2005-08-26 | 2007-03-01 | Huawei Technologies Co., Ltd. | An user plane protocol stack and a lossless movement method |
| CN102394732A (en) * | 2011-09-06 | 2012-03-28 | 中国人民解放军国防科学技术大学 | Multi-micropacket parallel processing structure |
| US20140006670A1 (en) * | 2012-06-27 | 2014-01-02 | Mahesh Wagh | Controlling A Physical Link Of A First Protocol Using An Extended Capability Structure Of A Second Protocol |
| WO2020125839A1 (en) * | 2018-12-18 | 2020-06-25 | GRID INVENT gGmbH | Electronic element and electrically controlled display element |
| CN111104775A (en) * | 2019-11-22 | 2020-05-05 | 核芯互联科技(青岛)有限公司 | Network-on-chip topological structure and implementation method thereof |
| CN116325706A (en) * | 2020-08-31 | 2023-06-23 | 美光科技公司 | Network credit return mechanism |
| US20220222198A1 (en) * | 2021-12-22 | 2022-07-14 | Narasimha Lanka | Sideband interface for die-to-die interconnects |
| US20220342841A1 (en) * | 2021-12-22 | 2022-10-27 | Swadesh Choudhary | Die-to-die adapter |
| CN115563046A (en) * | 2022-09-29 | 2023-01-03 | 奇异摩尔(上海)集成电路设计有限公司 | High-speed interface, method and system suitable for Chiplet Chiplet interconnection |
| CN115794731A (en) * | 2023-01-29 | 2023-03-14 | 北京超摩科技有限公司 | Decoupling control method for transmission of multi-channel data link between core particles |
| CN117331881A (en) * | 2023-10-07 | 2024-01-02 | 北京微电子技术研究所 | Data transmission system suitable for aerospace chip interconnection protocol |
| CN117544433A (en) * | 2023-10-24 | 2024-02-09 | 海光信息技术股份有限公司 | Core particle, low-power consumption control method, chip and computer equipment |
Non-Patent Citations (2)
| Title |
|---|
| ZHIQIANG CHEN等: "Traversal Packets: Opportunistic Bypass Packets for Deadlock Recovery", 《 IEEE DESIGN & TEST 》, 12 September 2022 (2022-09-12) * |
| 熊国杰等: "一种面向Chiplet互连的高效传输协议设计与实现", 《计算机工程与科学》, vol. 45, no. 8, 15 August 2023 (2023-08-15) * |
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