CN115086192A - Data processing method, device and system and monitoring card - Google Patents
Data processing method, device and system and monitoring card Download PDFInfo
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- 238000012544 monitoring process Methods 0.000 title claims abstract description 39
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- 238000004891 communication Methods 0.000 claims abstract description 96
- 238000000034 method Methods 0.000 claims abstract description 21
- 230000005540 biological transmission Effects 0.000 claims abstract description 15
- 238000004458 analytical method Methods 0.000 claims abstract description 14
- 230000015654 memory Effects 0.000 claims description 38
- 238000012545 processing Methods 0.000 claims description 34
- 230000006798 recombination Effects 0.000 claims description 3
- 238000005215 recombination Methods 0.000 claims description 3
- 238000007726 management method Methods 0.000 description 16
- 230000006870 function Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000012634 fragment Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 4
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- 125000004122 cyclic group Chemical group 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013523 data management Methods 0.000 description 1
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- 230000003287 optical effect Effects 0.000 description 1
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- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The embodiment of the invention discloses a data processing method, a device, a system and a monitoring card, wherein the method comprises the following steps: acquiring a first data frame which is sent by a communication board card to be tested and accords with an FC-AE-ASM protocol format; analyzing the first data frame to obtain corresponding communication data, and determining the frame type of the first data frame, wherein the frame type comprises: a correct data frame or an error data frame; and recombining the communication data into a second data frame conforming to the DMA interface data form for transmission, wherein the second data frame comprises: an error code identification field for indicating a frame type. The data processing method, the device, the system and the monitoring card disclosed by the embodiment of the invention can realize the data monitoring function of the FC-AE-ASM communication board card, upload error information to an upper computer for analysis by a user, and enable the user to fully know the communication condition of the communication board card to be detected.
Description
Technical Field
The present invention relates to, but not limited to, the field of communications, and in particular, to a data processing method, apparatus, system, and monitoring card.
Background
Avionics is rapidly developed into a digital system from an analog system, and a fiber channel protocol (FC-AE) in an avionics environment comprises a plurality of FC upper-layer protocols such as FC-AE-ASM, FC-AE-1553 and FC-AE-RDMA, and the protocols adapt to the extensive requirements of a unified network and can meet the development requirements of avionics.
An anonymous message transfer protocol (FC-AE-ASM) of an optical fiber channel in an avionics environment has been applied to a new generation avionics system with the advantages of low delay, high data communication efficiency, strong real-time communication capability, and the like, however, how to implement a data monitoring function for an FC-AE-ASM communication board card has become an urgent problem to be solved.
Disclosure of Invention
The embodiment of the application provides a data processing method, which comprises the following steps:
acquiring a first data frame which is sent by a communication board card to be tested and accords with an FC-AE-ASM protocol format;
analyzing the first data frame to obtain corresponding communication data, and determining a frame type of the first data frame, wherein the frame type comprises: a correct data frame or an error data frame;
recombining the communication data into a second data frame conforming to the DMA interface data form for transmission, wherein the second data frame comprises: an error code identification field to indicate the frame type.
An embodiment of the present application further provides a data processing apparatus, including: the system comprises a high-speed serial transceiver, an FC protocol processing module, an analysis module and a recombination module;
the high-speed serial transceiver is used for acquiring a first data frame which is sent by a communication board card to be tested and accords with an FC-AE-ASM protocol format;
the FC protocol processing module is used for analyzing the first data frame to obtain corresponding communication data;
the analysis module is configured to determine a frame type of the first data frame, where the frame type includes: a correct data frame or an error data frame;
the reassembly module is configured to reassemble the communication data into a second data frame conforming to a DMA interface data format, and send the second data frame, where the second data frame includes: an error code identification field to indicate the frame type.
The embodiment of the application also provides a monitoring card, which comprises a memory and a processor, wherein the memory is used for storing and executing instructions; the processor calls the execution instruction to execute the data processing method of any embodiment.
An embodiment of the present application further provides a data processing system, including: the system comprises a communication board card to be tested, an upper computer and the monitoring card in any embodiment, wherein the monitoring card is connected with the upper computer through a PCI-E bus, and the communication board card to be tested is communicated with the monitoring card by adopting an FC-AE-ASM protocol;
the communication board card to be tested is used for sending a first data frame which accords with the FC-AE-ASM protocol format to the monitoring card;
and the upper computer is used for receiving a second data frame sent by the monitoring card through the PCI-E bus.
Compared with the prior art, the data processing method, the data processing device, the data processing system and the monitoring card provided by at least one embodiment of the application have the following beneficial effects: all data frames of the FC-AE-ASM communication board card can be received and forwarded, error frames are reserved during forwarding, data receiving of the FC-AE-ASM communication board card can be achieved, and a data monitoring function of the FC-AE-ASM communication board card can be achieved. The error information is uploaded to the upper computer for user analysis, so that the user can fully know the communication condition of the communication board card to be detected, and the real condition of the transmitted data can be clear even if the data is in error.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the present application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.
Drawings
The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.
FIG. 1 is a flow chart of a data processing method according to an embodiment of the present invention;
fig. 2 is a block diagram of a data processing apparatus according to an exemplary embodiment of the present invention;
fig. 3 is a block diagram of a data processing apparatus according to another exemplary embodiment of the present invention;
FIG. 4 is a block diagram of a monitor card according to an exemplary embodiment of the present invention;
fig. 5 is a block diagram of a data processing system according to an exemplary embodiment of the present invention.
Detailed Description
The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.
Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
Fig. 1 is a flowchart of a data processing method according to an embodiment of the present invention, and as shown in fig. 1, the data processing method may include: s101, S102 and S103.
S101: and acquiring a first data frame which is sent by the communication board card to be tested and accords with the FC-AE-ASM protocol format.
The execution main body of the embodiment may be a data processing device or a monitoring card shown in any one of the following embodiments, and the monitoring card may adopt an FPGA chip to realize data reception and data monitoring on the FC-AE-ASM node communication board card to be tested, and transmit the monitoring data to the upper computer through the PCI-E interface.
The first data frame transmitted by the communication board card to be tested through the FC-AE-ASM protocol can be received, wherein the first data frame conforming to the FC-AE-ASM protocol format can be called as an FC-AE-ASM protocol frame or as an FC-AE-ASM frame.
S102: analyzing the first data frame to obtain corresponding communication data, and determining the frame type of the first data frame, wherein the frame type comprises: a correct data frame or an error data frame.
And analyzing the received first data frame conforming to the FC-AE-ASM protocol format to obtain the communication data of the communication board card to be tested, and determining the frame type of the first data frame according to the content of the relevant field in the first data frame. The communication data of the communication board card to be tested can be used for representing the communication condition of the communication board card to be tested, and the upper computer and the like can determine that the communication board card to be tested is normal in communication or has communication faults according to the communication data of the communication board card to be tested.
Table 1 shows a frame structure of the first data frame, and as shown in table 1, the first data frame may include: a Data Field (Data Field) Field and a Cyclic Redundancy Check (CRC) Field. In an example, the type of the first data frame may be determined to be a correct data frame or an erroneous data frame based on the length of the data field and/or the CRC field in the first data frame.
TABLE 1
SOFi is a start of frame delimiter that identifies whether a frame is the first frame of a sequence of frames.
And the Data Field is used for filling Data, and the filled Data is communication Data of the communication board card to be tested.
The CRC is a cyclic redundancy check code, and is 32-bit data for confirming whether received data is correct through CRC check. The detection principle of CRC is the same as that of the existing scheme, and this embodiment is not described herein again.
EOFn is an end-of-frame delimiter used to identify whether a frame is the last frame of a sequence of frames.
Frame Header is Frame Header, Message ID is Message identifier, Reserved-Security is Reserved Security field, Reserved field, Priority is Priority field, and Payload length is data length. When the padded data includes a data header, intermediate data, and a data trailer, the length of the data refers to the length of the intermediate data.
L may be 0 or 1, and when the length field of the data is equal to 0x00000000, that is, the value of Payload length is 0 byte, if L is 0, it indicates that the maximum length of the padded data is 16777216 bytes, and at this time, a carry bit of 24 bits is full, and a bit is required to be represented by 25 bits, and the value of Payload length is 16777216 bytes. If L is 1, the data length of the padding is 0 bytes, that is, the value of Payload length is 0 bytes. If the value of Payload length is 0, then L is significant; if the value of Payload length is not 0, then L has no meaning.
In an example, the error data frame may include: a CRC error frame, an ultra-short data frame, or an ultra-long data frame; the ultra-short data frame means that the length of a data field in the first data frame is smaller than a first preset length, and the ultra-long data frame means that the length of the data field in the first data frame is larger than a second preset length, and the second preset length is larger than the first preset length.
In this embodiment, it may be determined that the type of the first data frame is a correct data frame or an error data frame according to the length of the data field in the first data frame and/or the CRC field, and that the error data frame is a CRC error frame, an ultra-short data frame, or an ultra-long data frame. The monitoring function of the FC-AE-ASM communication board card can be realized, all data frames of the FC-AE-ASM communication board card can be received, the error data frame is reserved, after the error data frame is divided into the error data frame, the ultra-short data frame or the ultra-long data frame, the received correct data frame, the CRC error frame, the ultra-short data frame or the ultra-long data frame is identified and then uploaded to an upper computer for user analysis, and a user can fully know the communication condition of the communication board card to be detected.
And when the CRC check is correct and the length of the data field is greater than or equal to a first preset length and less than or equal to a second preset length, determining that the first data frame is a correct data frame.
Table 2 shows a frame structure of the error data frame, and as shown in table 2, it can be determined whether the type of the first data frame is an error frame according to the CRC field in the first data frame. Upon a CRC check error, the first data frame may be determined to be an erroneous data frame.
TABLE 2
Table 3 is a frame structure of the ultra-short data frame, and as shown in table 3, it may be determined whether the type of the first data frame is the ultra-short data frame according to the length of the data field in the first data frame. When the length of the data field is less than a first preset length, the first data frame can be determined to be an ultra-short data frame. Or, when the sum of the lengths of the data field, the priority field, the length field of the data, and the L field is less than a first preset length, it may be determined that the first data frame is an ultra-short data frame. The first preset length may be, but is not limited to, 4 bytes.
TABLE 3
Table 4 shows a frame structure of the ultra-long data frame, and as shown in table 4, it may be determined whether the type of the first data frame is the ultra-long data frame according to the length of the data field in the first data frame. And when the length of the data field is greater than a second preset length, determining that the first data frame is a super-long data frame. The second predetermined length may be, but is not limited to, 2096 bytes.
TABLE 4
S103: recombining the communication data into a second data frame conforming to a Direct Memory Access (DMA) interface data form for transmission, where the second data frame may include: an error code identification field for indicating a frame type.
In a conventional data scheme for receiving the FC-AE-ASM communication board card, an error frame is filtered, only a correct data frame is received, only the FC-AE-ASM data can be received, and the function of monitoring the data frame of the communication board card to be detected cannot be realized.
In this embodiment, all data frames of the FC-AE-ASM communication board card can be received and forwarded, and an error frame is retained during forwarding, for example, all received data frames can be sent to an upper computer, so that data reception of the FC-AE-ASM communication board card can be realized, and a data monitoring function of the FC-AE-ASM communication board card can be realized. The error information is uploaded to an upper computer for user analysis, so that a user can fully know the communication board card to be detected, and the real situation of the transmitted data can be clear even if the data is in error.
The received data can be uploaded to an upper computer through a DMA interface, an error code identification field is added in a data stream uploaded by the DMA for identifying the type of the received frame, a received correct data frame or an error data frame (such as a CRC error frame, an ultra-short data frame or an ultra-long data frame) can be identified through the error code identification field, and the identified correct data frame or the identified error data frame is uploaded to the upper computer for analysis by a user, so that the communication condition of the communication board card to be detected can be conveniently analyzed and positioned.
In an example, the error code identification field may be represented in four bytes, 0x00000000 represents a correct data frame, 0x00000001 represents a CRC error frame, 0x00000002 represents an ultra-short data frame, and 0x00000003 represents an ultra-long data frame.
The second data frame, which conforms to the DMA interface data form, may be referred to as a DMA data frame, or as a DMA frame.
Table 5 shows a frame structure of the second data frame, and as shown in table 5, the frame structure of the second data frame may include an error code identification field, a header field of the first data frame, a data field filled in a data field of the first data frame, and a trailer and a CRC field of the first data frame. The error code identification field is used to indicate the category of the received data frame, and the received correct data frame or error data frame (such as CRC error frame, ultra-short data frame or ultra-long data frame) can be identified by the error code identification field.
The frame head field of the first data frame, the data field filled in the data field of the first data frame, and the frame tail and CRC field of the first data frame are used for representing the received communication data of the communication board.
TABLE 5
In an example, the second data frame may further include: the predefined generalized frame header field may include: a field for storing a timestamp of receiving the first data frame. The generalized frame header field is a frame header defined in advance, and can include a field for receiving a timestamp of a first data frame, so that the timestamp of the received frame is recorded, and the state of the communication board card to be tested can be conveniently analyzed and positioned by adding the timestamp of the received frame.
In an example, the preset generalized frame header field may further include a data length field for indicating the length of the data filled in the first data frame data field, and identification information for indicating some identification information uploaded to the upper computer, such as, but not limited to, message identification information.
In an example, the second data frame may further include: a DMA frame header field, which may include: a physical location field of the DMA interface and a data length field for indicating the length of data filled in the first data frame data field.
The data processing method provided by the embodiment of the invention can receive and forward all data frames of the FC-AE-ASM communication board card, and can keep error frames during forwarding, thereby realizing data reception of the FC-AE-ASM communication board card and data monitoring function of the FC-AE-ASM communication board card. The error information is uploaded to an upper computer for user analysis, so that a user can fully know the communication board card to be detected, and the real situation of the transmitted data can be clear even if the data is in error.
In an exemplary embodiment of the present invention, after parsing the first data frame to obtain corresponding communication data, the method may further include:
the method comprises the following steps of accessing an external DDR memory by adopting a preset receiving and transmitting alternation rule, writing communication data into a receiving area in the DDR memory when the preset receiving and transmitting alternation rule indicates sending access, and dividing the DDR memory into two areas: a reception area and a transmission area.
In this embodiment, the DDR memory may communicate with an external DDR memory, and read data from a sending area of the DDR memory, or write data into a receiving area of the DDR memory. The DDR memory is accessed in a receiving and sending alternative access mode, data sending and receiving can be achieved by using only one DDR memory, the problems that sending and receiving are achieved by using two DDR memories respectively, one DDR is only used for sending data, and one DDR is only used for receiving data are solved, and cost can be saved. And the DDR cache space is divided into a receiving area and a sending area, so that the cache space is optimized.
In one example, the DDR memory may include DDR3 memory.
Fig. 2 is a block diagram of a data processing apparatus according to an exemplary embodiment of the present invention, and fig. 3 is a block diagram of a data processing apparatus according to another exemplary embodiment of the present invention, and as shown in fig. 2 and fig. 3, the data processing apparatus may include: a high-speed serial transceiver 21, an FC protocol processing module 22, an analysis module 23, and a reassembly module 24.
The data processing device may be a Field-Programmable Gate Array (FPGA) chip.
And the high-speed serial transceiver is used for acquiring a first data frame which is sent by the communication board card to be tested and conforms to the FC-AE-ASM protocol format. The high-speed serial transceiver realizes the transceiving of high-speed data, decodes and converts the received data, and codes and converts the data to be transmitted. When the data processing device is an FPGA chip, the receiving and sending of high-speed data can be realized by calling a Gigabit Transceiver (GTP) through the FPGA.
And the FC protocol processing module is used for analyzing the first data frame to obtain corresponding communication data. The FC protocol processing module is responsible for framing, sending, receiving and analyzing the protocol, forming the sent data into a form conforming to an FC-AE-ASM protocol frame and sending the data, and analyzing the received FC-AE-ASM protocol data according to requirements to obtain effective information.
An analysis module configured to determine a frame type of the first data frame, wherein the frame type may include: a correct data frame or an error data frame. The analysis module is used for analyzing and judging the received FC-AE-ASM protocol frame so as to determine that the first data frame is a correct data frame or an error data frame and determine that the error data frame is a CRC error frame, an ultra-short data frame or an ultra-long data frame.
The reassembly module is configured to reassemble the communication data into a second data frame conforming to the DMA interface data format for transmission, where the second data frame may include: an error code identification field for indicating a frame type. The recombination module is responsible for recombining the received communication data into a data stream which accords with the data form of the DMA interface so as to upload the data stream to the upper computer through the DMA interface.
The data processing apparatus provided in the embodiment of the present invention is used for executing the technical solution of any method embodiment, and the implementation principle and the implementation effect thereof are similar, and are not described herein again.
In an example embodiment of the present invention, as shown in fig. 3, the data processing apparatus may further include: the cache arbitration module 25 is configured to access an external DDR memory by using a preset transceiving alternation rule, and when the preset transceiving alternation rule indicates sending access, write communication data into a receiving area in the DDR memory, where the DDR memory is divided into two areas: a reception area and a transmission area.
As shown in fig. 3, the cache arbitration module may be connected to the off-chip cache module 26, which uses the high-speed DDR3 as an off-chip cache, and divides the cache space of the DDR3 memory into two equal parts: the sending area and the receiving area optimize the buffer space. The cache arbitration module can arbitrate access to the DDR3 memory in a receiving and sending alternate access mode, can realize sending and receiving of data by using only one DDR memory, avoids the problems that sending and receiving are respectively realized by using two DDR memories, one DDR is only used for sending data, and one DDR is only used for receiving data, and can save cost.
In an example, the analysis module is further to receive address management of data storage and management of access to DDR3 memory.
In an example embodiment of the present invention, as shown in fig. 3, the data processing apparatus may further include: the redundancy management module 27 is configured to manage redundant transceiving of two transceiving ports (or transceiving channels), such as serial transceiving a and serial transceiving B. In this embodiment, the communication board card to be tested can communicate through the two transceiving ports, serial transceiving is realized through the two transceiving ports, the redundancy management module can manage the two transceiving ports, normal operation of at least one transceiving port is ensured, and data transmission or reception with the communication board card to be tested is realized.
In an example embodiment of the present invention, as shown in fig. 3, the data processing apparatus may further include: a user interface module 28 and a host interface 29. The user interface module can receive a second data frame which is sent by the reconfiguration module and accords with the DMA interface data form, and uploads the second data frame to the host interface through the DMA. The host interface can call the PCI-E core to communicate with the upper computer and upload the second data frame to the upper computer.
In an example, the data processing device can send data or configuration information, receive the data or configuration information sent by the upper computer and forward the data or configuration information to the communication board card to be tested. The host computer can issue data to be sent and configuration information to the host computer interface through a high-speed serial computer expansion bus (PCI-E or PCIE) interface, the host computer interface can call a PCI-E core to communicate with the host computer, receive the data and/or the configuration information issued by the host computer interface through DMA, and the user interface module receives the data issued by the host computer interface through I/O. The user interface module receives the configuration information through the I/O interface to update the configuration table in real time, and the configuration table is configured with relevant information of sending and receiving functions, such as information of a receiving and sending port and management information of the off-chip cache module.
In an example embodiment of the present invention, the data processing apparatus may implement transmission of data or configuration information, and as shown in fig. 3, the data processing apparatus may further include: a transmission fragment management module 30, a transmission buffer module 31, and an interrupt management and reception buffer module 32.
The sending fragment management module is used for realizing the sending fragment management of the data, carrying out fragment management and sending on the data to be sent received by the DMA of the user interface module, and realizing the automatic fragment of the data to be sent.
The sending cache module is used for being responsible for address management and read-write access DDR3 management of data storage to be sent.
The interrupt management and receive cache module is responsible for accessing DDR3 management. And interrupting and uploading the burst message, wherein the interrupting and uploading of the burst message refers to interrupting and receiving the data sent by the communication board card to be tested if the upper computer issues the data to be sent at the moment when receiving the data sent by the communication board card to be tested, and interrupting and uploading the data sent by the communication board card to be tested to the upper computer.
In an example embodiment of the present invention, as shown in fig. 3, the data processing apparatus may further include: a link maintenance module 33 and a clock management module 34.
The clock management module is used for distributing clocks in a data processing device (such as an FPGA) and is responsible for synchronous management of the clocks inside the whole FPGA.
The link maintenance module is responsible for maintenance of FC bottom primitive, and is used for maintaining synchronous links, maintaining on-off of optical fibers, link errors and the like.
Fig. 4 is a block diagram of a monitoring card according to an exemplary embodiment of the present invention, and as shown in fig. 4, the monitoring card may include: a memory 41 and a processor 42.
The memory is used for storing and executing instructions, and the processor may be a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits that implement embodiments of the present invention. When the monitoring card is operated, the processor is communicated with the memory, and the processor calls the execution instruction to execute the following operations:
acquiring a first data frame which is sent by a communication board card to be tested and accords with an FC-AE-ASM protocol format;
analyzing the first data frame to obtain corresponding communication data, and determining a frame type of the first data frame, wherein the frame type comprises: a correct data frame or an error data frame;
recombining the communication data into a second data frame conforming to the DMA interface data form for transmission, wherein the second data frame comprises: an error code identification field to indicate the frame type.
In an example embodiment of the present invention, the processor is further configured to:
after the first data frame is analyzed to obtain corresponding communication data, a preset transceiving alternation rule is adopted to access an external DDR memory, when the preset transceiving alternation rule indicates sending access, the communication data are written into a receiving area in the DDR memory, and the DDR memory is divided into two areas: a reception area and a transmission area.
Fig. 5 is a block diagram of a data processing system according to an exemplary embodiment of the present invention, and as shown in fig. 5, the data processing system may include: the system comprises a communication board card 51 to be tested, an upper computer 52 and a monitoring card 53 shown in any embodiment, wherein the monitoring card can be connected with the upper computer through a PCI-E bus, and the communication board card to be tested is communicated with the monitoring card by adopting an FC-AE-ASM protocol;
the communication board card to be tested is used for sending a first data frame which accords with an FC-AE-ASM protocol format to the monitoring card or receiving a data frame to be sent which accords with the FC-AE-ASM protocol format and is sent by the monitoring card;
and the upper computer is used for receiving a second data frame sent by the monitoring card through the PCI-E bus or sending data to be sent or configuration information to the monitoring card through the PCI-E bus.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Claims (10)
1. A data processing method, comprising:
acquiring a first data frame which is sent by a communication board card to be tested and accords with an FC-AE-ASM protocol format;
analyzing the first data frame to obtain corresponding communication data, and determining a frame type of the first data frame, wherein the frame type comprises: a correct data frame or an error data frame;
recombining the communication data into a second data frame conforming to the DMA interface data form for transmission, wherein the second data frame comprises: an error code identification field to indicate the frame type.
2. The method of claim 1, wherein the erroneous data frame comprises: a CRC error frame, an ultra-short data frame, or an ultra-long data frame;
the ultra-short data frame refers to the fact that the length of a data field in the first data frame is smaller than a first preset length, the ultra-long data frame refers to the fact that the length of the data field in the first data frame is larger than a second preset length, and the second preset length is larger than the first preset length.
3. The method of claim 2, wherein the error code identification field is represented by four bytes, 0x00000000 represents a correct data frame, 0x00000001 represents a CRC error frame, 0x00000002 represents an ultra-short data frame, and 0x00000003 represents an ultra-long data frame.
4. The method of claim 1 or 2, wherein the second data frame further comprises: a preset generalized frame header field, the generalized frame header field comprising: a field for storing a timestamp of receiving the first data frame.
5. The method of claim 4, wherein the second data frame further comprises: a frame header field, the frame header field comprising: a physical location field and a data length field of the DMA interface.
6. The method of claim 1, wherein after parsing the first data frame to obtain corresponding communication data, the method further comprises:
the method comprises the following steps of accessing an external DDR memory by adopting a preset receiving and transmitting alternation rule, writing communication data into a receiving area in the DDR memory when the preset receiving and transmitting alternation rule indicates sending access, and dividing the DDR memory into two areas: a reception area and a transmission area.
7. A data processing apparatus, characterized by comprising: the system comprises a high-speed serial transceiver, an FC protocol processing module, an analysis module and a recombination module;
the high-speed serial transceiver is used for acquiring a first data frame which is sent by a communication board card to be tested and accords with an FC-AE-ASM protocol format;
the FC protocol processing module is used for analyzing the first data frame to obtain corresponding communication data;
the analysis module is configured to determine a frame type of the first data frame, where the frame type includes: a correct data frame or an error data frame;
the reassembly module is configured to reassemble the communication data into a second data frame conforming to a DMA interface data format, and send the second data frame, where the second data frame includes: an error code identification field to indicate the frame type.
8. The apparatus of claim 7, further comprising: the cache arbitration module is used for accessing an external DDR memory by adopting a preset transceiving alternation rule, writing the communication data into a receiving area in the DDR memory when the preset transceiving alternation rule indicates sending access, and dividing the DDR memory into two areas: a reception area and a transmission area.
9. A monitor card comprising a memory for storing execution instructions and a processor; the processor calls the execution instruction for executing the data processing method according to any one of claims 1 to 6.
10. A data processing system, comprising: the monitoring card comprises a communication board card to be tested, an upper computer and the monitoring card according to claim 9, wherein the monitoring card is connected with the upper computer through a PCI-E bus, and the communication board card to be tested is communicated with the monitoring card by adopting an FC-AE-ASM protocol;
the communication board card to be tested is used for sending a first data frame which accords with the FC-AE-ASM protocol format to the monitoring card;
and the upper computer is used for receiving a second data frame sent by the monitoring card through the PCI-E bus.
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