CN117833912A - Fractional frequency division phase-locked loop based on phase interpolation and sampling - Google Patents
Fractional frequency division phase-locked loop based on phase interpolation and sampling Download PDFInfo
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Abstract
The invention provides a fractional frequency-division phase-locked loop based on phase interpolation and sampling, wherein the input of a sampling circuit and a charge pump module is a reference clock signal, and the output end of a frequency locking module is used as the clock output of the phase-locked loop; the charge pump module performs charge and discharge according to the reference clock signal, controls the frequency locking module to perform frequency locking, and outputs clock waveform signals of a plurality of phases to the phase interpolation module; the phase interpolation module interpolates the phase of the clock waveform signal according to the decimal signal output by the decimal sigma-delta modulator, and selects a target clock waveform signal from the clock waveform signal and sends the target clock waveform signal to the sampling circuit; the sampling circuit samples the rising edge of the target clock waveform signal, determines sampling voltage and outputs the sampling voltage to the transconductance amplifier, and the transconductance amplifier converts the sampling voltage into control current of the frequency locking module to control the frequency of the frequency locking module. The noise of the phase-locked loop can be effectively reduced, and the area is smaller.
Description
Technical Field
The present disclosure relates to the field of electronic circuits, and in particular, to a fractional frequency pll based on phase interpolation and sampling.
Background
A phase locked loop is a negative feedback control system that uses a voltage generated by phase synchronization to detune a voltage controlled oscillator to generate a target frequency. The frequency and the phase of an oscillation signal in the loop are controlled by using an externally input reference signal, so that the automatic tracking of the frequency of an output signal to the frequency of an input signal is realized.
At present, the sub-sampling technology can reduce noise in the bandwidth of the phase-locked loop, but is mainly applied to the integer phase-locked loop, in order to realize the fractional frequency division of the phase-locked loop, a time-to-digital converter (TDC) module is added after a clock is input, and the fractional sigma-delta modulator is used for controlling the TDC module to realize the fractional frequency division, however, the mode requires that the TDC module has higher precision, otherwise higher noise is introduced, and meanwhile, the power consumption is higher. In addition, when fractional division is implemented, the bandwidth of the phase-locked loop must also be relatively low to suppress the noise of the fractional sigma-delta modulator, which also causes a problem of large area.
Disclosure of Invention
The embodiment of the disclosure at least provides a fractional frequency-division phase-locked loop based on phase interpolation and sampling, which can effectively reduce low-frequency phase noise of the phase-locked loop, and suppress sigma delta noise at the same time, so that the overall noise of the phase-locked loop is reduced, and meanwhile, the phase-locked loop has a smaller area.
The embodiment of the disclosure provides a fractional frequency phase-locked loop based on phase interpolation and sampling, comprising: the device comprises a charge pump module, a frequency locking module, a phase interpolation module, a decimal sigma-delta modulator, a sampling circuit and a transconductance amplifier;
the sampling circuit, the transconductance amplifier, the frequency locking module and the phase interpolation module are sequentially connected; the charge pump module is connected in parallel between the input end of the sampling circuit and the output end of the transconductance amplifier; the decimal sigma-delta modulator is connected with the phase interpolation module;
the input of the sampling circuit and the charge pump module is a reference clock signal, and the output end of the frequency locking module is used as the clock output of the phase-locked loop;
the charge pump module performs charge and discharge according to the reference clock signal, controls the frequency locking module to perform frequency locking, and outputs clock waveform signals of a plurality of phases to the phase interpolation module by the frequency locking module;
the phase interpolation module interpolates the phase of the clock waveform signal according to the decimal signal output by the decimal sigma-delta modulator, and selects a target clock waveform signal from the clock waveform signals to send to the sampling circuit;
the sampling circuit samples the rising edge of the target clock waveform signal, determines sampling voltage, outputs the sampling voltage to the transconductance amplifier, and converts the sampling voltage into control current of the frequency locking module by the transconductance amplifier so as to control the frequency of the frequency locking module.
In an alternative embodiment, the charge pump module includes a phase frequency detector and a charge pump;
the phase frequency detector generates an upper switch control signal and a lower switch control signal according to the input reference clock signal;
and the charge pump charges and discharges according to the upper switch control signal and the lower switch control signal.
In an alternative embodiment, the frequency locking module includes: low pass filter and ring oscillator, wherein:
the low-pass filter receives a charge-discharge signal of the charge pump module and converts the charge-discharge signal into a control voltage of the ring oscillator;
the ring oscillator starts to oscillate after receiving the control voltage to achieve frequency locking.
In an alternative embodiment, the fractional sigma-delta modulator comprises a sigma-delta modulation unit and an accumulator;
the input of the decimal sigma-delta modulator is a control word signal, wherein the control word signal consists of an integer part and a decimal part;
and after adding a preset deviation signal to the control word signal of the decimal part, outputting a decimal control signal for controlling the phase interpolation module to perform phase interpolation through the accumulator, wherein the deviation signal is used for controlling the decimal part interval range of the control word signal.
In an alternative embodiment, the phase interpolation module includes: the time sequence controller, the decoder, the current digital-to-analog converter and the interpolation capacitor;
the decoder converts the small-scale control signal into a control signal of the current digital-to-analog converter, wherein the control signal is used for controlling the output current of the current digital-to-analog converter;
the current output by the current digital-to-analog converter charges the interpolation capacitor, and the voltage change speed of the interpolation capacitor is influenced according to the output current, so that phase interpolation is realized;
after receiving the clock waveform signal output by the frequency locking module, resetting the voltage value of the interpolation capacitor by the time sequence controller according to the clock waveform signal, and after the resetting is stopped, starting charging the interpolation capacitor.
In an alternative embodiment, the sampling circuit includes a first delay unit, a second delay unit, a first inverter, a second inverter, a first transmission gate, a second transmission gate, and a sampling capacitor;
the first delay unit is connected with the first inverter; the second delay unit is connected with the second inverter; the input end of the second delay unit is connected between the first delay unit and the first inverter;
one end of the first transmission gate is connected with the phase interpolation module, and the other end of the first transmission gate is connected with the second transmission gate; the second transmission gate is connected with the transconductance amplifier;
one end of the sampling capacitor is connected between the first transmission gate and the second transmission gate, and the other end of the sampling capacitor is grounded;
the control end of the first transmission gate is connected with the first delay unit, and the inverse control end of the first transmission gate is connected with the first inverter;
the control end of the second transmission gate is connected with the second delay unit, and the inverse control end of the second transmission gate is connected with the second inverter.
In an alternative embodiment, the reference clock signal is input to the first delay unit, the first delay unit outputs a sampling clock signal, and the second delay unit outputs a holding clock signal after processing;
the first transmission gate samples the target clock waveform signal according to the sampling clock signal, and the sampled voltage obtained by sampling is kept in the sampling capacitor;
and after the sampling is finished, the holding clock signal is released, and the sampling voltage on the sampling capacitor is output to the transconductance amplifier.
The embodiment of the present disclosure further provides a control method of a fractional-n pll based on phase interpolation and sampling, which is applied to the fractional-n pll based on phase interpolation and sampling according to any one of the above embodiments, where the fractional-n pll includes: the charge pump module, the frequency lock module, the phase interpolation module, the fractional sigma-delta modulator, the sampling circuit, and the transconductance amplifier, the method comprising:
respectively inputting reference clock signals to the sampling circuit and the charge pump module, and outputting clocks by the output end of the frequency locking module;
controlling the charge pump module to charge and discharge according to the reference clock signal, controlling the frequency locking module to lock the frequency, and outputting clock waveform signals of a plurality of phases to the phase interpolation module by the frequency locking module;
controlling the phase interpolation module to interpolate the phase of the clock waveform signal according to the decimal signal output by the decimal sigma-delta modulator, and selecting a target clock waveform signal from the clock waveform signal to send to the sampling circuit;
and controlling the sampling circuit to sample the rising edge of the target clock waveform signal, determining a sampling voltage, outputting the sampling voltage to the transconductance amplifier, and converting the sampling voltage into the control current of the frequency locking module by the transconductance amplifier so as to control the frequency of the frequency locking module.
The embodiment of the disclosure also provides an electronic device, including: a processor, a memory and a bus, the memory storing machine readable instructions executable by the processor, the processor and the memory communicating over the bus when the electronic device is running, the machine readable instructions when executed by the processor performing the steps of any one of the possible embodiments of the above described phase interpolation and sampling based fractional pll control method or the above described phase interpolation and sampling based fractional pll control method.
The disclosed embodiments also provide a computer readable storage medium having a computer program stored thereon, which when executed by a processor performs the steps of any one of the above-described methods for controlling a fractional-n pll based on phase interpolation and sampling, or the above-described methods for controlling a fractional-n pll based on phase interpolation and sampling.
The disclosed embodiments also provide a computer program product comprising a computer program/instructions which, when executed by a processor, implement the steps of the above-described method of controlling a fractional-n pll based on phase interpolation and sampling, or any of the possible implementations of the above-described method of controlling a fractional-n pll based on phase interpolation and sampling.
The embodiment of the disclosure provides a fractional frequency phase-locked loop based on phase interpolation and sampling, which comprises: the input of the sampling circuit and the charge pump module is a reference clock signal, and the output end of the frequency locking module is used as the clock output of the phase-locked loop; the charge pump module performs charge and discharge according to the reference clock signal, controls the frequency locking module to perform frequency locking, and outputs clock waveform signals of a plurality of phases to the phase interpolation module through the frequency locking module; the phase interpolation module interpolates the phase of the clock waveform signal according to the decimal signal output by the decimal sigma-delta modulator, and selects a target clock waveform signal from the clock waveform signals to send to the sampling circuit; the sampling circuit samples the rising edge of the target clock waveform signal, determines a sampling voltage, outputs the sampling voltage to the transconductance amplifier, and converts the sampling voltage into a control current of the frequency locking module by the transconductance amplifier so as to control the frequency of the frequency locking module. The low-frequency phase noise of the phase-locked loop can be effectively reduced, and the sigma delta noise is suppressed, so that the overall noise of the phase-locked loop is reduced, and the phase-locked loop has a smaller area.
The foregoing objects, features and advantages of the disclosure will be more readily apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the embodiments are briefly described below, which are incorporated in and constitute a part of the specification, these drawings showing embodiments consistent with the present disclosure and together with the description serve to illustrate the technical solutions of the present disclosure. It is to be understood that the following drawings illustrate only certain embodiments of the present disclosure and are therefore not to be considered limiting of its scope, for the person of ordinary skill in the art may admit to other equally relevant drawings without inventive effort.
Fig. 1 shows a schematic diagram of a fractional-n pll based on phase interpolation and sampling according to an embodiment of the present disclosure;
FIG. 2 shows a schematic diagram of a fractional sigma-delta modulator provided by an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a phase interpolation module according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of a sampling circuit according to an embodiment of the disclosure;
FIG. 5 illustrates a flow chart of a method of controlling a fractional-N PLL based on phase interpolation and sampling provided by an embodiment of the present disclosure;
fig. 6 shows a schematic diagram of an electronic device provided by an embodiment of the disclosure.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. The components of the embodiments of the present disclosure, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the disclosure, as claimed, but is merely representative of selected embodiments of the disclosure. All other embodiments, which can be made by those skilled in the art based on the embodiments of this disclosure without making any inventive effort, are intended to be within the scope of this disclosure.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The term "and/or" is used herein to describe only one relationship, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
It is found that, at present, the sub-sampling technique can reduce noise in the bandwidth of the phase-locked loop, but is mainly applied to the integer phase-locked loop, in order to realize the fractional frequency division phase-locked loop, a time-to-digital converter (TDC) module is added after a clock is input, and the fractional sigma-delta modulator is used for controlling the TDC module to realize the fractional frequency division, however, this mode requires that the TDC module must have higher precision, otherwise higher noise is introduced, and meanwhile, the power consumption is higher. In addition, when fractional division is implemented, the bandwidth of the phase-locked loop must also be relatively low to suppress the noise of the fractional sigma-delta modulator, which also causes a problem of large area.
Based on the above study, the present disclosure provides a fractional-n pll based on phase interpolation and sampling, comprising: the input of the sampling circuit and the charge pump module is a reference clock signal, and the output end of the frequency locking module is used as the clock output of the phase-locked loop; the charge pump module performs charge and discharge according to the reference clock signal, controls the frequency locking module to perform frequency locking, and outputs clock waveform signals of a plurality of phases to the phase interpolation module through the frequency locking module; the phase interpolation module interpolates the phase of the clock waveform signal according to the decimal signal output by the decimal sigma-delta modulator, and selects a target clock waveform signal from the clock waveform signals to send to the sampling circuit; the sampling circuit samples the rising edge of the target clock waveform signal, determines a sampling voltage, outputs the sampling voltage to the transconductance amplifier, and converts the sampling voltage into a control current of the frequency locking module by the transconductance amplifier so as to control the frequency of the frequency locking module. The low-frequency phase noise of the phase-locked loop can be effectively reduced, and the sigma delta noise is suppressed, so that the overall noise of the phase-locked loop is reduced, and the phase-locked loop has a smaller area.
For the sake of understanding the present embodiment, first, a detailed description will be given of a fractional-n pll based on phase interpolation and sampling disclosed in the present embodiment, referring to fig. 1, which is a schematic structural diagram of a fractional-n pll 100 based on phase interpolation and sampling provided in the present embodiment.
As shown in fig. 1, the fractional-n phase-locked loop 100 based on phase interpolation and sampling includes: a charge pump block 110, a frequency lock block 120, a phase interpolation block 130, a fractional sigma-delta modulator 140, a sampling circuit 150, and a transconductance amplifier 160. The charge pump module 110 includes a phase frequency detector 111 and a charge pump 112; the frequency locking module 120 includes: a low pass filter 121 and a ring oscillator 122.
Specifically, the sampling circuit 150, the transconductance amplifier 160, the frequency locking module 120, and the phase interpolation module 130 are sequentially connected; the charge pump module 110 is connected in parallel between the input of the sampling circuit 150 and the output of the transconductance amplifier 160; the fractional sigma-delta modulator 140 is connected to the phase interpolation module 130.
In an implementation, the inputs of the sampling circuit 150 and the charge pump module 110 are reference clock signals, and the output of the frequency locking module 120 is used as the clock output of the fractional-n pll 100 based on phase interpolation and sampling.
Here, the charge pump module 110 performs charge and discharge according to the input reference clock signal, controls the frequency locking module 120 to perform frequency locking, and after the frequency locking, the frequency locking module 120 outputs clock waveform signals of a plurality of phases to the phase interpolation module 130.
Specifically, the reference clock signal is input to the phase frequency detector 111, and the phase frequency detector 111 generates an UP switch control signal UP and a down switch control signal DN of the charge pump 112 according to the input reference clock signal; the charge pump 112 charges and discharges according to the UP switch control signal UP and the down switch control signal DN.
Here, the clock signal output by the phase interpolation module 130 is also input to the phase frequency detector 111, the phase frequency detector 111 uses the reference clock signal as a reference signal, the clock signal output by the phase interpolation module 130 is used as a signal to be locked, and further, the frequency and phase difference between the reference clock signal and the clock signal output by the phase interpolation module 130 are compared, and are output in a voltage manner.
Wherein, when the phase of the signal to be locked is lagged, the phase frequency detector 111 outputs an UP switch control signal UP to drive the charge pump 112 to output a positive voltage pulse; when the phase of the signal to be locked advances, the phase frequency detector 111 outputs the lower switch control signal DN, and drives the charge pump 112 to output a negative voltage pulse.
Note that, the phase of the clock waveform signal output by the frequency locking module 120 may be set according to actual needs, which is not particularly limited herein.
Further, the low-pass filter 121 receives the charge-discharge signal of the charge pump 112 in the charge pump module 110, and converts the charge-discharge signal into the control voltage of the ring oscillator 122; the ring oscillator 122 starts oscillating after receiving the control voltage output from the low-pass filter 121 to achieve frequency locking.
Further, the phase interpolation module 130 interpolates the phase of the clock waveform signal according to the decimal signal output by the decimal sigma-delta modulator 140, and selects a target clock waveform signal from the clock waveform signals to send to the sampling circuit 150.
Here, the phase interpolation module 130 interpolates the phase using the fractional signal generated by the fractional sigma-delta modulator 140 to refine the phase of the waveform signal, and selects a clock waveform signal of a certain phase from among the clock waveform signals of a plurality of phases output from the frequency locking module 120 as a target clock waveform signal to output to the sampling circuit 150.
It should be noted that, the selection of the target clock waveform signal may be set according to actual needs, and is not particularly limited herein.
Further, the sampling circuit 150, after receiving the target clock waveform signal output by the phase interpolation module 130, samples the rising edge of the target clock waveform signal, determines a sampling voltage, and outputs the sampling voltage to the transconductance amplifier 160, and the transconductance amplifier 160 converts the sampling voltage into the control current of the frequency locking module 120 to control the frequency of the ring oscillator 122 in the frequency locking module 120.
The transconductance amplifier 160 compares the sampled voltage with a preset reference voltage, and converts the sampled voltage into a control current. The preset reference voltage may be set according to actual needs, and is not particularly limited herein.
As one possible implementation, referring to fig. 2, a schematic diagram of a fractional sigma-delta modulator 140 is provided as an example of the present disclosure.
As shown in fig. 2, the fractional sigma-delta modulator 140 includes a sigma-delta modulation unit 141 and an accumulator 142.
In an embodiment, the input to the fractional sigma-delta modulator 140 is a control word signal, wherein the control word signal is comprised of an integer portion and a fractional portion. After adding a preset deviation signal to the fractional control word signal, the fractional control word signal passes through the accumulator 142 and outputs a fractional control signal for controlling the phase interpolation module 130 to perform phase interpolation, wherein the deviation signal is used for controlling the fractional interval range of the control word signal.
As another possible implementation, referring to fig. 3, a schematic structural diagram of a phase interpolation module 130 is provided in an embodiment of the disclosure.
As shown in fig. 3, the phase interpolation module 130 includes: a timing controller 131, a decoder 132, a current digital-to-analog converter 133, and an interpolation capacitor 134.
In particular implementations, the decoder 132 converts the fractional control signal output by the fractional sigma-delta modulator 140 into a control signal for the current digital-to-analog converter 133, where the control signal is used to control the magnitude of the output current of the current digital-to-analog converter 133.
Further, the output current of the current dac 133 charges the interpolation capacitor 134, and affects the voltage change speed of the interpolation capacitor 134 according to the output current, so as to implement phase interpolation.
Here, since the current of the current digital-to-analog converter 133 is different in magnitude, the voltage of the interpolation capacitor 134 is different in speed, and thus the interpolation of the phase is realized.
After receiving the clock waveform signal output by the ring oscillator 122 in the frequency locking module 120, the timing controller 131 resets the voltage value of the interpolation capacitor 134 according to the clock waveform signal, and after the reset is stopped, the interpolation capacitor 134 starts to charge.
The integer control signal output from the fractional sigma-delta modulator 140 is input to the timing controller 131. The timing controller 131 also outputs a clock signal that is transmitted to the phase frequency detector 111 for use as a signal to be locked.
As another possible implementation, referring to fig. 4, a schematic structural diagram of a sampling circuit 150 according to an embodiment of the disclosure is provided.
As shown in fig. 4, the sampling circuit 150 includes a first delay unit 151, a second delay unit 152, a first inverter 153, a second inverter 154, a first transmission gate 155, a second transmission gate 156, and a sampling capacitor 157.
Specifically, the first delay unit 151 is connected to the first inverter 153; the second delay unit 152 is connected to the second inverter 154; an input terminal of the second delay unit 152 is connected between the first delay unit 151 and the first inverter 153; one end of the first transmission gate 155 is connected to the phase interpolation module 130, and the other end is connected to the second transmission gate 156; the second transmission gate 156 is connected to the transconductance amplifier 160; one end of the sampling capacitor 157 is connected between the first transmission gate 155 and the second transmission gate 156, and the other end of the sampling capacitor 157 is grounded; the control end of the first transmission gate 155 is connected to the first delay unit 151, and the inverse control end of the first transmission gate 155 is connected to the first inverter 153; the control terminal of the second transmission gate 156 is connected to the second delay unit 152, and the inverse control terminal of the second transmission gate 156 is connected to the second inverter 154.
In a specific implementation, the reference clock signal is input to the first delay unit 151, the sampling clock signal is output by the first delay unit 151, and then the holding clock signal is output after the processing of the second delay unit 152; the first transmission gate 155 samples the target clock waveform signal input from the phase interpolation module 130 according to the sampling clock signal output from the first delay unit 151, and holds the sampled voltage in the sampling capacitor 157; after the sampling is completed, the hold clock signal is released, and the sampled voltage on the sampling capacitor 157 is output to the transconductance amplifier 160.
Here, the sampling clock signal generates an inverted sampling clock signal after passing through the first inverter 153; the hold clock signal is passed through a second inverter 154 to generate an inverted hold clock signal.
Wherein the sampling clock signal is transmitted to the control end of the first transmission gate 155, and the inverted sampling clock signal is transmitted to the inverted control end of the first transmission gate 155; the hold clock signal is transmitted to the control terminal of the second transmission gate 156 and the inverted hold clock signal is transmitted to the inverted control terminal of the second transmission gate 156.
The embodiment of the disclosure provides a fractional frequency phase-locked loop based on phase interpolation and sampling, which comprises: the input of the sampling circuit and the charge pump module is a reference clock signal, and the output end of the frequency locking module is used as the clock output of the phase-locked loop; the charge pump module performs charge and discharge according to the reference clock signal, controls the frequency locking module to perform frequency locking, and outputs clock waveform signals of a plurality of phases to the phase interpolation module through the frequency locking module; the phase interpolation module interpolates the phase of the clock waveform signal according to the decimal signal output by the decimal sigma-delta modulator, and selects a target clock waveform signal from the clock waveform signals to send to the sampling circuit; the sampling circuit samples the rising edge of the target clock waveform signal, determines a sampling voltage, outputs the sampling voltage to the transconductance amplifier, and converts the sampling voltage into a control current of the frequency locking module by the transconductance amplifier so as to control the frequency of the frequency locking module. The low-frequency phase noise of the phase-locked loop can be effectively reduced, and the sigma delta noise is suppressed, so that the overall noise of the phase-locked loop is reduced, and the phase-locked loop has a smaller area.
Further, describing in detail a control method of a fractional-n pll based on phase interpolation and sampling disclosed in an embodiment of the present disclosure, an execution subject of the control method of a fractional-n pll based on phase interpolation and sampling provided in an embodiment of the present disclosure is generally a computer device having a certain computing power, where the computer device includes, for example: the terminal device, or server or other processing device, may be a User Equipment (UE), mobile device, user terminal, cellular telephone, cordless telephone, personal digital assistant (Personal Digital Assistant, PDA), handheld device, computing device, vehicle mounted device, wearable device, etc. In some possible implementations, the control method of the fractional-n pll based on phase interpolation and sampling may be implemented by a processor calling computer readable instructions stored in a memory.
Referring to fig. 5, a flowchart of a control method of a fractional-n pll based on phase interpolation and sampling according to an embodiment of the present disclosure is provided, where the method is applied to the fractional-n pll based on phase interpolation and sampling in any one of fig. 1 to 4, and the method includes steps S501 to S504, where:
s501, respectively inputting reference clock signals to the sampling circuit and the charge pump module, and controlling the output end of the frequency locking module to perform clock output.
S502, controlling the charge pump module to charge and discharge according to the reference clock signal, controlling the frequency locking module to lock the frequency, and outputting clock waveform signals of a plurality of phases to the phase interpolation module by the frequency locking module.
S503, controlling the phase interpolation module to interpolate the phase of the clock waveform signal according to the decimal signal output by the decimal sigma-delta modulator, and selecting a target clock waveform signal from the clock waveform signals to send to the sampling circuit.
S504, controlling the sampling circuit to sample the rising edge of the target clock waveform signal, determining a sampling voltage, outputting the sampling voltage to the transconductance amplifier, and converting the sampling voltage into a control current of the frequency locking module by the transconductance amplifier so as to control the frequency of the frequency locking module.
According to the control method of the fractional frequency division phase-locked loop based on phase interpolation and sampling, reference clock signals are respectively input to a sampling circuit and a charge pump module, and the output end of a frequency locking module is controlled to output a clock. The charge pump module is controlled to charge and discharge according to the reference clock signal, the frequency locking module is controlled to lock the frequency, and the frequency locking module outputs clock waveform signals of a plurality of phases to the phase interpolation module. And controlling a phase interpolation module to interpolate the phase of the clock waveform signal according to the decimal signal output by the decimal sigma-delta modulator, and selecting a target clock waveform signal from the clock waveform signal to send to a sampling circuit. The control sampling circuit samples the rising edge of the target clock waveform signal, determines sampling voltage, outputs the sampling voltage to the transconductance amplifier, and converts the sampling voltage into control current of the frequency locking module by the transconductance amplifier so as to control the frequency of the frequency locking module. The low-frequency phase noise of the phase-locked loop can be effectively reduced, and the sigma delta noise is suppressed, so that the overall noise of the phase-locked loop is reduced, and the phase-locked loop has a smaller area.
It will be appreciated by those skilled in the art that in the above-described method of the specific embodiments, the written order of steps is not meant to imply a strict order of execution but rather should be construed according to the function and possibly inherent logic of the steps.
The process flow of each module in the method and the interaction flow between each module may be described with reference to the related description in the above system embodiment, which is not described in detail herein.
Corresponding to the control method of the fractional-n pll based on phase interpolation and sampling in fig. 5, the embodiment of the disclosure further provides an electronic device 600, as shown in fig. 6, which is a schematic structural diagram of the electronic device 600 provided by the embodiment of the disclosure, including:
a processor 61, a memory 62, and a bus 63; memory 62 is used to store execution instructions, including memory 621 and external memory 622; the memory 621 is also referred to as an internal memory, and is used for temporarily storing operation data in the processor 61 and data exchanged with the external memory 622 such as a hard disk, the processor 61 exchanges data with the external memory 622 through the memory 621, and when the electronic device 600 is operated, the processor 61 and the memory 62 communicate through the bus 63, so that the processor 61 performs the steps of the control method of the fractional pll based on phase interpolation and sampling in fig. 5.
The disclosed embodiments also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the control method of the fractional-n pll based on phase interpolation and sampling described in the above method embodiments. Wherein the storage medium may be a volatile or nonvolatile computer readable storage medium.
The embodiments of the present disclosure further provide a computer program product, where the computer program product includes computer instructions, where the computer instructions, when executed by a processor, may perform the steps of the method for controlling a fractional-n pll based on phase interpolation and sampling described in the foregoing method embodiments, and specifically, reference may be made to the foregoing method embodiments, which are not described herein.
Wherein the above-mentioned computer program product may be realized in particular by means of hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied as a computer storage medium, and in another alternative embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), or the like.
It will be clear to those skilled in the art that, for convenience and brevity of description, reference may be made to the corresponding process in the foregoing method embodiment for the specific working process of the above-described system, which is not described herein again. In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems and methods may be implemented in other ways. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on such understanding, the technical solution of the present disclosure may be embodied in essence or a part contributing to the prior art or a part of the technical solution, or in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present disclosure. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Finally, it should be noted that: the foregoing examples are merely specific embodiments of the present disclosure, and are not intended to limit the scope of the disclosure, but the present disclosure is not limited thereto, and those skilled in the art will appreciate that while the foregoing examples are described in detail, it is not limited to the disclosure: any person skilled in the art, within the technical scope of the disclosure of the present disclosure, may modify or easily conceive changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features thereof; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the disclosure, and are intended to be included within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (10)
1. A fractional-n phase-locked loop based on phase interpolation and sampling, comprising: the device comprises a charge pump module, a frequency locking module, a phase interpolation module, a decimal sigma-delta modulator, a sampling circuit and a transconductance amplifier;
the sampling circuit, the transconductance amplifier, the frequency locking module and the phase interpolation module are sequentially connected; the charge pump module is connected in parallel between the input end of the sampling circuit and the output end of the transconductance amplifier; the decimal sigma-delta modulator is connected with the phase interpolation module;
the input of the sampling circuit and the charge pump module is a reference clock signal, and the output end of the frequency locking module is used as the clock output of the phase-locked loop;
the charge pump module performs charge and discharge according to the reference clock signal, controls the frequency locking module to perform frequency locking, and outputs clock waveform signals of a plurality of phases to the phase interpolation module by the frequency locking module;
the phase interpolation module interpolates the phase of the clock waveform signal according to the decimal signal output by the decimal sigma-delta modulator, and selects a target clock waveform signal from the clock waveform signals to send to the sampling circuit;
the sampling circuit samples the rising edge of the target clock waveform signal, determines sampling voltage, outputs the sampling voltage to the transconductance amplifier, and converts the sampling voltage into control current of the frequency locking module by the transconductance amplifier so as to control the frequency of the frequency locking module.
2. The fractional-n phase-locked loop of claim 1, wherein the charge pump module comprises a phase frequency detector and a charge pump;
the phase frequency detector generates an upper switch control signal and a lower switch control signal according to the input reference clock signal;
and the charge pump charges and discharges according to the upper switch control signal and the lower switch control signal.
3. The fractional-n phase-locked loop of claim 1, wherein the frequency-locking module comprises: low pass filter and ring oscillator, wherein:
the low-pass filter receives a charge-discharge signal of the charge pump module and converts the charge-discharge signal into a control voltage of the ring oscillator;
the ring oscillator starts to oscillate after receiving the control voltage to achieve frequency locking.
4. The fractional-n phase-locked loop of claim 1, wherein the fractional-sigma-delta modulator comprises a sigma-delta modulation unit and an accumulator;
the input of the decimal sigma-delta modulator is a control word signal, wherein the control word signal consists of an integer part and a decimal part;
and after adding a preset deviation signal to the control word signal of the decimal part, outputting a decimal control signal for controlling the phase interpolation module to perform phase interpolation through the accumulator, wherein the deviation signal is used for controlling the decimal part interval range of the control word signal.
5. The fractional-n phase-locked loop of claim 4, wherein the phase interpolation module comprises: the time sequence controller, the decoder, the current digital-to-analog converter and the interpolation capacitor;
the decoder converts the small-scale control signal into a control signal of the current digital-to-analog converter, wherein the control signal is used for controlling the output current of the current digital-to-analog converter;
the current output by the current digital-to-analog converter charges the interpolation capacitor, and the voltage change speed of the interpolation capacitor is influenced according to the output current, so that phase interpolation is realized;
after receiving the clock waveform signal output by the frequency locking module, resetting the voltage value of the interpolation capacitor by the time sequence controller according to the clock waveform signal, and after the resetting is stopped, starting charging the interpolation capacitor.
6. The fractional-n pll of claim 1, wherein the sampling circuit comprises a first delay cell, a second delay cell, a first inverter, a second inverter, a first transmission gate, a second transmission gate, and a sampling capacitor;
the first delay unit is connected with the first inverter; the second delay unit is connected with the second inverter; the input end of the second delay unit is connected between the first delay unit and the first inverter;
one end of the first transmission gate is connected with the phase interpolation module, and the other end of the first transmission gate is connected with the second transmission gate; the second transmission gate is connected with the transconductance amplifier;
one end of the sampling capacitor is connected between the first transmission gate and the second transmission gate, and the other end of the sampling capacitor is grounded;
the control end of the first transmission gate is connected with the first delay unit, and the inverse control end of the first transmission gate is connected with the first inverter;
the control end of the second transmission gate is connected with the second delay unit, and the inverse control end of the second transmission gate is connected with the second inverter.
7. The fractional-n phase-locked loop of claim 6, wherein:
the reference clock signal is input to the first delay unit, the first delay unit outputs a sampling clock signal, and the second delay unit outputs a holding clock signal after processing;
the first transmission gate samples the target clock waveform signal according to the sampling clock signal, and the sampled voltage obtained by sampling is kept in the sampling capacitor;
and after the sampling is finished, the holding clock signal is released, and the sampling voltage on the sampling capacitor is output to the transconductance amplifier.
8. A control method of a fractional-n pll based on phase interpolation and sampling, applied to the fractional-n pll based on phase interpolation and sampling as claimed in any of claims 1 to 7, the fractional-n pll comprising: the charge pump module, the frequency lock module, the phase interpolation module, the fractional sigma-delta modulator, the sampling circuit, and the transconductance amplifier, the method comprising:
respectively inputting reference clock signals to the sampling circuit and the charge pump module, and controlling the output end of the frequency locking module to perform clock output;
controlling the charge pump module to charge and discharge according to the reference clock signal, controlling the frequency locking module to lock the frequency, and outputting clock waveform signals of a plurality of phases to the phase interpolation module by the frequency locking module;
controlling the phase interpolation module to interpolate the phase of the clock waveform signal according to the decimal signal output by the decimal sigma-delta modulator, and selecting a target clock waveform signal from the clock waveform signal to send to the sampling circuit;
and controlling the sampling circuit to sample the rising edge of the target clock waveform signal, determining a sampling voltage, outputting the sampling voltage to the transconductance amplifier, and converting the sampling voltage into the control current of the frequency locking module by the transconductance amplifier so as to control the frequency of the frequency locking module.
9. An electronic device, comprising: a processor, a memory and a bus, said memory storing machine readable instructions executable by said processor, said processor and said memory communicating over the bus when the electronic device is running, said machine readable instructions when executed by said processor performing the steps of the method of controlling a fractional-n phase locked loop based on phase interpolation and sampling as claimed in claim 8.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, performs the steps of the method of controlling a fractional-n phase-locked loop based on phase interpolation and sampling as claimed in claim 8.
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| CN202310463666.XA CN117833912A (en) | 2023-04-26 | 2023-04-26 | Fractional frequency division phase-locked loop based on phase interpolation and sampling |
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