CN117725881A - Method and device for generating register test case and test equipment - Google Patents
Method and device for generating register test case and test equipment Download PDFInfo
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Abstract
The application relates to the technical field of integrated circuits, and discloses a method for generating a register test case, which comprises the following steps: reading a register description table and a register description table of a circuit module in an integrated circuit design specification; generating an initial list file of the register under the development framework of the verification platform according to the total description table of the register of the circuit module; updating the initial list file of the register according to the register description table of the circuit module to obtain a test list file of the register; and performing read-write test on the register according to the register test information stored in the register test list file, and generating a test case. The method can automatically generate the register test case and improve the reliability of register verification. The application also discloses a device for generating the register test case and test equipment.
Description
Technical Field
The present invention relates to the technical field of integrated circuits, and for example, to a method and apparatus for generating a register test case, and a test device.
Background
At present, in a chip, a register mainly bears the functions of information storage, processing and transmission, is controlled and accessed by software and hardware at the same time, is a bridge for the interaction of the software and the hardware in the running process of the chip, and has a significant position. Thus in chip RTL (Register Transfer Level ) emulation, register checking is a very necessary and important test. The verification engineer needs to perform a series of simulation tests such as reset value check, read-write, authority, reset source test and the like on registers in all modules in the project, so that the correct function of the chip registers is ensured.
In order to detect the function of the chip register, the related art adopts the following test method: and manually writing test cases, manually adding addresses of registers of each circuit module in a verification platform development framework environment and a C environment according to the integrated circuit design specification, and then adding a test case according to reset values of the registers, bit fields, mode authorities, reset sources and other information. And then debugging based on the test case, and adding the register information to the development framework environment and the C environment of the verification platform after the debugging is passed.
In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:
The test method adopted by the related art has higher requirements on the verifier, however, the verification personnel are not at the same level, so that the verification effect of the register is good and uneven, namely, the defect that the verification of the register is unreliable exists in a manual test mode.
It should be noted that the information disclosed in the foregoing background section is only for enhancing understanding of the background of the present application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.
The embodiment of the disclosure provides a method, a device and test equipment for generating a register test case, so as to improve the reliability of register verification.
In some embodiments, the method comprises: reading a register description table and a register description table of a circuit module in an integrated circuit design specification; generating an initial list file of the register under the development framework of the verification platform according to the total description table of the register of the circuit module; updating the initial list file of the register according to the register description table of the circuit module to obtain a test list file of the register; and performing read-write test on the register according to the register test information stored in the register test list file, and generating a test case.
In some embodiments, generating an initial list file of registers under a verification platform development framework from a summary table of register specifications for circuit modules includes: determining module information of a circuit module; the module information comprises a module name, a module base address and a register offset address of the circuit module; traversing the register description summary table, and extracting the register description information in the register description summary table into a register list file according to the module information to obtain a register initial list file.
In some embodiments, updating the initial list file of registers according to the register description table of the circuit module to obtain the test list file of registers includes: determining register description information in a register description table; the register description information comprises a register name and one or more of a bit field, a mask, read-write permission and a reset value; and under the condition that the register names in the register initial list file are matched with the register names in the register description table, extracting the register description information corresponding to the register names into the register list file to obtain a register test list file.
In some embodiments, further comprising: and before extracting the register description information corresponding to the register name to the register list file, carrying out compliance verification on the register description information.
In some embodiments, compliance verification of register description information includes: obtaining a bit field in the register description information; determining register description information compliance under the condition that the bit field width accords with the bit field condition; or, obtaining the read-write permission in the register description information; determining register description information compliance under the condition that the read-write authority accords with the authority condition; or obtaining the bit field in the register description information and the read-write permission in the register description information, and determining the register description information compliance under the condition that the bit field width accords with the bit field condition and the read-write permission accords with the permission condition.
In some embodiments, performing a read-write test on a register according to register test information stored in a register test list file includes: calculating a read mask value and a write mask value of the register test information; determining a read-write value of the register test information according to the read mask value and the write mask value; and comparing the read-write value with the expected value to determine a read-write test result.
In some embodiments, generating test cases includes: after the read-write test, extracting the mode authority in the register test list file; and generating a test case corresponding to the mode authority according to the mode authority.
In some embodiments, generating test cases includes: obtaining a test sample; and importing the register test information to the corresponding position of the test sample to generate the test sample.
In some embodiments, the apparatus includes a processor and a memory storing program instructions, the processor configured to perform a method for generating a register test case as described above when the program instructions are executed.
In some embodiments, a test apparatus includes: an equipment body; the device for generating a register test case described above is mounted on the apparatus main body.
The method, the device and the test equipment for generating the register test case provided by the embodiment of the disclosure can realize the following technical effects:
according to the embodiment of the disclosure, the initial list file of the register under the development framework of the verification platform can be generated according to the circuit module register description table stored in the integrated circuit design specification, the initial list file of the register is updated according to the circuit module register description table to obtain the register test list file, and the accuracy of extracting the register test information in the register test list file is ensured, so that the accuracy of test cases generated by read-write tests is improved, and the reliability of register verification is improved while the automatic generation of the register test cases is realized.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:
FIG. 1 is a schematic diagram of a method for generating register test cases provided by embodiments of the present disclosure;
FIG. 2 is a schematic diagram of another method for generating register test cases provided by embodiments of the present disclosure;
FIG. 3 is a schematic diagram of another method for generating register test cases provided by embodiments of the present disclosure;
FIG. 4 is a schematic diagram of another method for generating register test cases provided by embodiments of the present disclosure;
FIG. 5 is a schematic diagram of another method for generating register test cases provided by embodiments of the present disclosure;
FIG. 6 is a schematic illustration of one application of an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of an apparatus for generating register test cases provided by embodiments of the present disclosure.
Detailed Description
So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.
The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
The term "plurality" means two or more, unless otherwise indicated.
In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.
The term "corresponding" may refer to an association or binding relationship, and the correspondence between a and B refers to an association or binding relationship between a and B.
In the disclosed embodiment, the integrated circuit design specification includes a total table of register descriptions and a table of register descriptions of a plurality of circuit modules, and other tables not associated with registers.
The summary table of register descriptions represents summary information of all registers in the circuit module, including module name, module base address and register name, register function, register offset address, mode authority and reset source of the circuit module.
The register description table represents a specific functional description of each register in the circuit module. The register description table comprises bit fields, bit domain names, read-write permission, bit domain function descriptions and the like. Wherein the bit fields in the register description table are configured to perform a width check on the register according to the bit field width.
Table 1 register description of circuit block ABCCBA summary table example
Table 2 example of register description table for register a1_sfr in circuit block ABCCBA
It should be noted that, in the register description table of the register a1_sfr in the circuit module ABCCBA in table 2, the table column attributes of the register description table of the register a2_sfr and the register description table of the register b_sfr in the circuit module ABCCBA are the same as the column attributes of table 2.
Based on the above integrated circuit design specification, referring to fig. 1, an embodiment of the disclosure provides a method for generating a register test case, including:
s01, the test equipment reads a register description table and a register description table of the circuit modules in the integrated circuit design specification.
In this step, the test apparatus reads a register specification summary table and a register description table of the circuit modules in the integrated circuit design specification, including: the test equipment selects a register description table and a register description table of the circuit module in the integrated circuit design specification, and reads the table information of the register description table and the register description table of the circuit module.
And S02, the test equipment generates a register initial list file under the development framework of the verification platform according to the register description summary table of the circuit module.
In this step, the development framework of the verification platform may be a UVM (Universal VerificationMethodology) test environment framework or a C language test framework.
S03, the testing equipment updates the initial list file of the register according to the register description table of the circuit module so as to obtain the test list file of the register.
S04, according to the register test information stored in the register test list file, performing read-write test on the register and generating a test case.
By adopting the method for generating the register test case provided by the embodiment of the disclosure, the embodiment of the disclosure can generate the register initial list file under the development framework of the verification platform according to the circuit module register description table stored in the integrated circuit design specification, and update the register initial list file according to the circuit module register description table to obtain the register test list file, thereby ensuring the accuracy of extracting the register test information in the register test list file, improving the accuracy of the test case generated by the read-write test, and being beneficial to improving the reliability of register verification while realizing the automatic generation of the register test case.
Optionally, as shown in connection with fig. 2, the test device generates an initial list file of registers under the development framework of the verification platform according to a total table of register descriptions of the circuit modules, including:
S11, the testing equipment determines module information of the circuit module. The module information comprises a module name, a module base address and a register offset address of the circuit module.
S12, the test equipment traverses the register description table, extracts the register description information in the register description table into the register list file according to the module information, and obtains the register initial list file. The register specification information comprises a module name, a module base address, a register name, a register offset address, a mode authority and a reset source of a circuit module.
In this way, the embodiment of the disclosure determines the module information of the circuit module according to the register description summary table of the circuit module, traverses the register description summary table, extracts the register description information in the register description summary table to the register list file according to the module information, and obtains the register initial list file. Therefore, the test equipment can accurately extract the register description information by traversing the register description summary table, so that a register initial list file with accurate register description information is obtained, the accuracy of extracting the register test information in the register test list file is ensured, and the accuracy of test cases generated by read-write tests is improved.
Optionally, as shown in connection with fig. 3, the test apparatus updates the register initial list file according to the register description table of the circuit module to obtain a register test list file, including:
s21, the test equipment determines the register description information in the register description table. The register description information comprises a register name and one or more of a bit field, a mask, read-write permission and a reset value.
S22, under the condition that the register names in the initial list file of the register are matched with the register names in the register description table, the test equipment extracts the register description information corresponding to the register names to the register list file so as to obtain the test list file of the register.
In this way, the embodiment of the disclosure matches the register name in the register initial list file with the register in the register description table after determining the register description information in the register description table according to the register description table of the circuit module. If the matching operation of the register names in the register initial list file and the register names in the register description table is not executed, the register names in the register initial list file and the register names in the register description table cannot be guaranteed to be matched, and the register read-write test fails after the register names are not matched. Therefore, in the embodiment of the disclosure, the register names in the initial register list file are matched with the registers in the register description table, and when the register names are matched, the register description information corresponding to the register names is extracted to the register list file, so as to obtain the register test list file. Therefore, the accuracy of the test cases generated by the read-write test is improved, and the reliability of register verification is improved.
Optionally, the test apparatus determines that the register names in the register initial list file match the register names in the register description table in the following manner:
under the condition that the register names in the register description table are formed by capital letters and/or numbers, the test equipment compares the register names in the register list file with the register names in the register description table, and determines that the register names in the register initial list file are matched with the register names in the register description table when the comparison results are the same; or,
and the test equipment matches the register names in the register list file with the register names in the register description table by utilizing a regular matching rule under the condition that the register names in the register description table comprise lower case letters x and/or lower case letters n, and determines that the register names in the register initial list file are matched with the register names in the register description table when the matching is successful.
In this way, if the matching operation of the register names in the register initial list file and the register names in the register description table is not executed, the register read-write test fails after the mismatch, and the test case cannot be generated. Therefore, in the embodiment of the disclosure, when the register names in the register description table are composed of upper case characters and/or numbers, register name matching is performed based on a regular matching rule when the register names in the register description table comprise lower case letters x and/or lower case letters n, so that the test equipment successfully realizes the register read-write test, thereby generating a test case, and further improving the reliability of register verification.
Optionally, as shown in connection with fig. 4, the test apparatus updates the register initial list file according to the register description table of the circuit module to obtain a register test list file, including:
s31, the test equipment determines the register description information in the register description table. The register description information comprises a register name and one or more of a bit field, a mask, read-write permission and a reset value. As one example, the mask includes a read mask value ReadMask and a write mask value WriteMask.
In this step, the test apparatus determines the register description information in the register description table, including: the test equipment converts the register list file into a csv (common-Separated Values) file for storage; the test equipment determines the register description information in the csv file. Because the csv format file stores information in a plain text form, the test equipment can conveniently extract the register description information from the csv file.
S32, the testing equipment performs compliance verification on the register description information.
S33, under the condition that the register names in the initial list file of the register are matched with the register names in the register description table, the test equipment extracts the register description information corresponding to the register names to the register list file so as to obtain the test list file of the register.
In this way, after the register description information in the register description table is determined, compliance verification is performed on the register description information to ensure compliance of the register description information, so that the test equipment successfully realizes the register read-write test. And extracting the register description information corresponding to the register name to the register list file when the register name in the register initial list file is matched with the register name in the register description table so as to obtain the register test list file. Therefore, the reliability of the compliance verification of the register description information can be ensured, and the accuracy of the extraction of the register test information in the register test list file can be ensured, so that the accuracy of the test case generated by the read-write test is further improved.
It should be noted that, the compliance verification of the register description information by the test device may be performed simultaneously with determining whether the register names in the register initial list file and the register names in the register description table match, or may be performed after determining whether the register names in the register initial list file and the register names in the register description table match and before extracting the register description information corresponding to the register names into the register list file. Embodiments of the present disclosure may not be particularly limited thereto.
Optionally, the testing device performs compliance verification on the register description information, including:
the test equipment obtains the bit fields in the register description information. And the test equipment determines the register description information compliance under the condition that the bit field width accords with the bit field condition.
In this way, after the bit field in the register description information is obtained, the embodiment of the disclosure determines whether the bit field width meets the bit field condition, and determines that the register description information is compliant when determining that the bit field width meets the bit field condition. The test equipment successfully realizes the register read-write test, thereby generating test cases, and being beneficial to ensuring the reliability of the compliance verification of the register description information.
Optionally, the bit-domain width meets a bit-domain condition, comprising:
the highest bit of the bit field is 31 and the lowest bit of the bit field is 0; and, a step of, in the first embodiment,
the different bit fields in the register description information are consecutive.
In one specific example, in conjunction with the table 2, in the bit field in the register description table of register a1_sfr in circuit module ABCCBA, the bit field most significant bit is 31 and the bit field least significant bit is 0, while [31:24] is consecutive to [23:16], and [23:16] is consecutive to [15:8], and [15:8] is consecutive to [7:0 ]. Thus, the register description information compliance in the register description table of the register a1—sfr in table 2 is determined.
Optionally, the testing device performs compliance verification on the register description information, including:
the test equipment obtains the read-write permission in the register description information. And under the condition that the read-write authority accords with the authority condition, the test equipment determines that the register description information is compliant.
In this way, after obtaining the read-write permission in the register description information, the embodiment of the disclosure judges whether the read-write permission meets the permission condition, and determines that the register description information is compliant when determining that the read-write permission meets the permission condition. The test equipment successfully realizes the register read-write test, thereby generating test cases, and being beneficial to ensuring the reliability of the compliance verification of the register description information.
Optionally, the read-write permission meets permission conditions, including:
writing all read-write authorities in a register description table into a preset array; traversing the read-write rights stored in the preset array and sequentially judging whether each read-write right accords with respective preset right conditions; when each read-write authority accords with the respective preset authority condition, determining that the read-write authority accords with the authority condition. As an example, all read-write permissions (RO, WO, RW, RO) in the register description table of register a1_sfr in table 2 are traversed into a preset array; traversing the read-write permission in the storage preset array, and judging whether the four read-write permissions meet respective preset permission conditions or not according to the read-write permissions; the first read-write authority RO accords with the read-only preset authority condition, the second read-write authority WO accords with the read-only preset authority condition, the third read-write authority RW accords with the read-write preset authority condition and the fourth read-write authority RO accords with the read-only preset authority condition. Therefore, if each read-write authority is determined to respectively accord with the respective preset authority conditions, the read-write authority is determined to accord with the authority conditions.
Optionally, the testing device performs compliance verification on the register description information, including:
obtaining a bit field in the register description information and a read-write permission in the register description information, and determining the register description information compliance under the condition that the bit field width accords with the bit field condition and the read-write permission accords with the permission condition.
In this way, after the bit field and the read-write permission in the register description information are obtained, the embodiment of the disclosure judges whether the bit field width accords with the bit field condition and the read-write permission accords with the permission condition, and determines that the register description information is compliant when the bit field width accords with the bit field condition and the read-write permission accords with the permission condition. The test equipment successfully realizes the register read-write test, thereby generating test cases, and being beneficial to comprehensively ensuring the reliability of the compliance verification of the description information of the register.
Optionally, referring to fig. 5, the test device performs a read-write test on the register according to the register test information stored in the register test list file, including:
s41, the test equipment calculates a read mask value and a write mask value of the register test information.
In this step, the test apparatus calculates a read mask value and a write mask value of the register test information, including: the test device calculates a read mask value and a write mask value of the register test information according to the read-write permission. As one example, bit fields include [31:16] and [15:8], [7:0]. Wherein, the read-write authority of [31:16] is read-write, the read-write authority of [15:8] is read-only, and the read-write authority of [7:0] is write-only. The initial value of the register is 00000000; and the test equipment writes a preset writing value of 0xFFFFFFFF into the register according to the read-write permission. Because the read-write permission of [15:8] is read-only, the bits FF corresponding to the bit field [15:8] in the preset write value cannot be written into the register, and other bits in the preset write value can be normally written, so that the write mask value of 0xFFFF00FF is calculated. Meanwhile, the test equipment performs a read operation on the register. Because the read-write permission of [7:0] is write-only, the bit FF corresponding to bit [7:0] in the 0xFFFFFFFF stored in the register cannot be read, and other bits of the 0xFFFFFFFF stored in the register can be read normally. Thus, the read mask value is calculated to be 0xFFFFFF00.
S42, the test equipment determines the read-write value of the register test information according to the read mask value and the write mask value.
In this step, the register test information includes a write value. The test equipment determines the read-write value of the register test information according to the read mask value and the write mask value, and comprises the following steps: the test equipment writes the writing value into the register; the test equipment performs a read operation of the register to obtain a read-write value of the write value.
S43, the test equipment compares the read-write value with the expected value to determine a read-write test result.
In this step, the test apparatus obtains the expected value in the following manner: the test equipment carries out bitwise AND operation on the register test information and the read mask value and obtains an operation result; the test device bitwise and operates the operation result and the write mask value and obtains an expected value.
In the step, the test equipment compares the read-write value with the expected value to determine a read-write test result, and the method comprises the following steps: when the read-write value is successfully compared with the expected value, the test equipment determines that the read-write test is successful; and when the comparison of the read-write value and the expected value fails, the test equipment determines that the read-write test fails.
In this way, the embodiment of the disclosure first calculates the read mask value and the write mask value of the register test information, then determines the read and write value of the register test information according to the read mask value and the write mask value, and finally compares the read and write value with the expected value to determine the read and write test result. And when the read-write test result shows that the comparison is successful, determining that the register function is correct and the read-write test is successful. And when the read-write test result shows that the comparison fails, the read-write test fails. Therefore, the embodiment of the disclosure can judge whether the test is successful or not by comparing the read-write value of the register test information determined based on the read mask value and the write mask value with the expected value, thereby being beneficial to improving the reliability and the accuracy of the register read-write test.
In one specific example, the bit fields include [31:16] and [15:8], [7:0]. Wherein, the read-write authority of [31:16] is read-write, the read-write authority of [15:8] is read-only, and the read-write authority of [7:0] is write-only.
First, the test apparatus calculates a read mask value 0xFFFF00 and a write mask value 0xFFFF00FF of the register test information. Then, the test apparatus performs a read operation of the register to obtain a read-write value of the above-described write value according to the write value 0xFFFFFFFF after writing the write value into the register. Secondly, the test equipment performs the following bitwise AND operation: the expected values are obtained for 0xFFFFFFFF &0xFFFFFF00& 0xFFFF00FF. Finally, the test equipment compares the read-write value with the expected value, and if the read-write value is the same as the expected value, the register function is correct and the read-write test is successful; if the read-write value is different from the expected value, the read-write test fails.
Optionally, the test device generates a test case, including:
and after the test equipment reads and writes the test, extracting the mode authority in the register test list file.
And the test equipment generates a test case corresponding to the mode authority according to the mode authority.
In this way, in order to facilitate a tester to check test cases under different mode authorities, the embodiment of the disclosure extracts the mode authorities in the register test list file after performing read-write test, and then generates the test cases corresponding to the mode authorities according to the mode authorities. Therefore, the classified storage of the test cases under the mode authority is realized, and the query and verification efficiency of the test cases is improved.
In a specific example, the test device generates a test case corresponding to the mode authority according to the mode authority, including: and the test equipment generates a first test case and a second test case which respectively correspond to different mode authorities according to the mode authorities. The first test case is stored in an sv file, and the second test case is stored in a c file.
Optionally, the test device generates a test case, including:
the test equipment obtains a test sample.
The test equipment imports the register test information to the corresponding position of the test sample, and generates the test sample.
In this way, the embodiment of the disclosure imports the register test information to the corresponding position of the test sample and generates the test sample, so that a tester can quickly acquire the register test information stored in the register list file by calling the test sample, and the tester can conveniently test and verify the register on the basis of improving the reliability and accuracy of the register read-write test.
Optionally, the test apparatus obtains a test sample, including: test sample example the array locations in the test sample example for storing the register test information are obtained. The test equipment imports the register test information to the corresponding position of the test sample, and generates the test sample, comprising: the test equipment imports the register test information into the array position of the test sample to generate the test sample.
In one specific example, the test samples are stored in the form of a demo file. In the test sample, a structure array for storing register test information is stored. After the test equipment obtains the test sample, the register test information stored in the register list file is imported into the structure array of the test sample.
It should be noted that, after the test device imports the register test information to the corresponding position of the test sample, the method further includes: the test equipment extracts the mode authority in the register test list; and the test equipment generates a test case corresponding to the mode authority under the corresponding position of the test case according to the mode authority. Therefore, the register test verification is conveniently carried out on the test cases with different mode authorities by a tester, and the query verification efficiency of the test cases is further improved.
In practical applications, as shown in table 1, table 2 and fig. 6, the method for generating a register test case specifically performs the following steps:
s51, the test equipment reads a register description table 1 and a register description table of the circuit modules in the integrated circuit design specification. Wherein the register description table includes respective register description tables of the registers a2_sfr and b_sfr. Wherein the respective register description tables of the register a2_sfr and the register b_sfr are not specifically shown.
S52, the testing equipment determines module information of the circuit module. The module information comprises a module name, a module base address and a register offset address of the circuit module.
S53, the test equipment traverses the register description table, extracts the register description information in the register description table into the register list file according to the module information, and obtains the register initial list file. The register specification information comprises a module name, a module base address, a register name, a register offset address, a mode authority and a reset source of a circuit module.
S54, the test equipment determines the register description information in the register description table. The register description information comprises a register name, a bit field, a read mask value, a write mask value, a read-write permission and a reset value.
And S55, the testing equipment performs compliance verification on the register description information.
S56, when the register names in the register initial list file are matched with the register names in the register description table, the test equipment extracts the register description information corresponding to the register names to the register list file so as to obtain the register test list file.
S57, the test equipment calculates a read mask value and a write mask value of the register test information stored in the register test list file according to the read-write permission, and determines the read-write value of the register test information according to the read mask value and the write mask value.
S58, the test equipment compares the read-write value with the expected value to determine a read-write test result.
S59, after the test equipment determines the read-write test result, a test sample is obtained, and the register test information is imported to the corresponding position of the test sample to generate the test sample.
As shown in connection with FIG. 7, an embodiment of the present disclosure provides an apparatus 200 for generating a register test case, including a processor 700 and a memory 701. Optionally, the apparatus 200 may further comprise a communication interface (Communication Interface) 702 and a bus 703. The processor 700, the communication interface 702, and the memory 701 may communicate with each other through the bus 703. The communication interface 702 may be used for information transfer. The processor 700 may call logic instructions in the memory 701 to perform the method for generating register test cases of the above-described embodiments.
Further, the logic instructions in the memory 701 may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product.
The memory 701 is used as a computer readable storage medium for storing a software program, a computer executable program, and program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 100 executes functional applications and data processing by running program instructions/modules stored in the memory 701, i.e., implements the method for generating register test cases in the above-described embodiments.
Memory 701 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for a function; the storage data area may store data created according to the use of the terminal device, etc. In addition, the memory 701 may include a high-speed random access memory, and may also include a nonvolatile memory.
The embodiment of the disclosure provides a test device, comprising: an equipment body, and the above-described apparatus 200 for generating a register test case. The apparatus 200 for generating a register test case is mounted to an equipment body. The mounting relationships described herein are not limited to being placed within the body of the device, but include mounting connections to other components of the test device, including but not limited to physical, electrical, or signal transmission connections, etc. Those skilled in the art will appreciate that the apparatus 200 for generating register test cases may be adapted to a viable device body, thereby implementing other viable embodiments.
Embodiments of the present disclosure provide a computer-readable storage medium storing computer-executable instructions configured to perform the above-described method for generating a register test case.
Embodiments of the present disclosure may be embodied in a software product stored on a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of a method according to embodiments of the present disclosure. While the aforementioned storage medium may be a non-transitory storage medium, such as: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk or an optical disk, or the like, which can store program codes.
The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. Moreover, the terminology used in the present application is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in this application, the terms "comprises," "comprising," and/or "includes," and variations thereof, mean that the stated features, integers, steps, operations, elements, and/or components are present, but that the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.
Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled artisan may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (10)
1. A method for generating a register test case, comprising:
reading a register description table and a register description table of a circuit module in an integrated circuit design specification;
generating an initial list file of the register under the development framework of the verification platform according to the total description table of the register of the circuit module;
updating the initial list file of the register according to the register description table of the circuit module to obtain a test list file of the register;
and performing read-write test on the register according to the register test information stored in the register test list file, and generating a test case.
2. The method of claim 1, wherein generating an initial list file of registers under a verification platform development framework from a summary table of register specifications for circuit modules comprises:
determining module information of a circuit module; the module information comprises a module name, a module base address and a register offset address of the circuit module;
traversing the register description summary table, and extracting the register description information in the register description summary table into a register list file according to the module information to obtain a register initial list file.
3. The method of claim 1, wherein updating the initial list file of registers based on the register description table of the circuit module to obtain the test list file of registers comprises:
Determining register description information in a register description table; the register description information comprises a register name and one or more of a bit field, a mask, read-write permission and a reset value;
and under the condition that the register names in the register initial list file are matched with the register names in the register description table, extracting the register description information corresponding to the register names into the register list file to obtain a register test list file.
4. A method according to claim 3, further comprising:
and before extracting the register description information corresponding to the register name to the register list file, carrying out compliance verification on the register description information.
5. The method of claim 4, wherein compliance verifying the register descriptive information comprises:
obtaining a bit field in the register description information; determining register description information compliance under the condition that the bit field width accords with the bit field condition; or,
obtaining read-write permission in the register description information; determining register description information compliance under the condition that the read-write authority accords with the authority condition; or,
obtaining a bit field in the register description information and a read-write permission in the register description information, and determining the register description information compliance under the condition that the bit field width accords with the bit field condition and the read-write permission accords with the permission condition.
6. The method of claim 1, wherein performing read-write testing of the registers based on the register test information stored in the register test list file comprises:
calculating a read mask value and a write mask value of the register test information;
determining a read-write value of the register test information according to the read mask value and the write mask value;
and comparing the read-write value with the expected value to determine a read-write test result.
7. The method of any of claims 1 to 6, wherein generating test cases comprises:
after the read-write test, extracting the mode authority in the register test list file;
and generating a test case corresponding to the mode authority according to the mode authority.
8. The method of any of claims 1 to 6, wherein generating test cases comprises:
obtaining a test sample;
and importing the register test information to the corresponding position of the test sample to generate the test sample.
9. An apparatus for generating a register test case comprising a processor and a memory storing program instructions, wherein the processor is configured, when executing the program instructions, to perform the method for generating a register test case as claimed in any one of claims 1 to 8.
10. A test apparatus, comprising:
an equipment body;
the apparatus for generating register test cases as recited in claim 9, being mounted to the device body.
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| CN202311650733.5A CN117725881A (en) | 2023-12-04 | 2023-12-04 | Method and device for generating register test case and test equipment |
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| CN202311650733.5A CN117725881A (en) | 2023-12-04 | 2023-12-04 | Method and device for generating register test case and test equipment |
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