CN112567375A - Format verification method, information identification method, device and storage medium - Google Patents

Format verification method, information identification method, device and storage medium Download PDF

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Publication number
CN112567375A
CN112567375A CN201980051925.XA CN201980051925A CN112567375A CN 112567375 A CN112567375 A CN 112567375A CN 201980051925 A CN201980051925 A CN 201980051925A CN 112567375 A CN112567375 A CN 112567375A
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file
unit
netlist
name
information
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刘其龙
冯鲲鹏
唐辉艳
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SZ DJI Technology Co Ltd
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SZ DJI Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/02—System on chip [SoC] design

Abstract

A form verification method, an information identification method, an apparatus, and a storage medium. The formal verification method comprises the following steps: acquiring a first file and a second file, wherein the second file is obtained according to the first file (S501); determining unit matching information corresponding to the first file and the second file, wherein the unit matching information comprises a corresponding relation between data units in the first file and data units in the second file (S502); and performing formal verification on the second file according to the unit matching information and the first file (S503). The method improves the reliability of formal verification of the second file.

Description

Format verification method, information identification method, device and storage medium
Technical Field
The embodiment of the invention relates to the technical field of chip design, in particular to a form verification method, an information identification method, equipment and a storage medium.
Background
With the rapid development of chip technology, the application of very large scale integrated circuits is becoming more and more extensive. At present, an Electronic Design Automation (EDA) tool is usually used to Design a chip, and during the process of designing the chip, form verification needs to be performed in each implementation step, so that the purpose of the form verification can be ensured to be the same before and after the Design.
In designing a chip, the EDA tool makes naming changes to the components of the design at various stages for various reasons. At this time, if the EDA tool provided by the same vendor is used, the EDA tool may use a unified file name matching method and a search method, so that the whole formal verification process may be implemented. If the EDA tools provided by different suppliers are used for form verification, the EDA tools cannot identify the form verification files due to the problems of mismatch of unit naming information of the EDA tools of different suppliers, file encryption or incompatibility among the tools of different manufacturers, so that the form verification difficulty is increased for the form verification tools of different manufacturers, and even normal form verification operation cannot be performed.
Disclosure of Invention
The embodiment of the invention provides a form verification method, an information identification method, equipment and a storage medium.
A first aspect of the present invention is to provide a formal verification method, including:
acquiring a first file and a second file, wherein the second file is obtained according to the first file;
determining unit matching information corresponding to the first file and the second file, wherein the unit matching information comprises a corresponding relation between a data unit in the first file and a data unit in the second file;
and performing form verification on the second file according to the unit matching information and the first file.
A second aspect of the present invention is to provide an information identifying method, including:
acquiring a first file and a second file, wherein the second file is obtained according to the first file and comprises at least one data unit;
determining unit matching information corresponding to the second file and the first file, wherein the unit matching information comprises a corresponding relation between the at least one data unit in the second file and the data unit in the first file;
and identifying the data unit in the second file by using the unit matching information.
A third aspect of the present invention is to provide a name information identifying method, including:
acquiring first name information of a data unit;
determining name matching information corresponding to the first name information and the second name information when a first electronic design tool changes the first name information of the data unit and generates second name information of the data unit;
sending the name matching information to a second electronic design tool for the second electronic design tool to identify a corresponding relationship between the first name information and the second name information; and
the first name information of the data unit is stored in a first file, the second name information of the data unit is stored in a second file, and the first electronic design tool and the second electronic design tool are different.
A fourth aspect of the present invention is to provide a formal verification apparatus including:
a first memory for storing a computer program;
a first processor for executing a computer program stored in the first memory to implement:
acquiring a first file and a second file, wherein the second file is obtained according to the first file;
determining unit matching information corresponding to the first file and the second file, wherein the unit matching information comprises a corresponding relation between a data unit in the first file and a data unit in the second file;
and performing form verification on the second file according to the unit matching information and the first file.
A fifth aspect of the present invention is to provide an information identifying apparatus, comprising:
a second memory for storing a computer program;
a second processor for executing the computer program stored in the second memory to implement:
acquiring a first file and a second file, wherein the second file is obtained according to the first file and comprises at least one data unit;
determining unit matching information corresponding to the second file and the first file, wherein the unit matching information comprises a corresponding relation between the at least one data unit in the second file and the data unit in the first file;
and identifying the data unit in the second file by using the unit matching information.
A sixth aspect of the present invention is to provide a name information identifying apparatus comprising:
a third memory for storing a computer program;
a third processor for executing the computer program stored in the third memory to implement:
acquiring first name information of a data unit;
determining name matching information corresponding to the first name information and the second name information when a first electronic design tool changes the first name information of the data unit and generates second name information of the data unit;
sending the name matching information to a second electronic design tool for the second electronic design tool to identify a corresponding relationship between the first name information and the second name information; and
the first name information of the data unit is stored in a first file, the second name information of the data unit is stored in a second file, and the first electronic design tool and the second electronic design tool are different.
A seventh aspect of the present invention is to provide a computer-readable storage medium, which is a computer-readable storage medium having stored therein program instructions for the form verification method according to the first aspect.
An eighth aspect of the present invention is to provide a computer-readable storage medium, which is a computer-readable storage medium having stored therein program instructions for the information identification method according to the second aspect.
A ninth aspect of the present invention is to provide a computer-readable storage medium, which is a computer-readable storage medium having stored therein program instructions for the name information identifying method according to the third aspect.
The formal verification method, the information identification method, the equipment and the storage medium provided by the embodiment of the invention effectively ensure the stability and reliability of formal verification operation.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a flow chart of an implementation of a very large scale integrated circuit according to an embodiment of the present invention;
FIG. 2 is a flow chart of a design using an electronic design automation tool according to an embodiment of the present invention;
FIG. 3 is a simplified schematic diagram of the formal verification operation shown in FIG. 2;
FIG. 4 is a schematic diagram of the formal verification shown in FIG. 3;
FIG. 5 is a flow chart of a formal verification method according to an embodiment of the present invention;
FIG. 6 is a flow chart of the method of formal verification shown in FIG. 5 to obtain a first document and a second document;
FIG. 7 is a flowchart of the method for obtaining the synthesized netlist and the layout netlist in FIG. 6;
FIG. 8 is a flow chart of another form of authentication method provided by embodiments of the present invention;
fig. 9 is a flowchart of an information identification method according to an embodiment of the present invention;
fig. 10 is a flowchart of a name information identification method according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a formal verification apparatus according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of an information identification device according to an embodiment of the present invention;
fig. 13 is a schematic structural diagram of a name information identification device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
With the rapid development of chip technology, the application of very large scale integrated circuits is becoming more and more extensive. Usually, an Electronic Design Automation (EDA) tool is used to Design a chip, and the implementation flow is shown in fig. 1 and mainly includes: designers try a hardware description language (VHDL, Verilog or HDL) to describe a design function by codes to form Register Transfer Level (RTL) codes, then, the RTL codes are logically and comprehensively processed into a comprehensive netlist, layout and wiring processing is carried out on the comprehensive netlist to obtain a physical layout design, and then, the physical layout design is verified and the like.
Specifically, as shown in fig. 2, a flow chart for designing by using an EDA tool is provided, specifically, the design flow mainly includes: the method comprises the steps of obtaining RTL design codes, carrying out synthesis and optimization processing on the RTL design codes to obtain a first netlist, carrying out scanning chain stitching based on the first netlist to obtain a second netlist after the first netlist passes formal verification, carrying out physical layout design based on the second netlist to obtain a third netlist after the second netlist passes formal verification, and carrying out formal verification operation on the third netlist.
In the above design process, formal verification is required between each step, and the purpose of formal verification is to ensure that the design is the same before and after. Currently, existing EDA tools name and change the composition of each register in the design at each stage for various reasons, for example: a register merge unit, a register ungroup unit, etc. In general, if a design tool provided by an EDA vendor is selected for the whole design process, the design tool can read the register unit normally, and as shown in fig. 3, after the first design tool is used to design the first design a into the second design B, if the first design tool is used to perform the formal verification, the whole formal verification process can be implemented stably. Specifically, as shown in fig. 4, the implementation flow of formal verification may include: form verification, reference information loading, tool loading, guide information loading, setting execution, comparison point matching, form verification operation running and verification result obtaining are carried out, then the verification result can be analyzed and processed, whether the form verification operation is successful or not is judged, and if the form verification operation is successful, the form verification operation is finished; and if the formal verification operation is unsuccessful, debugging.
In the above process, matching the comparison points is the most critical step, and in general, the matching operation can be automatically performed by using a design tool. After the matching comparison point is abnormal, for example: because the design tools of different manufacturers are incompatible and the like, the design tools of different manufacturers cannot be commonly used, at the moment, the conditions that unit naming information is not matched and cannot be searched easily occur in the form verification process, the error place needs to be searched in the result of each stage, and manual command matching needs to be added, so that the form verification efficiency is low, the labor cost is high, the project schedule is easily delayed, and the process automation is not easy to realize; furthermore, it is difficult for users using multiple EDA tools to perform formal verification, and debugging is greatly hindered.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The features of the embodiments and examples described below may be combined with each other without conflict between the embodiments.
FIG. 5 is a flow chart of a formal verification method according to an embodiment of the present invention; referring to fig. 5, the present embodiment provides a formal verification method, the execution subject of which is a formal verification device, it being understood that the formal verification device may be implemented as software, or a combination of software and hardware. Specifically, the formal verification method may include:
step S501: and acquiring a first file and a second file, wherein the second file is obtained according to the first file.
Step S502: and determining unit matching information corresponding to the first file and the second file, wherein the unit matching information comprises the corresponding relation between the data units in the first file and the data units in the second file.
Step S503: and performing form verification on the second file according to the unit matching information and the first file.
The following is detailed for the above steps:
step S501: and acquiring a first file and a second file, wherein the second file is obtained according to the first file.
Wherein the first file may include a synthesized netlist corresponding to the chip design code, and the second file may include a layout netlist corresponding to the synthesized netlist. Specifically, after the chip design code is obtained, logic synthesis processing can be performed on the chip design code by using an EDA tool to obtain a synthesis netlist corresponding to the chip design code; after the synthesized netlist is obtained, layout and routing processing can be performed based on the synthesized netlist, so that a layout netlist corresponding to the synthesized netlist can be obtained.
It is understood that the information represented by the first file and the second file is not limited to the synthesized netlist and the layout netlist, which are exemplified above, and those skilled in the art can set the information according to the specific application requirements and design requirements, for example: the first file may include a source program file and the second file may include a synthesized netlist corresponding to the chip design code; or, the first file may include a synthesized netlist corresponding to the chip design code, and the second file may include a netlist generated after logic test; alternatively, the first file may include a netlist generated after logic testing, the second file may include a layout netlist, and so on.
Step S502: and determining unit matching information corresponding to the first file and the second file, wherein the unit matching information comprises the corresponding relation between the data units in the first file and the data units in the second file.
After the first file and the second file are obtained, the first file and the second file may be analyzed to determine unit matching information corresponding to the first file and the second file according to the analysis result, and in some examples, in the form verification process, if the name information of at least one data unit in the first file does not correspond to the name information of all data units in the second file, the unit matching information corresponding to the first file and the second file may be determined. The unit matching information may include a correspondence between the data unit in the first file and the data unit in the second file.
In other examples, when the name information of at least one data unit in the second file does not correspond to the name information of all data units in the first file, then unit match information corresponding to the second file and the first file may be determined. The unit matching information may include a correspondence between the data unit in the second file and the data unit in the first file.
In other examples, in the form verification process, if the data unit in the second file cannot be identified and the name information of the data unit can be obtained, unit matching information corresponding to the first file and the second file is determined, where the unit matching information may include a correspondence between the name information of the data unit in the second file and the data unit in the first file and the name information of the data unit, so as to determine the data unit that cannot be identified in the second file based on the unit matching information and the name information of the data unit.
In other examples, in the form verification process, if the data unit in the second file and the name information corresponding to the data unit cannot be identified and the input-output relationship of the data unit can be identified, the unit matching information corresponding to the second file and the first file is determined. The unit matching information may include a corresponding relationship between an input-output relationship of each data unit in the second file and an input-output relationship of each data unit in the first file, so as to determine, based on the unit matching information and the input-output relationship, a data unit that cannot be identified in the second file and name information corresponding to the data unit.
For example, the first file includes a data unit a, a data unit B, and a data unit C, where the names of the data unit a, the data unit B, and the data unit C are a name a, a name B, and a name C, respectively; the second file comprises a data unit A ', a data unit B ' and a data unit C ', and the names corresponding to the data unit A ', the data unit B ' and the data unit C ' are respectively a name a ', a name B ' and a name C '; wherein, the data unit A corresponds to the data unit A ', the data unit B corresponds to the data unit B ', and the data unit C corresponds to the data unit C '.
In one embodiment, data unit A, data unit B, and data unit C in the first file are data unit A ', data unit B ', and data unit C ' in the second file, respectively. That is, the data unit a, the data unit B, and the data unit C in the first file are the same in function and/or kind as the data unit a ', the data unit B', and the data unit C 'in the second file, respectively, but the names of the data unit a, the data unit B, and the data unit C in the first file are different from the names of the corresponding data unit a', the data unit B ', and the data unit C' in the second file.
In one embodiment, since the name information of the data units in the first file is different from the name information of the data units in the second file, when performing formal verification on the second file, the name information corresponding to at least one data unit in the second file may not be recognized, for example: the name B 'of the data unit B' cannot be recognized. In performing formal verification, it is not possible for a data unit B 'in the second file to determine to which data unit in the first file this data unit B' corresponds. Alternatively, for data unit B in the first file, it cannot be determined to which data unit B in the second file this data unit B corresponds. At this time, in order to implement the format verification operation on the first file and the second file, unit matching information corresponding to the first file and the second file may be determined, where the determined unit matching information may include a correspondence between a data unit in the first file and a data unit in the second file, that is, the unit matching information at this time includes a correspondence between a data unit B ' and the data unit B (e.g., a correspondence between names of the data unit B ' and the data unit B, and a correspondence between input and output relationships of the data unit B ' and the data unit B); through the acquired unit matching information, stable topographic form verification operation can be conveniently carried out on the first file and the second file.
Since the name information of the data units in the first file is different from the name information of the data units in the second file, the data units in the first file corresponding to at least one data unit in the second file may not be identified when the second file is formal verified. That is, when the second file is formal-verified, it may also occur that the name information of at least one data unit in the second file does not correspond to the name information of all data units in the first file. In one embodiment, data units of a function and/or category corresponding to data units in the second file are not identified in the first file. For example, for the second file, the data unit B ' of the second file and the name B ' corresponding to the data unit B ' can be identified, and for the first file, the data unit B of the first file and the name B corresponding to the data unit B can be identified. However, it is not recognized that the data unit B' of the second file corresponds to the data unit B of the first file. Or it is not recognized that the name B 'of the data unit B' of the second file corresponds to the name B of the data unit B of the first file. For another example, for the first file, the data unit B of the first file and the name B corresponding to the data unit B can be identified. For the second file, the data unit B ' of the second file and the name B ' corresponding to the data unit B ' can be identified. However, it is not recognized that the data unit B of the first file corresponds to the data unit B' of the second file. Or it cannot be recognized that the name B of the data unit B of the first file corresponds to the name B 'of the data unit B' of the second file. At this time, unit matching information corresponding to the first file and the second file is determined, and the determined unit matching information may include a correspondence between the data unit in the first file and the data unit in the second file, that is, the unit matching information includes a correspondence between the name B 'of the data unit B' and the data unit B and the name B. Therefore, by the acquired cell matching information, stable topographic form verification operation for the first file and the second file is facilitated.
In some examples, determining unit matching information corresponding to the first file and the second file may include: and acquiring an input corresponding relation aiming at the register unit based on the comprehensive netlist and the layout netlist. And acquiring unit matching information corresponding to the comprehensive netlist and the layout netlist according to the input corresponding relation.
Specifically, after the comprehensive netlist and the layout netlist are obtained, the comprehensive netlist and the layout netlist can be analyzed, so that an input-output corresponding relation for the register unit is obtained, and then unit matching information corresponding to the comprehensive netlist and the layout netlist can be obtained according to the input-output corresponding relation.
For example, if the input/output connection relationship of the register unit a in the synthesized netlist is identical or similar to the input/output connection relationship of the register unit C in the layout netlist, the register unit a in the synthesized netlist corresponds to the register unit C in the layout netlist. That is, register cell a in the synthesized netlist matches register cell C in the layout netlist. In one embodiment, the synthesized netlist includes a register unit a, an input signal of the register unit a is an output signal of a register unit B, in this case, the layout netlist includes a register unit C, an input signal of the register unit C is an output signal of a register unit B ', the register unit B' corresponds to the register unit B, and when neither the register a nor the register C has other elements directly connected to them, the register unit a in the synthesized netlist and the register unit C in the layout netlist are considered to correspond to each other. That is, register cell a in the synthesized netlist matches register cell C in the layout netlist. And generating a unit matching relation, wherein the unit matching information indicates that the register unit A of the comprehensive netlist corresponds to the register unit C of the layout netlist.
It is understood that the correspondence existing in the unit matching information may be a one-way correspondence, for example: the corresponding relation from the register unit A of the comprehensive netlist to the register unit C of the layout netlist, or the corresponding relation from the register unit C of the layout netlist to the register unit A of the comprehensive netlist; alternatively, the correspondence existing in the unit matching information may also be a bidirectional correspondence, and may include: the corresponding relation from the register unit A of the synthesized netlist to the register unit C of the layout netlist and the corresponding relation from the register unit C of the layout netlist to the register unit A of the synthesized netlist.
In other examples, determining the cell matching information corresponding to the first file and the second file may include: and acquiring the corresponding relation of the input and output elements of the register unit and the corresponding relation of the name of the register unit based on the comprehensive netlist and the layout netlist. And acquiring unit matching information corresponding to the comprehensive netlist and the layout netlist according to the corresponding relation of the input and output elements of the register unit and the corresponding relation of the name of the register unit. For example, if the name of a first register unit in the synthesized netlist and the name of a second register unit in the layout netlist have the same keyword, the first register unit in the synthesized netlist and the second register unit in the layout netlist correspond to each other.
Specifically, after the comprehensive netlist and the layout netlist are obtained, the comprehensive netlist and the layout netlist can be analyzed, so that an input corresponding relation and a name corresponding relation for the register unit are obtained, and then unit matching information corresponding to the comprehensive netlist and the layout netlist can be obtained according to the input corresponding relation and the name corresponding relation.
For example, the synthesized netlist includes register unit a, the name information of which is name information a, the input information of the register unit A is a register unit B, at this time, a register unit C is included in the layout netlist, the name information of the register unit C is name information C, the input information of the register unit C is register unit B', and register unit B' corresponds to register unit B, unit matching information can be generated, the unit matching information includes the corresponding relationship between the register unit A and the register unit C and/or the corresponding relationship between the name information a and the name information C, the corresponding relationship included in the unit matching information is similar to the corresponding relationship in the above embodiment, that is, the corresponding relationship may be a one-way corresponding relationship or a two-way corresponding relationship.
Step S503: and performing form verification on the second file according to the unit matching information and the first file.
After the unit matching information is acquired, the second file can be subjected to formal verification according to the unit matching information and the first file, so that the stability and reliability of the formal verification of the second file are effectively guaranteed.
In the formal verification method provided by this embodiment, the first file and the second file are obtained, the unit matching information corresponding to the first file and the second file is determined, and then the second file is subjected to formal verification according to the unit matching information and the first file, because the unit matching information may include a correspondence between a data unit in the first file and a data unit in the second file, at this time, it is possible to perform formal verification stably and effectively while performing formal verification by using formal verification devices of different suppliers, which not only ensures the quality and efficiency of formal verification operations, but also reduces the difficulty of performing formal verification for users using various EDA tools, and at the same time, provides a great convenience for debugging work, and further improves the practicability of the method.
FIG. 6 is a flow chart of the method of formal verification shown in FIG. 5 to obtain a first document and a second document; on the basis of the foregoing embodiment, with reference to fig. 6, when the first file includes the synthesized netlist corresponding to the chip design code, and the second file includes the layout netlist corresponding to the synthesized netlist, the obtaining the first file and the second file in this embodiment may include:
step S601: and acquiring a comprehensive netlist corresponding to the chip design code, wherein the comprehensive netlist comprises a register unit.
Step S602: and obtaining a layout netlist based on the comprehensive netlist, wherein the name information of the register unit in the comprehensive netlist is different from the name information of the corresponding register unit in the layout netlist.
After the chip design code is obtained, logic synthesis processing can be performed on the chip design code, so that a synthesis netlist corresponding to the chip design code can be obtained, and at the moment, the synthesis netlist can comprise one or more register units; after the comprehensive netlist is obtained, the comprehensive netlist can be analyzed to obtain a layout netlist, and specifically, the process of obtaining the layout netlist based on the comprehensive netlist can include: carrying out layout and wiring processing on the comprehensive netlist by using a preset tool to obtain a layout netlist corresponding to the comprehensive netlist; at this time, the name information of the register unit in the synthesized netlist is different from the name information of the corresponding register unit in the layout netlist.
It is understood that all first register cells and first name information corresponding to the first register cells may be included in the synthesized netlist; all the second register units and second name information corresponding to the second register units can be included in the layout netlist; and the first register unit in the synthesized netlist corresponds to the second register unit in the layout netlist.
It should be noted that the preset tool may be an EDA tool that is preset and used for performing layout and routing processing on the synthesized netlist, the preset tool and the formal verification device may belong to the same vendor, or the preset tool and the formal verification device may also belong to different vendors, as shown in fig. 7, the synthesized netlist may be processed by the preset tool to obtain the layout netlist, at this time, the preset tool may generate unit matching information, and then the second file may be subjected to formal verification according to the unit matching information and the first file.
In the embodiment, the comprehensive netlist corresponding to the chip design code is obtained, and then the layout netlist is obtained based on the comprehensive netlist, so that the accuracy and reliability of the comprehensive netlist and the layout netlist are effectively ensured.
FIG. 8 is a flowchart of a formal verification method according to an embodiment of the present invention; in the above embodiment, referring to fig. 8, the method in the present embodiment may be applied to a formal verification apparatus, and when performing formal verification operations using the formal verification apparatus, the following may occur: in the first file, the name information of the data unit or data unit located in the first file corresponding to the at least one data unit in the second file cannot be identified, or in the second file, the name information of the data unit or data unit located in the second file corresponding to the name information of the at least one data unit in the first file cannot be identified. For convenience of explanation, the above-described case in which the formal verification apparatus appears is collectively referred to as the case in which the formal verification apparatus cannot identify the register unit. Specifically, the method may include:
step S801: and detecting whether the formal verification equipment and the preset tool belong to the same supplier.
Step S802: when the formal verification device and the preset tool belong to different suppliers, it is determined that the formal verification device cannot identify the correspondence between the register units respectively located in different files generated by the preset tool. Alternatively, the first and second electrodes may be,
step S803: when the formal verification device and the preset tool belong to the same vendor, it is determined that the formal verification device can identify the register unit.
After the formal verification device and the preset tool are obtained, in order to ensure the quality and efficiency of the formal verification operation, the formal verification device and the preset tool may be detected, that is, whether the formal verification device and the preset tool belong to the same provider is identified, specifically, first provider identification information of the formal verification device and second provider identification information of the preset tool may be obtained, and whether the formal verification device and the preset tool belong to the same provider may be detected through the first provider identification information and the second provider identification information. When the first vendor identification information and the second vendor identification information are the same, it may be determined that the formal verification apparatus and the preset tool belong to the same vendor, and the formal verification apparatus can identify the register unit at this time. When the first vendor identification information and the second vendor identification information are different, it may be determined that the formal verification apparatus and the preset tool belong to different vendors, and it may be determined that the formal verification apparatus cannot identify the register unit.
In some examples, after determining that the formal verification device is able to identify the register unit, the method further comprises:
step S804: and performing formal verification on the layout netlist by using formal verification equipment and the comprehensive netlist.
When the formal verification equipment can identify the register unit, the formal verification equipment and the comprehensive netlist can be directly used for performing formal verification on the layout netlist, so that the quality and the efficiency of the formal verification are improved.
It should be noted that the above steps are optional steps, that is, when an operation of performing formal verification on the layout netlist is configured, the method in this embodiment may include the above step S804; when the operation of performing formal verification on the layout netlist is not configured, the method in this embodiment does not include step S804.
In specific application, the first file can be a comprehensive netlist corresponding to the chip design code, the second file can be a layout netlist corresponding to the comprehensive netlist, and the layout netlist can be obtained by performing layout and routing processing on the comprehensive netlist through a preset tool. Then, the formal verification operation of the layout netlist is performed by using formal verification equipment belonging to a different supplier from the preset tool, and since the name information of the register unit in the synthesized netlist is different from the name information of the register unit in the layout netlist, the formal verification operation can be realized through unit matching information. Specifically, the formal verification method may include:
the first step is as follows: and analyzing the comprehensive netlist by using a preset tool to obtain a layout netlist, and specifically, adding mark information corresponding to the preset tool in the layout netlist when obtaining the layout netlist.
The second step is that: and automatically generating unit matching information by using a preset tool, wherein the unit matching information corresponds to the comprehensive netlist and the layout netlist.
Specifically, the unit matching information may be automatically generated by using a script in a preset tool, and the unit matching information may include an input correspondence relationship between register units in the synthesized netlist after the register units in the synthesized netlist are processed by the preset tool.
The third step: and performing formal verification operation on the layout netlist by using formal verification equipment and unit matching information.
The operation process of the form verification comprises the matching of the register units, and the form verification after the matching is to verify whether the input signals of the matching units are the same or not, so that whether the form verification is successful or not is determined. Specifically, after the unit matching information is obtained, the corresponding relationship between the naming information of the register unit in the layout netlist and the naming information of the register unit in the synthesized netlist can be determined based on the unit matching information, so that the formal verification operation of the layout netlist can be realized based on the unit matching information.
In the form verification method provided by the application embodiment, the incompatible characteristics of different design tools are considered, and meanwhile, in order to ensure the quality and efficiency of form verification operation, when the name information of any register unit is changed, unit matching information can be generated, and then when form verification is performed by using different design tools, the register unit can be identified through the unit matching information, so that the accuracy of name information matching of the register unit is ensured, and it needs to be noted that the method can process large batches of files, and further the application range of the method is improved; meanwhile, the efficiency and the success rate of the form verification are improved, the possibility of data loss in the file conversion process is reduced, and the inquiry and the positioning are convenient for follow-up debugging problems.
Fig. 9 is a flowchart of an information identification method according to an embodiment of the present invention; referring to fig. 9, the present embodiment provides an information recognition method, the execution subject of which is an information recognition apparatus, it being understood that the information recognition apparatus may be implemented as software, or a combination of software and hardware. Specifically, the information identification method may include:
step S901: the method comprises the steps of obtaining a first file and a second file, wherein the second file is obtained according to the first file, and the second file comprises at least one data unit.
Step S902: and determining unit matching information corresponding to the second file and the first file, wherein the unit matching information comprises the corresponding relation between at least one data unit in the second file and the data unit in the first file.
Step S903: the data units in the second file are identified using the unit matching information.
The following is detailed for the above steps:
step S901: the method comprises the steps of obtaining a first file and a second file, wherein the second file is obtained according to the first file, and the second file comprises at least one data unit.
In some examples, the first file includes a synthesized netlist corresponding to the chip design code, and the second file includes a layout netlist corresponding to the synthesized netlist; or the first file comprises a source program file, and the second file comprises a synthesized netlist corresponding to the chip design code; or the first file comprises a comprehensive netlist corresponding to the chip design code, and the second file comprises a netlist generated after logic test; or the first file comprises a netlist generated after logic test, and the second file comprises a layout netlist.
It will be appreciated that where the first file and the second file represent different information, the at least one data element included in the second file may also have a different representation, for example where the second file is a netlist file, the at least one data element included in the second file may be at least one register element. Similarly, when the first file is a netlist file, the first file may include at least one register unit therein, and the name information of the at least one register unit in the first file is different from the name information of the corresponding register unit in the second file.
In some examples, the second file is a result of processing the first file by a first electronic design automation tool; the first file, the second file, and the cell matching information are simultaneously used for data processing of a second electronic design automation tool, wherein the first electronic design automation tool and the second electronic design automation tool are different.
Further, when it is detected that the first electronic design automation tool changes at least one first data unit in the first file and generates at least one data unit stored in the second file, it is determined that the at least one data unit in the second file corresponds to the at least one first data unit in the first file.
Further, the first file, the second file, and the cell matching information are simultaneously used for data processing of a second electronic design automation tool, including: the first document and the cell matching information are simultaneously used in a formal verification process of the second document by the second electronic design automation tool.
Step S902: and determining unit matching information corresponding to the second file and the first file, wherein the unit matching information comprises the corresponding relation between at least one data unit in the second file and the data unit in the first file.
In some examples, when the name information corresponding to at least one data unit in the second file cannot be identified, determining unit matching information corresponding to the first file and the second file; alternatively, when a data unit corresponding to the name information of at least one data unit in the second file cannot be identified in the first file, unit matching information corresponding to the second file and the first file is determined.
Specifically, determining the unit matching information corresponding to the second file and the first file may include: acquiring an input corresponding relation and a name corresponding relation aiming at the register unit based on the first file and the second file; and acquiring unit matching information corresponding to the first file and the second file according to the input corresponding relation and the name corresponding relation.
In some examples, determining unit matching information corresponding to the second file and the first file may include: acquiring an input corresponding relation of at least one data unit based on the first file and the second file; and acquiring unit matching information corresponding to the first file and the second file according to the input corresponding relation.
Step S903: the data units in the second file are identified using the unit matching information.
After the unit matching information is acquired, the data unit in the second file can be identified by using the unit matching information, so that the accuracy and reliability of information identification are effectively ensured, and the second file is conveniently applied and processed.
It should be noted that, the specific implementation procedure, implementation effect and implementation principle of the above method steps in this embodiment are similar to the specific implementation procedure, implementation effect and implementation principle of the method in the embodiment shown in fig. 5 to 8 in the above example, and reference may be made to the related description of the embodiment shown in fig. 5 to 8 for the part of this embodiment that is not described in detail. The implementation process and technical effect of the technical solution refer to the descriptions in the embodiments shown in fig. 5 to 8, and are not described herein again.
Fig. 10 is a flowchart of a name information identification method according to an embodiment of the present invention; as shown in fig. 10, the present embodiment provides a name information identifying method, the execution subject of which is a name information identifying device, it being understood that the name information identifying device may be implemented as software, or a combination of software and hardware. Specifically, the name information identification method may include:
step S1001: first name information of a data unit is acquired.
Step S1002: when the first electronic design tool changes the first name information of the data unit and generates the second name information of the data unit, determining name matching information corresponding to the first name information and the second name information.
Step S1003: and sending the name matching information to a second electronic design tool so that the second electronic design tool can identify the corresponding relation between the first name information and the second name information.
Wherein the first electronic design tool and the second electronic design tool are different; at this time, when the first electronic design tool is used to change the first name information of the data unit into the second name information, the first electronic design tool may determine the name matching information corresponding to the first name information and the second name information in order to ensure that the second name information of the data unit can be accurately recognized by another electronic design tool (second electronic design tool). Specifically, the first name information of the data unit is stored in a first file, and the second name information of the data unit is stored in a second file, in this case, the name matching information may be understood as the name correspondence relationship of the data unit corresponding to the first file and the second file. In some examples, the first file is generated prior to the second file during the chip design process. Or the first file and the second file are both generated in the chip design process, and the first file is used for generating the second file.
In some examples, the second electronic design tool is used for formal verification of chip design, and at this time, after the second electronic design tool obtains the name matching information, formal verification may be performed on the second file based on the name matching information and the first file, so as to ensure that the first file and the second file meet preset requirements.
In some examples, the name matching information may include the first name information, the second name information, and an index between the first name information and the second name information; or the name matching information comprises first name information, second name information and an index from the second name information to the first name information; or, the name matching information may further include: the first name information, the second name information, and the bidirectional index information from the first name information to the second name information.
After determining the name matching information, the name matching information may be sent to a second electronic design tool, and at this time, the second electronic design tool may identify, based on the name matching information, a correspondence between second name information of the data unit in the second file and first name information of the data unit in the first file, thereby achieving effective identification of the data unit.
According to the name information identification method provided by the embodiment, the first name information of the data unit is obtained, when the first electronic design tool changes the first name information of the data unit and generates the second name information of the data unit, the name matching information corresponding to the first name information and the second name information is determined, and the name matching information is sent to the second electronic design tool, so that the second electronic design tool can effectively identify the corresponding relation between the first name information and the second name information, the accuracy and reliability of name information identification are effectively ensured, the name information of the data unit can be identified by using different electronic design tools, and the application range of the method is further expanded.
In some examples, sending the name matching information to the second electronic design tool may include: storing name matching information about the first name information and the second name information in a name matching file; and sending the name matching file to a second electronic design tool.
Specifically, when the name matching information is sent to the second electronic design tool, in order to ensure the safety and reliability of the name matching information transmission, the name matching information about the first name information and the second name information may be stored in one name matching file, and then the name matching file is sent to the second electronic design tool, so that the stability and reliability of the method are improved.
Fig. 11 is a schematic structural diagram of a formal verification apparatus according to an embodiment of the present invention; referring to fig. 11, the present embodiment provides a formal verification apparatus that can perform the formal verification method shown in fig. 5 described above. Specifically, the formal verification device may include:
a first memory 12 for storing a computer program;
a first processor 11 for executing the computer program stored in the first memory 12 to implement:
acquiring a first file and a second file, wherein the second file is obtained according to the first file;
determining unit matching information corresponding to the first file and the second file, wherein the unit matching information comprises a corresponding relation between a data unit in the first file and a data unit in the second file;
and performing form verification on the second file according to the unit matching information and the first file.
The formal verification device may further include a first communication interface 13 for the electronic device to communicate with other devices or a communication network.
In some examples, the first processor 11 is further configured to: when the name information corresponding to at least one data unit in the second file cannot be identified, determining unit matching information corresponding to the first file and the second file; when a data unit corresponding to the name information of at least one data unit in the second file cannot be identified in the first file, unit matching information corresponding to the first file and the second file is determined.
In some examples, the first file includes a synthesized netlist corresponding to the chip design code and the second file includes a layout netlist corresponding to the synthesized netlist.
In some examples, when the first processor 11 obtains the first file and the second file, the first processor 11 is configured to: acquiring a comprehensive netlist corresponding to the chip design code, wherein the comprehensive netlist comprises a register unit; and obtaining a layout netlist based on the comprehensive netlist, wherein the name information of the register unit in the comprehensive netlist is different from the name information of the corresponding register unit in the layout netlist.
In some examples, the synthesized netlist includes all of the first register cells and first name information corresponding to the first register cells; the layout netlist comprises all second register units and second name information corresponding to the second register units; and the first register unit in the synthesized netlist corresponds to the second register unit in the layout netlist.
In some examples, when the first processor 11 obtains the layout netlist based on the synthesized netlist, the first processor 11 is configured to: and carrying out layout and wiring processing on the comprehensive netlist by using a preset tool to obtain a layout netlist corresponding to the comprehensive netlist.
In some examples, the first processor 11 is further configured to: detecting whether the formal verification equipment and the preset tool belong to the same supplier or not; when the formal verification equipment and the preset tool belong to different suppliers, determining that the formal verification equipment cannot identify the corresponding relation between the register units respectively located in different files generated by the preset tool; alternatively, when the formal verification device and the preset tool belong to the same vendor, it is determined that the formal verification device can identify the register unit.
In some examples, the first processor 11 is further configured to: and after determining that the formal verification equipment can identify the register unit, performing formal verification on the layout netlist by using the formal verification equipment and the synthesized netlist.
In some examples, when the first processor 11 determines the unit matching information corresponding to the first file and the second file, the first processor 11 is configured to: acquiring an input corresponding relation aiming at the register unit based on the comprehensive netlist and the layout netlist; and acquiring unit matching information corresponding to the comprehensive netlist and the layout netlist according to the input corresponding relation.
In some examples, when the first processor 11 determines the unit matching information corresponding to the first file and the second file, the first processor 11 is configured to: acquiring an input corresponding relation and a name corresponding relation aiming at the register unit based on the comprehensive netlist and the layout netlist; and acquiring unit matching information corresponding to the comprehensive netlist and the layout netlist according to the input corresponding relation and the name corresponding relation.
The apparatus shown in fig. 11 can execute the method of the embodiment shown in fig. 5-8, and the detailed description of this embodiment can refer to the related description of the embodiment shown in fig. 5-8. The implementation process and technical effect of the technical solution refer to the descriptions in the embodiments shown in fig. 5 to 8, and are not described herein again.
Fig. 12 is a schematic structural diagram of an information identification device according to an embodiment of the present invention; referring to fig. 12, the present embodiment provides an information identifying apparatus that can perform the information identifying method shown in fig. 9 described above. Specifically, the information recognition apparatus may include:
a second memory 22 for storing a computer program;
a second processor 21 for executing the computer program stored in the second memory 22 to implement:
acquiring a first file and a second file, wherein the second file is obtained according to the first file and comprises at least one data unit;
determining unit matching information corresponding to the second file and the first file, wherein the unit matching information comprises a corresponding relation between at least one data unit in the second file and a data unit in the first file;
the data units in the second file are identified using the unit matching information.
The information identification device may further include a second communication interface 23, which is used for the electronic device to communicate with other devices or a communication network.
In some examples, a second processor 21 to: when the name information corresponding to at least one data unit in the second file cannot be identified, determining unit matching information corresponding to the first file and the second file; alternatively, when a data unit corresponding to the name information of at least one data unit in the second file cannot be identified in the first file, unit matching information corresponding to the second file and the first file is determined.
In some examples, the first file includes a synthesized netlist corresponding to the chip design code, and the second file includes a layout netlist corresponding to the synthesized netlist; or the first file comprises a source program file, and the second file comprises a synthesized netlist corresponding to the chip design code; or the first file comprises a comprehensive netlist corresponding to the chip design code, and the second file comprises a netlist generated after logic test; or the first file comprises a netlist generated after logic test, and the second file comprises a layout netlist.
In some examples, the first file includes at least one register unit therein, and name information of the at least one register unit in the first file is different from name information of a corresponding register unit in the second file; and, when the second processor 21 acquires the first file and the second file, the second processor 21 is configured to: a second file is obtained based on the first file.
In some examples, when the second processor 21 determines the unit matching information corresponding to the second file and the first file, the second processor 21 is configured to: acquiring an input corresponding relation and a name corresponding relation aiming at the register unit based on the first file and the second file; and acquiring unit matching information corresponding to the first file and the second file according to the input corresponding relation and the name corresponding relation.
In some examples, the second file is a result of processing the first file by a first electronic design automation tool; the first file, the second file, and the cell matching information are simultaneously used for data processing of a second electronic design automation tool, wherein the first electronic design automation tool and the second electronic design automation tool are different.
In some examples, when it is detected that the first electronic design automation tool changed at least one first data unit in the first file and generated at least one data unit stored in the second file, it is determined that the at least one data unit in the second file corresponds to the at least one first data unit in the first file.
In some examples, the first file, the second file, and the cell matching information are used simultaneously for data processing by a second electronic design automation tool, including: the first document and the cell matching information are simultaneously used in a formal verification process of the second document by the second electronic design automation tool.
In some examples, when the second processor 21 determines the unit matching information corresponding to the second file and the first file, the second processor 21 is configured to: acquiring an input corresponding relation of at least one data unit based on the first file and the second file; and acquiring unit matching information corresponding to the first file and the second file according to the input corresponding relation.
The apparatus shown in fig. 12 may perform the method of the embodiment shown in fig. 9, and reference may be made to the related description of the embodiment shown in fig. 9 for a part of this embodiment that is not described in detail. The implementation process and technical effect of the technical solution are described in the embodiment shown in fig. 9, and are not described herein again.
Fig. 13 is a schematic structural diagram of a name information identification device according to an embodiment of the present invention; referring to fig. 13, the present embodiment provides a name information identifying apparatus that can perform the above-described name information identifying method shown in fig. 10. Specifically, the name information identifying device may include:
a third memory 32 for storing a computer program;
a third processor 31 for executing the computer program stored in the third memory 32 to implement:
acquiring first name information of a data unit;
when the first electronic design tool changes the first name information of the data unit and generates the second name information of the data unit, determining name matching information corresponding to the first name information and the second name information;
sending the name matching information to a second electronic design tool for the second electronic design tool to identify a corresponding relationship between the first name information and the second name information; and
the first name information of the data unit is stored in a first file, the second name information of the data unit is stored in a second file, and the first electronic design tool and the second electronic design tool are different.
The name information identifying device may further include a third communication interface 33, which is used for the electronic device to communicate with other devices or a communication network.
In some examples, when the third processor 31 sends the name matching information to the second electronic design tool, the third processor 31 is configured to: storing name matching information about the first name information and the second name information in a name matching file; and sending the name matching file to a second electronic design tool.
In some examples, the name matching information includes first name information, second name information, and an index between the first name information to the second name information; or the name matching information comprises the first name information, the second name information and an index from the second name information to the first name information.
In some examples, the second electronic design tool is used for formal verification of the chip design.
In some examples, the first file is generated prior to the second file during the chip design process.
In some examples, the first file and the second file are both files generated during the chip design process, and the first file is used to generate the second file.
The apparatus shown in fig. 13 may perform the method of the embodiment shown in fig. 10, and reference may be made to the related description of the embodiment shown in fig. 10 for a part of this embodiment that is not described in detail. The implementation process and technical effect of the technical solution are described in the embodiment shown in fig. 10, and are not described herein again.
In addition, the embodiment of the present invention provides a computer storage medium for storing computer software instructions for an electronic device, which includes a program for executing the formal verification method in the method embodiments shown in fig. 5 to 8.
An embodiment of the present invention provides a computer storage medium for storing computer software instructions for an electronic device, which includes a program for executing the information identification method in the method embodiment shown in fig. 9.
An embodiment of the present invention provides a computer storage medium for storing computer software instructions for an electronic device, which includes a program for executing the name information identification method in the method embodiment shown in fig. 10.
The technical solutions and the technical features in the above embodiments may be used alone or in combination in case of conflict with the present disclosure, and all embodiments that fall within the scope of protection of the present disclosure are intended to be equivalent embodiments as long as they do not exceed the scope of recognition of those skilled in the art.
In the embodiments provided in the present invention, it should be understood that the disclosed related devices and methods can be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (53)

1. A formal verification method, comprising:
acquiring a first file and a second file, wherein the second file is obtained according to the first file;
determining unit matching information corresponding to the first file and the second file, wherein the unit matching information comprises a corresponding relation between a data unit in the first file and a data unit in the second file;
and performing form verification on the second file according to the unit matching information and the first file.
2. The method of claim 1,
when the name information corresponding to at least one data unit in the second file cannot be identified, determining unit matching information corresponding to the first file and the second file;
when a data unit corresponding to the name information of the at least one data unit in the second file cannot be identified in the first file, determining unit matching information corresponding to the first file and the second file.
3. The method of claim 1,
the first file comprises a comprehensive netlist corresponding to a chip design code, and the second file comprises a layout netlist corresponding to the comprehensive netlist.
4. The method of claim 3, wherein obtaining the first file and the second file comprises:
acquiring a comprehensive netlist corresponding to a chip design code, wherein the comprehensive netlist comprises a register unit;
and obtaining the layout netlist based on the comprehensive netlist, wherein the name information of the register unit in the comprehensive netlist is different from the name information of the corresponding register unit in the layout netlist.
5. The method of claim 4,
the comprehensive netlist comprises all first register units and first name information corresponding to the first register units;
the layout netlist comprises all second register units and second name information corresponding to the second register units;
and the first register unit in the synthesized netlist corresponds to the second register unit in the layout netlist.
6. The method of claim 4, wherein obtaining the layout netlist based on the synthesized netlist comprises:
and carrying out layout and wiring processing on the comprehensive netlist by using a preset tool to obtain a layout netlist corresponding to the comprehensive netlist.
7. The method of claim 6, applied to a formal verification device, the method further comprising:
detecting whether the formal verification equipment and the preset tool belong to the same supplier or not;
when the formal verification device and the preset tool belong to different suppliers, determining that the formal verification device cannot identify the corresponding relations between the register units respectively located in different files generated by the preset tool; alternatively, the first and second electrodes may be,
determining that the formal verification device is capable of identifying the register unit when the formal verification device and the preset tool belong to the same vendor.
8. The method of claim 7, wherein after determining that the form verification device is able to identify the register unit, the method further comprises:
and performing formal verification on the layout netlist by using the formal verification equipment and the comprehensive netlist.
9. The method of any of claims 4-8, wherein determining unit match information corresponding to the first file and the second file comprises:
acquiring an input corresponding relation aiming at the register unit based on the comprehensive netlist and the layout netlist;
and acquiring unit matching information corresponding to the comprehensive netlist and the layout netlist according to the input corresponding relation.
10. The method of any of claims 4-8, wherein determining unit match information corresponding to the first file and the second file comprises:
acquiring an input corresponding relation and a name corresponding relation aiming at the register unit based on the comprehensive netlist and the layout netlist;
and acquiring unit matching information corresponding to the comprehensive netlist and the layout netlist according to the input corresponding relation and the name corresponding relation.
11. An information identification method, comprising:
acquiring a first file and a second file, wherein the second file is obtained according to the first file and comprises at least one data unit;
determining unit matching information corresponding to the second file and the first file, wherein the unit matching information comprises a corresponding relation between the at least one data unit in the second file and the data unit in the first file;
and identifying the data unit in the second file by using the unit matching information.
12. The method of claim 11,
when the name information corresponding to at least one data unit in the second file cannot be identified, determining unit matching information corresponding to the first file and the second file; alternatively, the first and second electrodes may be,
when a data unit corresponding to the name information of the at least one data unit in the second file cannot be identified in the first file, determining unit matching information corresponding to the second file and the first file.
13. The method of claim 11,
the first file comprises a comprehensive netlist corresponding to a chip design code, and the second file comprises a layout netlist corresponding to the comprehensive netlist; or
The first file comprises a source program file, and the second file comprises a synthesized netlist corresponding to a chip design code; or
The first file comprises a comprehensive netlist corresponding to a chip design code, and the second file comprises a netlist generated after logic test; or
The first file comprises a netlist generated after logic test, and the second file comprises a layout netlist.
14. The method according to claim 11, wherein the first file comprises at least one register unit, and the name information of the at least one register unit in the first file is different from the name information of the corresponding register unit in the second file; and
the acquiring the first file and the second file includes:
obtaining the second file based on the first file.
15. The method of claim 14, wherein determining unit matching information corresponding to the second file and the first file comprises:
acquiring an input corresponding relation and a name corresponding relation aiming at the register unit based on the first file and the second file;
and acquiring unit matching information corresponding to the first file and the second file according to the input corresponding relation and the name corresponding relation.
16. The method of claim 11,
the second file is obtained by processing the first file by a first electronic design automation tool; the first file, the second file, and the cell matching information are simultaneously used for data processing of a second electronic design automation tool, wherein the first electronic design automation tool is different from the second electronic design automation tool.
17. The method of claim 16,
determining that the at least one data unit in the second file corresponds to the at least one first data unit in the first file when it is detected that the first electronic design automation tool changed the at least one first data unit in the first file and generated the at least one data unit stored in the second file.
18. The method of claim 17,
the first file, the second file, and the unit matching information are simultaneously used for data processing of a second electronic design automation tool, including:
the first file and the unit matching information are simultaneously used in a form verification process of a second electronic design automation tool on the second file.
19. The method of any of claims 14-18, wherein determining unit match information corresponding to the second file and the first file comprises:
acquiring an input corresponding relation of the at least one data unit based on the first file and the second file;
and acquiring unit matching information corresponding to the first file and the second file according to the input corresponding relation.
20. A method for identifying name information, comprising:
acquiring first name information of a data unit;
determining name matching information corresponding to the first name information and the second name information when a first electronic design tool changes the first name information of the data unit and generates second name information of the data unit;
sending the name matching information to a second electronic design tool for the second electronic design tool to identify a corresponding relationship between the first name information and the second name information; and
the first name information of the data unit is stored in a first file, the second name information of the data unit is stored in a second file, and the first electronic design tool and the second electronic design tool are different.
21. The method of claim 20, wherein sending the name matching information to a second electronic design tool comprises:
storing name matching information regarding the first name information and the second name information in a name matching file; and
and sending the name matching file to the second electronic design tool.
22. The method of claim 20,
the name matching information comprises the first name information, second name information and an index from the first name information to the second name information; or
The name matching information includes the first name information, second name information, and an index from the second name information to the first name information.
23. The method of claim 20,
the second electronic design tool is used for formal verification of chip design.
24. The method of claim 20,
in the chip design process, the first file is generated before the second file.
25. The method of claim 20,
the first file and the second file are both generated in the chip design process, and the first file is used for generating the second file.
26. A formal verification device, comprising:
a first memory for storing a computer program;
a first processor for executing a computer program stored in the first memory to implement:
acquiring a first file and a second file, wherein the second file is obtained according to the first file;
determining unit matching information corresponding to the first file and the second file, wherein the unit matching information comprises a corresponding relation between a data unit in the first file and a data unit in the second file;
and performing form verification on the second file according to the unit matching information and the first file.
27. The device of claim 26, wherein the first processor is further configured to:
when the name information corresponding to at least one data unit in the second file cannot be identified, determining unit matching information corresponding to the first file and the second file;
when a data unit corresponding to the name information of the at least one data unit in the second file cannot be identified in the first file, determining unit matching information corresponding to the first file and the second file.
28. The apparatus of claim 26,
the first file comprises a comprehensive netlist corresponding to a chip design code, and the second file comprises a layout netlist corresponding to the comprehensive netlist.
29. The device of claim 28, wherein when the first processor obtains the first file and the second file, the first processor is configured to:
acquiring a comprehensive netlist corresponding to a chip design code, wherein the comprehensive netlist comprises a register unit;
and obtaining the layout netlist based on the comprehensive netlist, wherein the name information of the register unit in the comprehensive netlist is different from the name information of the corresponding register unit in the layout netlist.
30. The apparatus of claim 29,
the comprehensive netlist comprises all first register units and first name information corresponding to the first register units;
the layout netlist comprises all second register units and second name information corresponding to the second register units;
and the first register unit in the synthesized netlist corresponds to the second register unit in the layout netlist.
31. The apparatus of claim 29, wherein when the first processor obtains the layout netlist based on the synthesized netlist, the first processor is configured to:
and carrying out layout and wiring processing on the comprehensive netlist by using a preset tool to obtain a layout netlist corresponding to the comprehensive netlist.
32. The device of claim 31, wherein the first processor is further configured to:
detecting whether the formal verification equipment and the preset tool belong to the same supplier or not;
determining that the formal verification device cannot identify the register unit when the formal verification device and the preset tool belong to different suppliers; alternatively, the first and second electrodes may be,
determining that the formal verification device is capable of identifying the register unit when the formal verification device and the preset tool belong to the same vendor.
33. The device of claim 32, wherein the first processor is further configured to:
and after determining that the register unit can be identified by the formal verification equipment, performing formal verification on the layout netlist by using the formal verification equipment and the comprehensive netlist.
34. The apparatus of any of claims 29-33, wherein when the first processor determines unit match information corresponding to the first file and the second file, the first processor is configured to:
acquiring an input corresponding relation aiming at the register unit based on the comprehensive netlist and the layout netlist;
and acquiring unit matching information corresponding to the comprehensive netlist and the layout netlist according to the input corresponding relation.
35. The apparatus of any of claims 29-33, wherein when the first processor determines unit match information corresponding to the first file and the second file, the first processor is configured to:
acquiring an input corresponding relation and a name corresponding relation aiming at the register unit based on the comprehensive netlist and the layout netlist;
and acquiring unit matching information corresponding to the comprehensive netlist and the layout netlist according to the input corresponding relation and the name corresponding relation.
36. An information identifying apparatus, characterized by comprising:
a second memory for storing a computer program;
a second processor for executing the computer program stored in the second memory to implement:
acquiring a first file and a second file, wherein the second file is obtained according to the first file and comprises at least one data unit;
determining unit matching information corresponding to the second file and the first file, wherein the unit matching information comprises a corresponding relation between the at least one data unit in the second file and the data unit in the first file;
and identifying the data unit in the second file by using the unit matching information.
37. The apparatus of claim 36, wherein the second processor is configured to:
when the name information corresponding to at least one data unit in the second file cannot be identified, determining unit matching information corresponding to the first file and the second file; alternatively, the first and second electrodes may be,
when a data unit corresponding to the name information of the at least one data unit in the second file cannot be identified in the first file, determining unit matching information corresponding to the second file and the first file.
38. The apparatus of claim 36,
the first file comprises a comprehensive netlist corresponding to a chip design code, and the second file comprises a layout netlist corresponding to the comprehensive netlist; alternatively, the first and second electrodes may be,
the first file comprises a source program file, and the second file comprises a synthesized netlist corresponding to a chip design code; alternatively, the first and second electrodes may be,
the first file comprises a comprehensive netlist corresponding to a chip design code, and the second file comprises a netlist generated after logic test; alternatively, the first and second electrodes may be,
the first file comprises a netlist generated after logic test, and the second file comprises a layout netlist.
39. The apparatus of claim 36, wherein the first file comprises at least one register unit, and wherein name information of the at least one register unit in the first file is different from name information of a corresponding register unit in the second file; and
when the second processor acquires the first file and the second file, the second processor is configured to:
obtaining the second file based on the first file.
40. The device of claim 39, wherein when the second processor determines that the units corresponding to the second file and the first file match information, the second processor is configured to:
acquiring an input corresponding relation and a name corresponding relation aiming at the register unit based on the first file and the second file;
and acquiring unit matching information corresponding to the first file and the second file according to the input corresponding relation and the name corresponding relation.
41. The apparatus of claim 36,
the second file is obtained by processing the first file by a first electronic design automation tool; the first file, the second file, and the cell matching information are simultaneously used for data processing of a second electronic design automation tool, wherein the first electronic design automation tool is different from the second electronic design automation tool.
42. The apparatus of claim 41,
determining that the at least one data unit in the second file corresponds to the at least one first data unit in the first file when it is detected that the first electronic design automation tool changed the at least one first data unit in the first file and generated the at least one data unit stored in the second file.
43. The apparatus of claim 42,
the first file, the second file, and the unit matching information are simultaneously used for data processing of a second electronic design automation tool, including:
the first file and the unit matching information are simultaneously used in a form verification process of a second electronic design automation tool on the second file.
44. The device of any of claims 39-43, wherein when the second processor determines the unit match information corresponding to the second file and the first file, the second processor is configured to:
acquiring an input corresponding relation of the at least one data unit based on the first file and the second file;
and acquiring unit matching information corresponding to the first file and the second file according to the input corresponding relation.
45. A name information identifying apparatus, characterized by comprising:
a third memory for storing a computer program;
a third processor for executing the computer program stored in the third memory to implement:
acquiring first name information of a data unit;
determining name matching information corresponding to the first name information and the second name information when a first electronic design tool changes the first name information of the data unit and generates second name information of the data unit;
sending the name matching information to a second electronic design tool for the second electronic design tool to identify a corresponding relationship between the first name information and the second name information; and
the first name information of the data unit is stored in a first file, the second name information of the data unit is stored in a second file, and the first electronic design tool and the second electronic design tool are different.
46. The apparatus according to claim 45, wherein when the third processor sends the name matching information to a second electronic design tool, the third processor is configured to:
storing name matching information regarding the first name information and the second name information in a name matching file; and
and sending the name matching file to the second electronic design tool.
47. The apparatus of claim 45,
the name matching information comprises the first name information, second name information and an index from the first name information to the second name information; alternatively, the first and second electrodes may be,
the name matching information includes the first name information, second name information, and an index from the second name information to the first name information.
48. The apparatus of claim 45,
the second electronic design tool is used for formal verification of chip design.
49. The apparatus of claim 45,
in the chip design process, the first file is generated before the second file.
50. The apparatus of claim 45,
the first file and the second file are both generated in the chip design process, and the first file is used for generating the second file.
51. A computer-readable storage medium, characterized in that the storage medium is a computer-readable storage medium in which program instructions for implementing the formal verification method according to any one of claims 1 to 10 are stored.
52. A computer-readable storage medium, characterized in that the storage medium is a computer-readable storage medium in which program instructions for implementing the information identification method according to any one of claims 11 to 19 are stored.
53. A computer-readable storage medium, characterized in that the storage medium is a computer-readable storage medium in which program instructions for implementing the name information identifying method according to any one of claims 20 to 25 are stored.
CN201980051925.XA 2019-12-26 2019-12-26 Format verification method, information identification method, device and storage medium Pending CN112567375A (en)

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