CN117497516A - High-density photoelectric integrated three-dimensional packaging structure and manufacturing method thereof - Google Patents
High-density photoelectric integrated three-dimensional packaging structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN117497516A CN117497516A CN202311459593.3A CN202311459593A CN117497516A CN 117497516 A CN117497516 A CN 117497516A CN 202311459593 A CN202311459593 A CN 202311459593A CN 117497516 A CN117497516 A CN 117497516A
- Authority
- CN
- China
- Prior art keywords
- chip
- rewiring layer
- transimpedance amplifier
- optical
- electrical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 230000003287 optical effect Effects 0.000 claims abstract description 91
- 229910052751 metal Inorganic materials 0.000 claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000006243 chemical reaction Methods 0.000 claims abstract description 24
- 238000000605 extraction Methods 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 82
- 239000010703 silicon Substances 0.000 claims description 82
- 239000000463 material Substances 0.000 claims description 25
- 230000005693 optoelectronics Effects 0.000 claims description 16
- 239000004033 plastic Substances 0.000 claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 238000001465 metallisation Methods 0.000 claims description 11
- 239000005022 packaging material Substances 0.000 claims description 6
- 239000013307 optical fiber Substances 0.000 claims description 5
- 238000007789 sealing Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 21
- 230000005540 biological transmission Effects 0.000 abstract description 19
- 230000010354 integration Effects 0.000 description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 239000011295 pitch Substances 0.000 description 11
- 239000012778 molding material Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000008054 signal transmission Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Light Receiving Elements (AREA)
Abstract
The invention provides a high-density photoelectric integrated three-dimensional packaging structure and a manufacturing method thereof, comprising the following steps: the packaging substrate is sequentially stacked with the optical chip, the rewiring layer and the electric chip on the packaging substrate; the electrical chip comprises a functional surface and is arranged to be in direct contact with the rewiring layer, and the electrical chip is electrically interconnected with the optical chip through a metal line in the rewiring layer so as to allow an output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip through the metal line in the rewiring layer; the electrical connection component is electrically coupled with the transimpedance amplifier chip through a metal circuit in the rewiring layer and is used for realizing signal extraction of the transimpedance amplifier chip, so that the transmission path can be shortened, the loss can be reduced, the transmission rate can be improved, and the packaging height can be reduced. According to the manufacturing method, the redistribution layer is formed on one side of the functional surface of the electric chip, so that the bump process below the electric chip is omitted, and the whole manufacturing process is simple and easy to implement.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a high-density photoelectric integrated three-dimensional packaging structure and a manufacturing method thereof.
Background
With the development of high-rate data communication technology, requirements on transmission rate, bandwidth and high energy efficiency of an optical module are increasingly high. Light has the advantages of small signal attenuation, low energy consumption, high bandwidth and the like, so that silicon optical technology is introduced to increase the I/O bandwidth and reduce the energy consumption to the maximum extent. Among them, how to package optical integrated circuits (PICs) and Electrical Integrated Circuits (EIC) well is the key direction of current research.
Currently, the packaging modes of the photoelectric chip mainly include the following three categories: two-dimensional planar integration, 2.5-dimensional integration, and 3-dimensional stacked integration. As shown in fig. 1, the optical chip (PIC) 110 and the electrical chip (EIC) 130 are directly interconnected by using leads, and two-dimensional integration is implemented by COB packaging technology, which is easy to implement, but the high-speed signal interconnection between the PIC and the EIC is relatively long, the occupied area is relatively large, and the I/O number is severely limited. As shown in fig. 2 to 3, 2.5 and 3-dimensional integration of the optical chip 110 and the electrical chip 130 can achieve higher density package integration, wherein the 3-dimensional integration shown realizes vertical electrical interconnection of the optical chip 110 and the electrical chip 130 through the silicon interposer 120, more chips can be integrated per unit area, and the I/O number is further increased.
For multi-channel optical transceiver module applications, high density interconnection of optical chips to electrical chips is required, and thus a greater number of electrical chips per unit area needs to be accommodated, as well as higher I/O density. The existing three-dimensional photoelectric integration scheme presents the following problems in the application of an optical transceiver module: firstly, the optical chip and the electric chip can realize vertical interconnection through a medium through hole TMV, but the medium through hole TMV is difficult to reach the diameter of a through hole below 50 mu m, the size of a bonding pad on the through hole is overlarge, and the requirements of multichannel signal and high-density interconnection under a limited area are difficult to be met: in the photoelectric integration scheme based on the silicon adapter plate, the optical chip and the electric chip are vertically interconnected through the TSV, and although the TSV can reach the diameter of a through hole below 50 mu m, the silicon adapter plate and the chip are electrically connected by a bump process, namely, bumps or micro bumps are required on the front surface and the back surface of the silicon adapter plate, so that the difficulty in implementation of the process is high and the reliability is high.
It should be noted that the foregoing description of the technical background is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions cannot be considered to be known to the person skilled in the art simply because they are set forth in the background section.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a three-dimensional package structure of high-density optoelectronic integration and a manufacturing method thereof, which are used for solving the problems that the wiring difficulty is increased and the requirements of miniaturization, high integration level, reliability and the like of the optoelectronic module cannot be met when the existing optoelectronic integration adopts the high-density package.
To achieve the above and other related objects, the present invention provides a high-density optoelectronic integrated three-dimensional package structure, comprising:
an optical chip, a rewiring layer and an electrical chip which are sequentially stacked on the packaging substrate;
the optical chip includes a photoelectric conversion element;
the electrical chip includes a functional face and is disposed in direct contact with the rewiring layer with the functional face thereof, the electrical chip including a transimpedance amplifier chip, the electrical chip being electrically interconnected with the optical chip by a metal line in the rewiring layer to allow an output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip via the metal line in the rewiring layer;
and the electrical connection part is arranged at intervals with the electrical chip and is electrically coupled with the transimpedance amplifier chip through a metal circuit in the rewiring layer, so as to lead out signals of the transimpedance amplifier chip, and the electrical connection part and the electrical chip are coated with a plastic sealing layer.
Optionally, the transimpedance amplifier chip is configured to process multichannel signals, and the functional surface of the transimpedance amplifier chip is provided with a bonding pad and has a bonding pad layout with a center-to-center spacing of not more than 85 μm.
Optionally, the pads of the transimpedance amplifier chip are in direct contact on the first major face of the rewiring layer and are electrically interconnected with the photoelectric conversion element by metal lines and solder bumps within the rewiring layer, wherein the photoelectric conversion element comprises a photodetector.
Optionally, the electrical connection component comprises a silicon bridge chip, the silicon bridge chip and the electrical chip being arranged in parallel on the first main face of the rewiring layer.
Optionally, the silicon bridge chip further includes a conductive via and a contact pad bonded to one end of the conductive via, and the contact pad of the silicon bridge chip is directly contacted to the first main surface of the rewiring layer and is electrically coupled to the transimpedance amplifier chip through a metal line in the rewiring layer.
Optionally, the silicon bridge chip is configured with a plurality of conductive through holes allowing the multichannel signals of the transimpedance amplifier chip to be output to the outside in parallel, and the height of the silicon bridge chip is larger than that of the electric chip so that the top of the silicon bridge chip is exposed and electrically connected with the packaging substrate through wire bonding, and the silicon bridge chip is used for realizing signal extraction of the transimpedance amplifier chip.
Optionally, the silicon bridge chip is further configured to supply power to the transimpedance amplifier chip.
Optionally, the optical chip includes a photosensitive region and an optical coupler, and the photosensitive region is optically coupled with an optical fiber inserted from a side of the optical chip through the optical coupler.
The invention also provides a manufacturing method of the high-density photoelectric integrated three-dimensional packaging structure, which comprises the following steps:
providing a model frame, wherein a sacrificial material layer is formed on the model frame;
arranging and fixing an electric chip and an electric connection part at intervals on the sacrificial material layer, wherein the functional surface of the electric chip is fixed towards the sacrificial material layer, and the electric chip comprises a transimpedance amplifier chip;
coating the electric chip and the electric connection part to form a plastic packaging material layer;
removing the sacrificial material layer, stripping the model frame to expose the functional surface of the electric chip, and forming a rewiring layer on one side of the plastic layer, which exposes the functional surface of the electric chip, wherein the rewiring layer comprises a first main surface and a second main surface which are opposite, a dielectric layer and a metal circuit positioned in the dielectric layer, and the functional surface of the electric chip is in direct contact with the first main surface of the rewiring layer;
bonding an optical chip to the second major face of the rewiring layer, the optical chip including a photoelectric conversion element, the optical chip being electrically interconnected with the electrical chip by a metal line within the rewiring layer to allow an output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip via the metal line within the rewiring layer;
and fixing the optical chip on a packaging substrate and forming electrical interconnection with the packaging substrate, and electrically connecting the electrical connection component with the packaging substrate in a wire bonding mode to realize signal extraction of the transimpedance amplifier chip.
Optionally, the method further comprises: before the step of forming the rewiring layer, forming a metallization pattern on one side of the plastic packaging material layer exposing the functional surface of the electric chip based on a graphic mask, wherein the transimpedance amplifier chip comprises a welding pad positioned on the functional surface of the transimpedance amplifier chip, and bonding the metallization pattern with a metal circuit in the rewiring layer by forming the rewiring layer on the metallization pattern.
Optionally, the electrical connection component includes a silicon bridge chip, and the manufacturing method further includes: the electrical chip is electrically connected to the silicon bridge chip through metal lines in the rewiring layer by bringing contact pads at one end of the silicon bridge chip into direct contact with the rewiring layer.
Optionally, the optical chip further includes a bonding pad located on a functional surface thereof, and the manufacturing method further includes: and electrically coupling the bonding pad of the optical chip with the packaging substrate by adopting a wire bonding mode, and receiving external signals.
The invention provides an optical transceiver module, which is provided with the three-dimensional packaging structure of high-density photoelectric integration.
As described above, the high-density photoelectric integrated three-dimensional packaging structure and the manufacturing method thereof have the following beneficial effects:
according to the high-density photoelectric integrated three-dimensional packaging structure provided by the invention, the optical chip, the rewiring layer and the electric chip are stacked in sequence, the optical chip and the electric chip are electrically interconnected by utilizing the rewiring layer, so that the electric chip is directly and electrically contacted with the rewiring layer, a silicon adapter plate and a micro-bump are omitted, a transmission path between a photoelectric conversion element and the electric chip is shortened, the transmission rate is improved, the transmission loss is reduced, the reliability of the photoelectric chip integration is effectively improved, and the packaging height is also reduced; in addition, the silicon bridge chip and the electric chip are arranged on the rewiring layer side by side, and the signal extraction of the electric chip is realized through the silicon bridge chip, so that the external wiring requirement is met, and the packaging density is improved, and therefore, the invention can show the advantage of photoelectric integration in the aspect of high-density interconnection. According to the manufacturing method of the high-density photoelectric integrated three-dimensional packaging structure, the redistribution layer is formed on one side of the functional surface of the electric chip, so that the bump process below the electric chip is omitted, the influence on reliability due to the fine spacing between the electric chip bonding pads such as a transimpedance amplifier chip is avoided, the whole manufacturing process is simple and easy to implement, the packaging height can be reduced, and the packaging cost can be reduced, thereby laying a foundation for large-scale application of a photoelectric system.
Drawings
FIGS. 1-3 are schematic diagrams illustrating exemplary implementations of optoelectronic co-packages; the schematic diagram of the 2-dimensional photoelectric co-packaging structure shown in fig. 1, the schematic diagram of the 2.5-dimensional photoelectric co-packaging structure shown in fig. 2, and the schematic diagram of the 3-dimensional photoelectric co-packaging structure shown in fig. 3.
Fig. 4 is a schematic diagram showing the layout of pads of a transimpedance amplifier chip used in the high-density optoelectronically integrated three-dimensional package structure of the present invention.
Fig. 5 is a schematic structural view showing a high-density integrated three-dimensional package structure according to a comparative example of the present invention.
Fig. 6 is a schematic structural diagram of a high-density integrated three-dimensional package structure according to an embodiment of the present invention.
Fig. 7A shows an SEM image of a silicon bridge chip used in the high-density photo-integrated three-dimensional package structure of the present invention.
Fig. 7B is a graph illustrating exemplary structural parameters of a silicon bridge chip used in the high-density photo-integrated three-dimensional package structure of the present invention.
FIGS. 8A-8B are top views of a high density optoelectronic integrated three-dimensional package structure of the present invention; fig. 8B is a partial view of the structure indicated by P in fig. 8A.
Fig. 9 to 14 are schematic views showing structures obtained at various stages in the method for manufacturing a high-density integrated three-dimensional package structure according to the present invention.
Fig. 15 is a schematic view showing a three-dimensional package structure of high-density optoelectronic integration with a package height in accordance with an embodiment of the present invention.
Fig. 16 is a graph illustrating the results of S-parameter model simulation test of transmission characteristics of TIA chip electrical channels in the high-density optoelectronic integrated three-dimensional package structure of the present invention by differential signals.
Description of element reference numerals
10. 110 optical chip
120. Silicon adapter plate
130. 30 electric chip
1410. Micro bump
1420. Lead wire
1440 BGA
150. Optical fiber
160. Packaging substrate
20. Rewiring layer
220. Silicon adapter plate
310. Transimpedance amplifier chip
320. Silicon bridge chip
33. Plastic packaging material layer
330. Plastic seal layer
340. Heat dissipation structure
420. First lead wire
430. Second lead
440. Solder bump
450. Bonding pad
460. Wire bonding welding disk
510. Model frame
520. Sacrificial material layer
600. Packaging substrate
Detailed Description
Further advantages and effects of the present invention will become apparent to those skilled in the art from the disclosure of the present invention, which is described by the following specific examples.
Please refer to fig. 4 to fig. 16. It should be understood that the structures, proportions, sizes, etc. shown in the drawings are for illustration purposes only and should not be construed as limiting the invention to the extent that it can be practiced, since modifications, changes in the proportions, or otherwise, used in the practice of the invention, are not intended to be critical to the essential characteristics of the invention, but are intended to fall within the spirit and scope of the invention. Also, the terms such as "upper", "lower", "left", "right", "middle" and "a" and the like are used in this specification for convenience of description, but are not intended to limit the scope of the invention, and the relative changes or modifications thereof are considered to be within the scope of the invention without any substantial technical changes.
The optical transceiver module includes an optical transmitter and an optical receiver through which a received optical signal can be converted into an electrical signal that can be processed by an Integrated Circuit (IC) including a transimpedance amplifier (TIA) and a driver chip. With the development of high-rate data communication technology, a larger number of electrical chips per unit area needs to be accommodated, and higher I/O density. Taking the application of a 16-channel optical transceiver module as an example, a suitable transimpedance amplifier chip often has a pad layout with a fine pitch, and a typical layout structure can be seen in fig. 4. The electrical chip is originally electrically interconnected with other chips by using a wire bonding mode, but the wire bonding mode limits the packaging density and the transmission rate, so that the requirement of high-speed electric signal transmission quality between the exchange chip and an optical engine (for realizing the photoelectric conversion function) cannot be met, namely the requirement of high-density interconnection between the electrical chip and the optical chip cannot be met.
As shown in fig. 5, a three-dimensional integrated optoelectric co-package typical structure is shown, in which the optical chip 10 and the electrical chip 30 are stacked on the upper and lower surfaces of the silicon interposer 220, such that the electrical chip 30 is vertically interconnected with the optical chip 10 through the silicon interposer 220, and a rewiring layer is further disposed on the surface of the silicon interposer 220 adjacent to the electrical chip 300 to redistribute the solder joint position of the silicon interposer 220 on one side of the electrical chip. As shown in fig. 5, bumps are disposed on both front and back sides of the silicon interposer, and the silicon interposer is electrically connected to the chips stacked on top of and below the silicon interposer through the bumps, and the bumps need to be landed on the pads of the chips to form electrical contacts, so the bumps generally have smaller dimensions than the pads of the chips, and as the chip dimensions scale down, the pad layout of some chips has a tendency to have reduced pitch and size, and bumps with smaller ball diameters and/or pitches need to be manufactured. As shown in the TIA chip in FIG. 4, the bump is manufactured on the bonding pad of the electrical chip, and according to the size and the space of the bonding pad, the bump with the spherical diameter of 50 μm/the pitch of 85 μm or smaller is adopted, which faces the problems of higher process implementation difficulty, high cost and the like. In addition, since the pads of the electrical chip are distributed around the chip, even if the required bumps are fabricated, underfilling (unrerfill) cannot be performed between the chips, which may face problems such as stress mismatch and reliability. Therefore, the three-dimensional packaging scheme of the photoelectric integration is applied to the multichannel optical transceiver module, and the packaging density is difficult to improve due to the increase of the pin density, and the problems of high implementation difficulty, reliability and the like of the bottom filling process are met.
Therefore, the inventor has long studied and proposed an improved structure of a three-dimensional package structure of high-density photoelectric integration and a manufacturing method thereof.
As shown in fig. 6, an embodiment of the present application provides a high-density optoelectronic integrated three-dimensional package structure, including: a package substrate 600, and an optical chip 10, a rewiring layer 20 and an electrical chip 30 sequentially stacked on the package substrate, the optical chip 10 including a photoelectric conversion element; the electrical chip 30 comprises a functional surface and is arranged to be in direct contact with the rewiring layer 20 with its functional surface, wherein the electrical chip 30 comprises a transimpedance amplifier chip 310, the electrical chip 30 being electrically interconnected with the optical chip 10 by metal lines in the rewiring layer to allow an output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip 310 via the metal lines in the rewiring layer.
Here, in the present invention, the electrical chip and the optical chip respectively have a surface provided with a bonding pad or bonding pad as a functional surface, for example, the transimpedance amplifier chip 310 includes a functional surface and a bonding pad located on the functional surface, and the optical chip 10 includes a functional surface and a bonding pad 450 located on the functional surface.
The rewiring layer 20 is further provided with an electrical connection component, the electrical connection component is arranged at intervals with the electrical chip 30 and is electrically coupled with the transimpedance amplifier chip 310 at least through a metal circuit in the rewiring layer, so as to lead out signals of the transimpedance amplifier chip, and a plastic sealing layer 330 is further arranged to cover the electrical connection component and the electrical chip.
In this embodiment, the transimpedance amplifier chip 310 is configured for multi-channel signal processing, and has a bonding pad layout with a center-to-center spacing of not more than 85 μm and a bonding pad disposed on a functional surface of the transimpedance amplifier chip, and the bonding pad of the transimpedance amplifier chip is directly contacted to the first main surface of the rewiring layer and electrically interconnected with the optical chip 10 through a metal line in the rewiring layer.
Compared with the three-dimensional photoelectric integrated typical structure based on the adapter plate, according to the technical scheme, the electric chip is in direct contact with the rewiring layer, particularly the transimpedance amplifier chip is in direct contact with the rewiring layer and is electrically interconnected with the optical chip through the rewiring layer, so that micro bumps below the electric chip are omitted, the transmission path of high-frequency transmission signals is shortened, transmission loss is reduced, signal attenuation is reduced, underfilling after bump connection and reliability problems caused by the underfilling are avoided, and the packaging height can be reduced.
In one implementation, as shown in fig. 6, the electrical connection component includes a silicon bridge chip 320, where the silicon bridge chip 320 and the plurality of electrical chips 301, 302, 303, 304 are arranged on the first main surface of the rewiring layer in parallel, and the electrical chips include a transimpedance amplifier chip, where a fine pitch pad of the transimpedance amplifier chip fans out an I/O terminal via the rewiring layer, and one end of the silicon bridge chip 320 is electrically contacted to the first main surface of the rewiring layer, so as to realize signal extraction of the electrical chips, thereby not only meeting an external wiring requirement, but also improving a packaging density.
Fig. 7A shows a microscopic image of a silicon bridge chip used in the high-density optoelectronic integrated three-dimensional package structure of the present invention, in which conductive vias (TSVs) are provided vertically through and filled with metal. As an example, the silicon bridge chip 320 includes a conductive via and a contact pad bonded to one end of the conductive via, the contact pad of the silicon bridge chip directly contacts the rewiring layer 20 and is electrically coupled with the transimpedance amplifier chip 310 through a metal line in the rewiring layer, and the silicon bridge chip 320 is electrically coupled with the package substrate 600 through wire bonding to realize signal extraction of the transimpedance amplifier chip 310.
For example, as shown in fig. 8A, a silicon bridge chip 320 is configured with a plurality of conductive vias allowing a multi-channel signal of a transimpedance amplifier chip to be outputted to the outside in parallel, the height of the silicon bridge chip is larger than the height of the electrical chip so that the top of the silicon bridge chip is exposed, and the silicon bridge chip is electrically connected to the package substrate 600 by wire bonding for realizing signal extraction of the transimpedance amplifier chip.
Here, the embodiment of the present invention exemplifies a three-dimensional package structure of high-density optoelectronic integration with the number of transimpedance amplifier chips being 4, but the kind of the electrical chips and the number thereof to which the present invention is applied are not meant to be limited thereto.
As an example, the top of the silicon bridge chip 320 is also provided with a wire bonding location electrically connected to the package substrate 600 by, for example, gold wire leads, and the transimpedance amplifier chip leads the output signal to the wire bonding location of the silicon bridge chip 320 through the lateral channel of the rewiring layer 20.
Further, the silicon bridge chip 320 is further configured to supply power to the transimpedance amplifier chip, and as shown in fig. 8A, a portion of the dc signal between the power signal and the ground of the transimpedance amplifier chip may also be led to the top of the silicon bridge chip 320, and connected to the transimpedance amplifier chip through the conductive via of the silicon bridge chip and the metal line in the rewiring layer.
Fig. 7B provides exemplary structural parameters of a silicon bridge chip used in the high-density optoelectronically integrated three-dimensional package of the present invention, the silicon bridge chip 320 and the electrical chip 30 being in electrical contact with the first major face of the rewiring layer, the silicon bridge chip having a height greater than the electrical chip so that the top of the silicon bridge chip is exposed. The TSV diameter and the pitch of the silicon bridge chip may be adjusted according to the number of channels and the package size, and are not particularly limited herein.
As shown in fig. 8B, compared with the conventional silicon interposer, through the arrangement of the silicon bridge chip, the TSV with smaller size allows the wiring required by the multichannel signal to be correspondingly arranged under the limited area, so that the pitch of the contact PADs (PAD) of the silicon bridge chip is reduced, for example, the pitch of the contact PADs shown in fig. 8B is reduced to 150 μm, thereby improving the working speed of the circuit and simultaneously meeting the wiring requirement of external interconnection.
In a specific example, the top of the electric chip is further provided with a heat dissipation structure 340, the heat dissipation structure 340 can perform top heat dissipation on the electric chip 30 to reduce heat conduction of the electric chip to the optical chip, and the height of the silicon bridge chip is greater than the sum of the heights of the electric chip and the heat dissipation structure.
It will be appreciated by those skilled in the art that the height of the silicon bridge chip may be flexibly determined according to the thickness of the electrical chip covered by the molding layer, so long as the top of the silicon bridge chip is exposed on the premise of ensuring that the periphery of the electrical chip is covered.
In another implementation, the electrical connection component comprises a metal conductive post having one end substantially flush or flush with the surface of the molding layer 330 and the other end in contact with a contact on the first major face of the rewiring layer.
In some embodiments, the optical chip 10 includes a functional surface and a wire bonding pad 460 on the functional surface thereof, and the wire bonding pad 460 is electrically connected to the package substrate 600 by wire bonding for receiving an external signal. In a specific example, the optical chip 10 further includes a photosensitive region and an optical coupler, through which the photosensitive region is optically coupled with the optical fiber 150 inserted from the side of the optical chip.
For example, the optical chip 10 includes photoelectric conversion elements each including a bonding pad on a functional surface thereof, a solder joint or solder layer is formed between the bonding pad and the solder bump 440, the transimpedance amplifier chip receives and processes multichannel signals in parallel via the rewiring layer, and transmits high-speed electrical signals to an external chip and/or system through an electrical connection part.
It should be noted that, although the external interconnection of the package structure is implemented based on the solder ball method, the present invention also covers other methods of implementing the external interconnection including metal bumps, solder bumps, and the like.
In order to verify the advantages of the implementation manner of the invention in terms of package size and transmission quality, the preferred manner of the high-density photoelectric integrated three-dimensional package structure is adopted to sequentially perform package height and transmission loss simulation tests, and the comparison example of the invention is adopted to perform package height tests as a comparison, the obtained package height test results are respectively marked in fig. 6 and 15, the transmission characteristic simulation test of the electrical channel of the transimpedance amplifier chip and the transmission loss result thereof are shown in fig. 16 according to the preferred manner of the invention, wherein the transmission path of the differential signal is transmitted to a wire bonding position along the conductive through hole of the silicon bridge chip along the TIA chip and the metal route in the rewiring layer, the simulation result based on the differential signal shows that the transmission loss of the simulation test result differential signal is less than 0.71dB at 25 GHz. The whole packaging structure can realize high-density photoelectric integration only through a layer of mature bump technology, reduces the packaging height, reduces signal attenuation, and is beneficial to high-speed electric signal transmission in the light receiving module.
The embodiment also provides an optical transceiver module, which has the high-density photoelectric integrated three-dimensional packaging structure with the scheme.
The invention also provides a manufacturing method of the high-density photoelectric integrated three-dimensional packaging structure, and the high-density photoelectric integrated three-dimensional packaging structure is preferably manufactured by adopting the manufacturing method of the embodiment, and can be manufactured by adopting other manufacturing methods.
Hereinafter, a high-density optoelectronic integrated three-dimensional package structure provided by the present invention will be specifically described with reference to fig. 9 to 14, which includes the steps of:
s1: providing a model frame, wherein a sacrificial material layer is formed on the model frame, and the obtained structure is shown in fig. 9;
s2: arranging and fixing an electric chip and an electric connection part at intervals on the sacrificial material layer, wherein the functional surface of the electric chip faces the sacrificial material layer for fixing, the electric chip comprises a transimpedance amplifier chip, and the obtained structure is shown in fig. 10;
s3: coating the electric chip and the electric connection part to form a plastic package material layer, wherein the obtained structure is shown in fig. 11;
s4: removing the sacrificial material layer, stripping the model frame to expose the functional surface of the electric chip, and forming a rewiring layer on one side of the plastic package material layer exposed to the functional surface of the electric chip, wherein the rewiring layer comprises a first main surface and a second main surface which are opposite, a dielectric layer and a metal circuit positioned in the dielectric layer, the functional surface of the electric chip is in direct contact with the first main surface of the rewiring layer, and the obtained structure is shown in fig. 13;
s5: electrically connecting an optical chip to the second major face of the rewiring layer, the optical chip comprising a photoelectric conversion element, the optical chip being electrically interconnected with the electrical chip by a metal line of the rewiring layer to allow an output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip via the metal line of the rewiring layer;
s6: the optical chip is fixed on a packaging substrate and electrically interconnected with the packaging substrate, and the electrical connection component and the packaging substrate are electrically connected in a wire bonding mode to realize signal extraction of the transimpedance amplifier chip, so that the obtained structure is shown in fig. 14.
Based on the technical scheme, a fan-out packaging mode of a Chip-first is adopted, the electric Chip is remolded to the model frame by the functional surface of the electric Chip, then a rewiring layer is manufactured through a bonding pad of the functional surface of the electric Chip after the model frame is peeled off, so that the bonding pad of the electric Chip is directly contacted with the surface of the rewiring layer and is electrically contacted with a metal circuit exposed on the surface of the rewiring layer, the electric Chip and the optical Chip are electrically interconnected through the rewiring layer, a bump technology is not needed, the photoelectric integration requirement under the application scene of multichannel signals can be met, and the packaging density is also improved.
It should be specifically noted that the steps are merely distinguished for convenience of description, and are not limiting to the actual process flow, and in fact, the sequence of the steps may be adjusted or combined, for example, the step S5 and the step S6 may be performed synchronously or sequentially.
As shown in fig. 9, at step S1, the sacrificial material layer 520 includes one of a carrier tape and a thermally induced release material to facilitate peeling of the carrier frame.
In another specific example, a thermally releasable material may be applied onto the mold frame by spin coating, followed by arranging an electrical chip and an electrical connection component including a silicon bridge chip, a metal conductive pillar, a Local Silicon Interconnect (LSI), or the like at a spacing on the mold frame and fixing the two by curing the thermally releasable material at step S2.
As shown in fig. 10, step S2 includes, as an example, disposing and fixing a plurality of transimpedance amplifier chips 3101, 3102, 3103, 3104, which are configurable for multichannel signal processing, and a silicon bridge chip 320 side by side on a sacrificial material layer 520. In this embodiment, the silicon bridge chip 320 includes a conductive via and a contact pad bonded to one end of the conductive via.
As shown in fig. 11, at step S3, as an example, the first main surface of the rewiring layer 20 is integrally molded to form a molding material layer 33 that encapsulates the electrical chip and the electrical connection component, where the molding material layer 33 may integrally encapsulate the electrical chip and the electrical connection component by a method well known to those skilled in the art, and includes, but is not limited to, for example, one of compression molding, transfer molding, liquid sealing molding, vacuum lamination, and spin coating, and the material of the molding material layer 33 includes one of polyimide, silicone, and epoxy.
As an example, step S3 further includes: after forming the molding material layer 33, grinding or chemical mechanical polishing may be applied to the upper surface of the molding material layer 33 to improve the surface flatness of the molding material layer 33, thereby improving the quality of the re-wiring layer to be subsequently manufactured.
Specifically, as shown in fig. 12, step S4 includes: removing the sacrificial material layer 520, and peeling the mold frame 510 to expose the pads of the transimpedance amplifier chip and the contact pads of the silicon bridge chip; a rewiring layer 20 is formed on a side of the molding compound layer where the transimpedance amplifier chip is exposed, so that the bonding pads of the transimpedance amplifier chip and the contact pads of the silicon bridge chip directly contact the surface of the rewiring layer.
As shown in fig. 13, the re-wiring layer 20 includes a dielectric layer 20b and a metal wiring layer 20a located in the dielectric layer, as an example; the material of the dielectric layer 20b comprises one or more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the material of the metal wiring layer 20a includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium. The rewiring layer 20 may be formed by the following steps: forming a dielectric layer; forming a through hole or a groove in the dielectric layer through a Damascus process; the via or recess is filled with a metal material to form a metal wiring layer and a contact plug connecting adjacent metal wiring layers, the metal wiring layer and the contact plug being connected as a metal line, wherein one end of the metal line is exposed at the first main surface of the rewiring layer, such that the electrical chip 30 is electrically interconnected with the optical chip 10 through the metal line in the rewiring layer. The use of the damascene process can form a fine-pitch metal wiring layer, can increase the density of metal lines, thus enabling improved conduction and connection reliability, and the fine-pitch metal wiring layer has a smaller surface roughness than other types of wirings, and can also reduce signal transmission loss of high-speed electrical signals. Four 4-channel transimpedance amplifier chips are disposed side-by-side on a rewiring layer having 5 metal wiring layers in an optical transceiver module application with 16-to-16-emissions. The materials, the number of layers, and the distribution morphology of the dielectric layer and the metal wiring layer may be set according to the specific conditions of the chip, and are not limited herein.
In another specific example, step S4 further includes: before the step of forming the rewiring layer, forming a metallization pattern on the side of the plastic packaging material layer, which is exposed to the functional surface of the electric chip, such as the side exposed to the pad of the transimpedance amplifier chip, by using a lithography technique through electroplating, electroless plating or similar deposition methods based on a pattern mask; next, the remaining etching polymer or residue is removed and an underlying dielectric layer is deposited over the metallization pattern, where the metallization pattern includes bond pads or RDL pads, thereby forming fine pitch contacts. The metallization pattern is bonded to the metal lines within the re-routing layer by forming the re-routing layer 20 over the metallization pattern.
Further, as shown in fig. 13, an opening is further formed on the top dielectric layer of the rewiring layer to form a lower metal layer (UBM) in the opening for bonding an interconnect structure, wherein the interconnect structure includes ball grid array connectors (BGA), solder bumps, solder balls, controlled collapse chip connection (C4) bumps, or similar connectors. In this embodiment, the interconnect structure includes a solder bump 440 and a solder joint or layer formed by soldering with a bond pad 450 of the optical chip.
Specifically, the optical chip 10 includes a functional surface and contact pads located on the functional surface thereof, and step S5 includes: the optical chip 10 is electrically interconnected with the electrical chip 30 through the metal lines of the rewiring layer by bonding between the interconnect structures and the contact pads of the optical chip to allow the output signals of the photoelectric conversion elements to be transmitted to the transimpedance amplifier chip via the metal lines of the rewiring layer.
The step S6 comprises the following steps: the electrical connection members are electrically connected to the package substrate 600 by wire bonding, so that the transimpedance amplifier chip 310 is electrically interconnected to the package substrate 600 by metal lines in the rewiring layer.
As an example, as shown in fig. 14, the silicon bridge chip 320 is electrically connected to the package substrate 600 by wire bonding using the first wire 420.
Further, while or after the optical chip 10 is fixed on the package substrate 600, the optical chip 10 is electrically connected to the package substrate 600 by using the second lead 430 through a wire bonding method, the optical chip includes a functional surface and a wire bonding pad 460 located on the functional surface, and the wire bonding pad 460 of the optical chip is electrically connected to the package substrate 600 through wire bonding for receiving an external signal. In one example, the optical chip 10 is provided with a photoelectric conversion element that also includes bonding pads disposed on its functional surface. For example, the photoelectric conversion element includes a photodetector and a laser, and the photodetector is selected as a passive element.
By way of example, the optical chip 10 further includes a photosensitive region through which the optical fiber 150 inserted from the side of the optical chip is optically coupled and an optical coupler.
Step S6 further includes: the top surface of the molding material layer 33 is thinned by a planarization process, which includes grinding or chemical mechanical polishing, to expose the top surface of the silicon bridge chip and to improve the flatness of the resulting molding layer 330.
As an example, the top of the silicon bridge chip is provided with a wire bonding location, which is exposed from the top surface of the plastic layer 330 at least after the planarization process.
In summary, the present invention provides a three-dimensional package structure of high-density optoelectronic integration and a method for manufacturing the same, in which an optical chip, a rewiring layer and an electrical chip are stacked in order, and the optical chip and the electrical chip are electrically interconnected by using the rewiring layer, so that the electrical chip is directly and electrically contacted with the rewiring layer, a silicon interposer and a micro bump are omitted, the reliability of the optoelectronic chip integration is effectively improved, the transmission path between a photoelectric conversion element and the electrical chip is shortened, the loss is reduced, the transmission rate is increased, and the package height is also reduced. The manufacturing method of the high-density photoelectric integrated three-dimensional packaging structure does not need to realize electrical contact between the chip bonding pads and the interconnection structure through a bump process, avoids the influence on reliability caused by fine spacing between the chip bonding pads of the electric chip such as a transimpedance amplifier chip, has simple and easy whole preparation process, and can reduce the packaging cost, thereby laying a foundation for large-scale application of a photoelectric system. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (13)
1. A high density optoelectronic integrated three-dimensional package structure, comprising:
an optical chip, a rewiring layer and an electrical chip which are sequentially stacked on the packaging substrate;
the optical chip includes a photoelectric conversion element;
the electrical chip includes a functional face and is disposed in direct contact with the rewiring layer with the functional face thereof, the electrical chip including a transimpedance amplifier chip, the electrical chip being electrically interconnected with the optical chip by a metal line in the rewiring layer to allow an output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip via the metal line in the rewiring layer;
and the electrical connection part is arranged at intervals with the electrical chip and is electrically coupled with the transimpedance amplifier chip through a metal circuit in the rewiring layer, so as to lead out signals of the transimpedance amplifier chip, and the electrical connection part and the electrical chip are coated with a plastic sealing layer.
2. The three-dimensional package structure of claim 1, wherein: the transimpedance amplifier chip is configured for processing multichannel signals, and is provided with a bonding pad on a functional surface thereof and has a bonding pad layout with a center-to-center spacing of not more than 85 μm.
3. The three-dimensional package structure of claim 1, wherein: the bond pads of the transimpedance amplifier chip are in direct contact on the first major face of the rewiring layer and are electrically interconnected with the photoelectric conversion element by metal lines and solder bumps within the rewiring layer, wherein the photoelectric conversion element comprises a photodetector.
4. The three-dimensional package structure of claim 1, wherein: the electrical connection component includes a silicon bridge chip, the silicon bridge chip and the electrical chip being juxtaposed on the first major face of the rewiring layer.
5. The three-dimensional package structure of claim 4, wherein: the silicon bridge chip further comprises a conductive through hole and a contact pad connected to one end of the conductive through hole, wherein the contact pad of the silicon bridge chip is directly contacted on the first main surface of the rewiring layer and is electrically coupled with the transimpedance amplifier chip through a metal circuit in the rewiring layer.
6. The three-dimensional package structure of claim 5, wherein: the silicon bridge chip is provided with a plurality of conductive through holes which allow multichannel signals of the transimpedance amplifier chip to be output to the outside in parallel, the height of the silicon bridge chip is larger than that of the electric chip, so that the top of the silicon bridge chip is exposed and electrically connected with the packaging substrate through wire bonding, and the silicon bridge chip is used for realizing signal extraction of the transimpedance amplifier chip.
7. The three-dimensional package structure of claim 1, wherein the silicon bridge chip is further configured to power the transimpedance amplifier chip.
8. The three-dimensional package structure of claim 1, wherein: the optical chip includes a photosensitive region and an optical coupler, and the photosensitive region is optically coupled with an optical fiber inserted from a side of the optical chip through the optical coupler.
9. The manufacturing method of the high-density photoelectric integrated three-dimensional packaging structure is characterized by comprising the following steps of:
providing a model frame, wherein a sacrificial material layer is formed on the model frame;
arranging and fixing an electric chip and an electric connection part at intervals on the sacrificial material layer, wherein the functional surface of the electric chip is fixed towards the sacrificial material layer, and the electric chip comprises a transimpedance amplifier chip;
coating the electric chip and the electric connection part to form a plastic packaging material layer;
removing the sacrificial material layer, stripping the model frame to expose the functional surface of the electric chip, and forming a rewiring layer on one side of the plastic layer, which exposes the functional surface of the electric chip, wherein the rewiring layer comprises a first main surface and a second main surface which are opposite, a dielectric layer and a metal circuit positioned in the dielectric layer, and the functional surface of the electric chip is in direct contact with the first main surface of the rewiring layer;
bonding an optical chip to the second major face of the rewiring layer, the optical chip including a photoelectric conversion element, the optical chip being electrically interconnected with the electrical chip by a metal line within the rewiring layer to allow an output signal of the photoelectric conversion element to be transmitted to the transimpedance amplifier chip via the metal line within the rewiring layer;
and fixing the optical chip on a packaging substrate and forming electrical interconnection with the packaging substrate, and electrically connecting the electrical connection component with the packaging substrate in a wire bonding mode to realize signal extraction of the transimpedance amplifier chip.
10. The method of manufacturing of claim 9, further comprising: before the step of forming the rewiring layer, forming a metallization pattern on one side of the plastic packaging material layer exposing the functional surface of the electric chip based on a graphic mask, wherein the transimpedance amplifier chip comprises a welding pad positioned on the functional surface of the transimpedance amplifier chip, and bonding the metallization pattern with a metal circuit in the rewiring layer by forming the rewiring layer on the metallization pattern.
11. The method of manufacturing according to claim 9 or 10, characterized in that: the electrical connection component comprises a silicon bridge chip, and the manufacturing method further comprises the following steps: the electrical chip is electrically connected to the silicon bridge chip through metal lines in the rewiring layer by bringing contact pads at one end of the silicon bridge chip into direct contact with the rewiring layer.
12. The method of manufacturing according to claim 9, wherein: the optical chip further comprises a bonding pad positioned on the functional surface of the optical chip, and the manufacturing method further comprises the following steps: and electrically coupling the bonding pad of the optical chip with the packaging substrate by adopting a wire bonding mode, and receiving external signals.
13. An optical transceiver module, characterized in that: the optical transceiver module has a high-density optoelectronic integrated three-dimensional package structure as claimed in any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311459593.3A CN117497516A (en) | 2023-11-03 | 2023-11-03 | High-density photoelectric integrated three-dimensional packaging structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311459593.3A CN117497516A (en) | 2023-11-03 | 2023-11-03 | High-density photoelectric integrated three-dimensional packaging structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117497516A true CN117497516A (en) | 2024-02-02 |
Family
ID=89682314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311459593.3A Pending CN117497516A (en) | 2023-11-03 | 2023-11-03 | High-density photoelectric integrated three-dimensional packaging structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117497516A (en) |
-
2023
- 2023-11-03 CN CN202311459593.3A patent/CN117497516A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9748216B2 (en) | Apparatus and method for a component package | |
| US6867501B2 (en) | Semiconductor device and method for manufacturing same | |
| US20180040587A1 (en) | Vertical Memory Module Enabled by Fan-Out Redistribution Layer | |
| CN112133696B (en) | Package and method of forming the same | |
| US11935837B2 (en) | Photonics integrated circuit package | |
| CN112086444A (en) | Semiconductor device with a plurality of semiconductor chips | |
| US11605621B2 (en) | Hybrid integrated circuit package and method | |
| CN110335859B (en) | Multi-chip packaging structure based on TSV and preparation method thereof | |
| US11688725B2 (en) | Semiconductor packages | |
| CN219625758U (en) | High-density photoelectric integrated 2.5-dimensional fan-out type packaging structure | |
| IL294968A (en) | High bandwidth module | |
| CN115148612A (en) | Fan-out type system-in-package structure and manufacturing method | |
| CN117497516A (en) | High-density photoelectric integrated three-dimensional packaging structure and manufacturing method thereof | |
| JP2024516204A (en) | Fan-out module for integrating photonic integrated circuits | |
| CN219831453U (en) | Chip system packaging structure | |
| US11798931B2 (en) | Semiconductor package | |
| US20230377907A1 (en) | Package structure including photonic package having embedded optical glue | |
| US20240077669A1 (en) | Integrated circuit package and method of forming same | |
| US20240105704A1 (en) | 3D Package with Chip-on-Reconstituted Wafer or Reconstituted Wafer-on-Reconstituted Wafer Bonding | |
| WO2022261806A1 (en) | Chip stacking structure and manufacturing method, wafer stacking structure, and electronic device | |
| CN115377085A (en) | Wireless interconnection device and system | |
| TW202401678A (en) | Electronic package and manufacturing method thereof | |
| CN116525558A (en) | Package and method of forming the same | |
| CN116779692A (en) | Semiconductor package and method of forming the same | |
| CN117832187A (en) | Semiconductor package and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |