CN116779692A

CN116779692A - Semiconductor package and method of forming the same

Info

Publication number: CN116779692A
Application number: CN202310587633.6A
Authority: CN
Inventors: 吴俊毅; 余振华
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-05-23
Filing date: 2023-05-23
Publication date: 2023-09-19

Abstract

A method of forming a semiconductor package includes bonding a first wafer to a second wafer, wherein the first wafer includes a plurality of electronic dies and the second wafer includes a plurality of photonic packages; forming a trench between adjacent photonics dies of the plurality of photonics dies of the second wafer after bonding the first wafer; the trench is filled with an optical cement. The first wafer and the second wafer are diced to form a plurality of photonic packages, wherein a photonic package of the plurality of photonic packages includes an electronic die, a photonic die bonded to the electronic die, and an optical glue, wherein the optical glue extends along sidewalls of the photonic package. Embodiments of the present application disclose a semiconductor package and a method of forming the same.

Description

Semiconductor package and method of forming the same

Technical Field

Embodiments of the present application relate to semiconductor packages and methods of forming the same.

Background

Electrical signals and processing are one technique for signal transmission and processing. In recent years, optical signals and processing have been increasingly used, particularly due to the use of optical fibers for signal transmission.

Optical signals and processing may be combined with electrical signals and processing to provide a comprehensive application. For example, optical fibers may be used for long-range signal transmission, while electrical signals may be used for short-range signal transmission, as well as processing and control. Thus, a device integrating the optical element and the electrical element is formed for conversion between optical signals and electrical signals, and processing of the optical signals and electrical signals. Thus, a package may include an optical die (also referred to as a photonics die) that includes an optical device and an electronic die that includes an electronic device.

Disclosure of Invention

According to one embodiment of the present invention, a method of forming a semiconductor package, the method includes: bonding a first wafer to a second wafer, wherein the first wafer comprises a plurality of electronic dies and the second wafer comprises a plurality of photonic dies; forming a trench in the second wafer between adjacent ones of the plurality of photonics dies after bonding the first wafer; filling the grooves with an optical cement; and dicing the first wafer and the second wafer to form a plurality of photonic packages, wherein a photonic package of the plurality of photonic packages includes an electronic die, a photonic die bonded to the electronic die, and the optical glue, wherein the optical glue extends along sidewalls of the photonic package.

According to yet another embodiment of the present invention, a method of forming a semiconductor package, the method includes: attaching a photonic package and a semiconductor die to a carrier, wherein the photonic package comprises an electronic die, a photonic die bonded to the electronic die, and an optical paste embedded in the photonic die, wherein a first sidewall of the optical paste is flush with a sidewall of the electronic die; forming a molding material over the carrier surrounding the photonic package and the semiconductor die, the molding material covering the first side wall of the optical adhesive; forming a redistribution structure over the molding material; and removing portions of the molding material after forming the redistribution structure to expose the first side wall of the optical adhesive.

According to still another embodiment of the present application, a semiconductor package includes: a redistribution structure; a photonic package connected to the first face of the redistribution structure, the photonic package comprising an electronic die, a photonic die bonded to the electronic die, and an optical cement embedded in the photonic die, wherein a first sidewall of the optical cement is flush with a sidewall of the electronic die; a molding material on a first side of the redistribution structure, wherein the molding material partially surrounds the photonic package and exposes the first sidewall of the optical adhesive; a substrate connected to a second opposing face of the redistribution structure; and an underfill material between the substrate and the redistribution structure, wherein the underfill material exposes the first side wall of the optical glue.

Embodiments of the present application disclose a package structure comprising a photonic package with embedded optical cement.

Drawings

Aspects of embodiments of the application are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-6 illustrate cross-sectional views of a photonic package at various stages of fabrication, according to embodiments.

Fig. 7 and 8 illustrate cross-sectional views of a semiconductor package at various stages of manufacture, in accordance with an embodiment.

Fig. 9A, 9B, 9C, 9D, and 9E illustrate various views of a semiconductor package according to an embodiment.

Fig. 10 illustrates a cross-sectional view of a semiconductor package according to another embodiment.

Fig. 11 shows a cross-sectional view of a semiconductor package according to another embodiment.

Fig. 12A, 12B, and 12C illustrate various views of a semiconductor package according to another embodiment.

Fig. 13 shows a cross-sectional view of a semiconductor package according to another embodiment.

Fig. 14 shows a cross-sectional view of a semiconductor package according to another embodiment.

Fig. 15 illustrates a flowchart of a method of forming a semiconductor package according to an embodiment.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of embodiments of the invention. Specific examples of components and arrangements are described below to simplify the present embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact.

In addition, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Throughout the specification, unless indicated otherwise, the same or similar reference numerals in different figures refer to the same or similar elements formed from the same or similar materials by the same or similar methods of formation.

In some embodiments, the photonic package is formed by bonding the photonic package to the electronic die and replacing a portion of the dielectric layer of the photonic package with an optical paste. The edge coupler of the photonics die is proximate to the optical cement. The outer side wall of the optical glue is flush with the side wall of the photonic package and exposed, which allows the optical fiber to be easily attached to the outer side wall of the optical glue to achieve optical coupling with the edge coupler. In some embodiments, the photonic package is embedded in a molding material with another die and a redistribution structure is formed on the molding material. A cutting process is then performed to remove a portion of the molding material, exposing the outer sidewalls of the optical cement. Next, the redistribution structure is connected to the substrate, and an underfill material is formed between the redistribution structure and the substrate. The substrate has a trench formed at an uppermost dielectric layer facing the redistribution structure. The groove is adjacent to the optical cement and part of the filling material flows into the groove, which ensures that the filling material does not cover the outer side wall of the optical cement. The outer side walls of the optical cement are exposed to allow optical coupling between the side-mounted optical element (e.g., optical fiber) and the edge coupler. The disclosed structure enables co-packaged optical (CPO) integration and high bandwidth and ultra low power consumption by integrating the photonic package and the electronic die in the same package.

Fig. 1-6 illustrate cross-sectional views of a photonic package 100 at various stages of fabrication, according to embodiments.

Referring to fig. 1, a first side of a wafer 10 (e.g., the underside of wafer 10 in fig. 1) is connected (e.g., bonded) to the front side of wafer 20. Wafer 10 includes a plurality of photonic packages 120 separated by dicing regions. The location of the cut area of the wafer 10 is indicated by line 11 in fig. 1. Wafer 20 includes a plurality of electronic die 110 separated by dicing regions. The location of the dicing area of the wafer 20 is indicated by line 21 in fig. 1. Note that for simplicity, not all details of photonics die 120 and electronics die 110 are shown in all figures. Details of photonic package 120 and electronic die 110 are illustrated and discussed below with respect to fig. 6.

Wafer 10 is bonded to wafer 20 by a suitable bonding process, such as by a dielectric-to-dielectric bond and/or a metal-to-metal bond (e.g., direct bond, fusion bond, oxide-to-oxide bond, hybrid bond, or the like). In such embodiments, covalent bonds may be formed between oxide layers, such as the topmost dielectric layer on the first side of wafer 10 and the topmost dielectric layer on the front side of wafer 20. During bonding, metal bonding may also occur between die connectors 109 of electronic die 110 and die connectors 127 of photonics die 120. In the example of fig. 1, the diced regions of wafer 10 are aligned with corresponding diced regions of wafer 20 after the wafer bonding process.

Next, in fig. 2, conductive bumps 145 are formed on a second side of wafer 10 (e.g., the upper side of wafer 10 in fig. 1 and 2) to electrically couple to conductive features (e.g., vias, or conductive pads) of photonics die 120. The conductive bumps 145, after forming the individual photonic packages 100 in a subsequent dicing process, serve as external connectors for the photonic packages 100. Conductive bumps 145 may be of any suitable external contact type, such as Ball Grid Array (BGA), micro bumps, copper pillars, copper layers, nickel layers, lead-free (LF) layers, electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layers, cu/LF layers, sn/Ag layers, sn/Pb, combinations thereof, or the like.

Next, in fig. 3, trenches 13 (e.g., openings) are formed in the wafer 10 between adjacent photonic packages 120. For example, the trenches 13 may be formed along the dicing area of the wafer 10. Trenches 13 may extend through wafer 10 and expose underlying wafer 20. In the example of fig. 3, the bottom of the trench 13 is level with the lower surface of the wafer 10. In some embodiments, the bottom of the trench 13 may be formed slightly higher or lower than the lower surface of the wafer 10.

The trenches 13 may be formed using any suitable method, such as etching (e.g., anisotropic etching), blade cutting, laser cutting, or the like. In the illustrated embodiment, each photonics die 120 has a corresponding trench 13 along a sidewall (e.g., the right side sidewall in fig. 3). The trench 13 is formed in a region of the photonics die 120 where no functional circuitry is present, such that the trench 13 does not affect the functionality of the photonics die 120.

Next, in fig. 4, an optical paste 147 is formed in the groove 13. The optical glue 147 may fill or overfill the trench 13. In some embodiments, the optical glue 147 is transparent to light in a particular wavelength range that is used to carry the optical signals processed by the photonic package 120.

Next, in fig. 5, a dicing process is performed along the dicing areas of the wafers 10 and 20 to produce a plurality of individual (e.g., independent) photonic packages 100, wherein each photonic package 100 includes a photonic die 120 that is connected (e.g., bonded) to an electronic die 110. The cutting process may be performed, for example, using a blade, or a laser cutting tool. The dicing is to cut through or along the optical glue 147 such that after the dicing process, the photonic packages 120 in each photonic package 100 have the optical glue 147 embedded into (e.g., a dielectric layer of) the photonic packages 120. Due to the straight cut path of the dicing process, in some embodiments, the outer side wall 147S of the optical glue 147 in the photonic package 100 is flush (e.g., vertically aligned) with the corresponding side wall of the electronic die 110. Note that the outer sidewall 147S and the corresponding sidewall of the electronic die 110 include (portions of) the sidewall (e.g., the right sidewall in fig. 5) of the photonic package 100. Details of photonic package 100 are shown in fig. 6, including photonic die 120, electronic die 110, and optical cement 147.

Referring now to fig. 6, details of photonic package 100 are shown. Note that the photonic package 100 in fig. 6 corresponds to the photonic package 100 in fig. 5, but is flipped upside down. In the example of fig. 6, photonic package 100 includes an electronic die 110 connected (e.g., bonded) to photonic die 120, with optical cement 147 embedded in photonic die 120 and disposed along sidewalls of photonic package 100.

Electronic die 110 may be, for example, a semiconductor device, die, or chip that communicates with photonic package 120 using electrical signals. In the illustrated embodiment, electronic die 110 does not receive, transmit, or process optical signals. In the discussion herein, the term "electronic die" is used to distinguish "photonics die" (e.g., 120), which refers to a die that can receive, transmit, or process optical signals, such as converting optical signals to electrical signals, or vice versa. In addition to optical signals, the photonic package 120 may also transmit, receive, or process electrical signals. One electronic die 110 is shown in fig. 6, but in other embodiments, photonic package 100 may include two or more electronic dies 110. In some cases, multiple electronic dies 110 may be incorporated into photonic package 100 to reduce process costs.

In some embodiments, the electronic die 110 includes a substrate 101 (e.g., a semiconductor substrate such as silicon or the like). Electronic components, such as transistors, diodes, capacitors, resistors, etc., may be formed in the substrate 101 and/or on the substrate 101 and may be interconnected by interconnect structures 106 formed, for example, of metallization patterns (e.g., conductive lines 105 and vias 107) in one or more dielectric layers 103 on the substrate 101 to form an integrated circuit. The electronic die 110 further includes pads (not shown), such as aluminum pads, to which external connections are made. These pads are located on the active side (or front side) of the electronic die 110. One or more passivation layers are formed on the front side of the electronic die 110 and portions of the pads. Die connectors 109, such as conductive pillars (e.g., comprising a metal such as copper) are formed to extend through the passivation layer and are mechanically and electrically coupled to corresponding pads. Die attach 109 is electrically coupled to an integrated circuit of electronic die 110.

Note that in the example of fig. 6, portions of dielectric layer 103 of electronic die 110, i.e., where there are no functional circuits, are replaced with dielectric material 108. In some embodiments, the dielectric material 108 may be a gap fill material, which may include silicon oxide, silicon nitride, a polymer, or the like, or a combination thereof. In some embodiments, dielectric material 108 may be a material (e.g., silicon oxide) that is substantially transparent to light at wavelengths suitable for transmitting optical signals or optical power between the optical element (e.g., grating coupler) of photonics die 120 and the vertically mounted optical fiber (e.g., see 185 in fig. 13).

Electronic die 110 may include an integrated circuit for interfacing with photonic elements 135 (e.g., photodetectors and/or modulators) of photonic die 120. Electronic die 110 may include circuitry for controlling the operation of photonic element 135. For example, the electronic die 110 may include a controller, a driver, a transimpedance amplifier, or the like, or a combination thereof. In some embodiments, electronic die 110 may also include a Central Processing Unit (CPU). In some embodiments, electronic die 110 includes circuitry for processing electrical signals received from photonic element 135 including a photodetector. In some embodiments, electronic die 110 may control the high frequency signal of photonic element 135 based on an electrical signal (digital or analog) received from another device or die. In some embodiments, electronic die 110 may be an Electronic Integrated Circuit (EIC) or the like, providing serializer/deserializer (SerDes) functionality. In this manner, electronic die 110 may be used as part of an I/O interface between optical and electrical signals within photonic package 100. In some embodiments, the photonic package 100 described herein may be considered a system-on-a-die (SoC) or a system-integrated-circuit (SoIC) device.

Still referring to fig. 6, photonic package 120 includes one or more dielectric layers 131, conductive features (e.g., conductive lines 143 and vias 141) formed in dielectric layers 131, and various photonic devices formed in dielectric layers 131, such as waveguides 133, photonic elements 135, nitride waveguides 137 (e.g., 137A, 137B, and 137C), edge couplers 139, or the like. In addition, the photonic package 120 includes a redistribution structure 129 on the dielectric layer 131, and conductive bumps 145 under the dielectric layer 131.

In some embodiments, waveguide 133 is a silicon waveguide formed by patterning a silicon layer. The waveguide 133 or waveguides 133 may be patterned from a silicon layer. If a plurality of waveguides 133 are formed, the plurality of waveguides 133 may be individual waveguides 133 or may be connected in a continuous structure. In some embodiments, one or more waveguides 133 form a continuous loop.

Photonic element 135 may be integrated with waveguide 133 and may be formed with waveguide 133. The photonic element 135 may be optically coupled to the waveguide 133 to interact with optical signals within the waveguide 133. The photonic element 135 may include, for example, a photonic device such as a photodetector and/or modulator. For example, a photodetector may be optically coupled to the waveguide 133 to detect an optical signal within the waveguide 133 and generate an electrical signal corresponding to the optical signal. The modulator may be optically coupled to the waveguide 133 to receive the electrical signal and generate a corresponding optical signal within the waveguide 133 by modulating the optical power within the waveguide 133. In this manner, photonic element 135 facilitates input/output (I/O) of optical signals within waveguide 133. In other embodiments, photonic element 135 may include other active or passive elements, such as laser diodes, optical signal splitters, or other types of photonic structures or devices. The optical power may be provided to the waveguide 133 by, for example, an optical fiber (see, e.g., 185 in fig. 9A) coupled to an external light source. Contacts 136 (e.g., copper vias) are formed to electrically couple photonic element 135 with redistribution structure 129 of photonic die 120.

Although not shown, one or more grating couplers may be integrated with the waveguide 133 and may be formed with the waveguide 133. A grating coupler is a photonic structure that allows optical signals and/or optical power to be transmitted between the waveguide 133 and a photonic component, such as a vertically mounted optical fiber (see, e.g., optical fiber 185 in fig. 13) or a waveguide of another photonic system.

Fig. 6 further illustrates a plurality of nitride waveguides 137 (e.g., 137A, 137B, and 137C) formed in different layers of the dielectric layer 131. The nitride waveguide 137 may be formed by patterning a silicon nitride layer. The nitride waveguide 137 or waveguides 137 may be formed by patterning a silicon nitride layer. If a plurality of nitride waveguides 137 are formed, the plurality of nitride waveguides 137 may be individual nitride waveguides 137 or may be connected in a single continuous structure. In some embodiments, one or more nitride waveguides 137 form a continuous loop. In some embodiments, nitride waveguides 137 may include photonic structures, such as grating couplers, edge couplers 139, or couplers (e.g., mode converters), that allow optical signals to be transmitted between two nitride waveguides 137 and/or between nitride waveguides 137 and waveguide 133. In the example of fig. 6, nitride waveguide 137A includes edge coupler 139 adjacent to the side wall of photonics die 120 facing optical glue 147. The edge coupler 139 allows optical signals and/or optical power to be transmitted between the nitride waveguide 137A and an external photonic element (e.g., see optical fiber 185 in fig. 9A) mounted horizontally on the side wall of the photonic package 100. In the discussion herein, the waveguide 133 (e.g., a silicon waveguide) and the nitride waveguide 137 (e.g., a silicon nitride waveguide) may be collectively referred to as the waveguides 133/137.

The optical cement 147 embedded in the photonics die 120 has better transparency (e.g., less optical loss) to optical signals than the dielectric layers 131/121 of the photonics die 120, thus facilitating optical communication between the edge coupler 139 and, for example, a horizontally mounted optical fiber (e.g., see optical fiber 185 in fig. 9A). In the example of fig. 6, the optical cement 147 protrudes from the lower surface of the dielectric layer 131. The surface 147T of the optical cement 147 has a curved shape (e.g., convex shape), which can be formed by overfilling the grooves 13 with the optical cement 147.

Light may be optically coupled to each other between adjacent waveguides (e.g., 133, 137A, 137B, 137C) when the horizontal distance between adjacent waveguides (e.g., 133, 137A, 137B, 137C) is small, for example, when there is lateral overlap, and when the vertical distance between adjacent waveguides (e.g., 133, 137A, 137B, 137C) is small. Thus, light in nitride waveguide 137A may be optically coupled to overlying waveguide 133 through nitride waveguides 137B and 137C, thereby forming a so-called "optical channel" (a vertical optical coupling path similar to the vertical electrical coupling path provided by a via). Thus, an optical signal from a horizontally mounted optical fiber (e.g., the outer sidewall of optical glue 147 deposited alongside edge coupler 139) can be received by edge coupler 139 and then vertically pass through the "optical channel" to photonic element 135 (e.g., photodetector/modulator) embedded in waveguide 133. Photonic element 135 performs conversion between optical signals and electrical signals, which enables electronic die 110 to process electrical signals converted from optical signals.

Fig. 6 further illustrates the redistribution structure 129 of photonics die 120. The redistribution structure 129 includes one or more dielectric layers 121 and conductive features (e.g., conductive lines 123 and vias 125) formed in the dielectric layers 121. A die connector 127 (e.g., copper pillar, copper pad, or the like) of the photonic package 120 is formed on an upper surface of the photonic package 120 and is electrically coupled with the conductive features of the redistribution structure 129. In some embodiments, dielectric layers 121 and 131 are formed of a dielectric material (e.g., silicon oxide) that is substantially transparent to light of a wavelength suitable for transmitting optical signals. Note that the types of elements, the number of elements, the arrangement/configuration of elements illustrated in fig. 6 are merely non-limiting examples, other types/numbers of elements, and other arrangements/configurations of elements are possible and are fully intended to be included within the scope of embodiments of the present disclosure.

Fig. 7 and 8 illustrate cross-sectional views of semiconductor package 150 at various stages of fabrication, according to an embodiment.

In fig. 7, two photonic packages 100 and an electronic die 153 are attached to a carrier 151. The carrier 151 may be, for example, a wafer (e.g., a silicon wafer), a panel, a glass substrate, a ceramic substrate, or the like. The photonic package 100 and the electronic die 153 may be attached to the carrier 151 using, for example, an adhesive or release layer (not shown). The electronic die 153 may be, for example, a CPU, an Application Specific Integrated Circuit (ASIC), a High Bandwidth Memory (HBM) die, or the like. The electronic die 153 may include a substrate 154, electronic components formed in and/or on the substrate 154, and interconnect structures connecting the electronic components to form a die functional circuit. Die connections 155 of electronic die 153 provide electrical connections to electronic die 153. The details are similar to those of the electronic die 110 and are therefore not repeated. Note that the positioning of the photonic packages 100 is such that, for each photonic package 100, the optical glue 147 is located on the outer side wall of the photonic package 100 (e.g., not facing the electronic die 153) in order to facilitate coupling of the optical fibers to the optical glue 147 in subsequent processing.

Next, a molding material 157 is formed on the carrier 151, around the photonic package 100 and the electronic die 153. The molding material 157 covers the outer sidewalls of the optical glue 147 in the photonic package 100. The molding material 157 may be cured by a curing process. After the molding material 157 is formed, a planarization process, such as Chemical Mechanical Planarization (CMP), is performed to achieve a coplanar upper surface between the photonic package 100, the electronic die 153, and the molding material 157.

Next, a redistribution structure 160 is formed over the molding material 157 and electrically coupled with the photonic package 100 and the electronic die 153. In some embodiments, the redistribution structure 160 includes one or more dielectric layers 161 and one or more conductive features (e.g., conductive lines 163 and vias 165) formed in the dielectric layers 161. In some embodiments, one or more dielectric layers 161 are formed of a polymer, such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, dielectric layer 161 is formed of a nitride, such as silicon nitride; oxides such as silica, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), or the like; or the like. The one or more dielectric layers 161 may be formed by any acceptable deposition process, such as spin-on, chemical Vapor Deposition (CVD), lamination, and the like, or combinations thereof. The conductive members 163/165 may be formed of a suitable conductive material such as copper, titanium, tungsten, aluminum, or the like.

In some embodiments, the redistribution structure 160 is formed by: a dielectric layer 161 is formed on the molding material 157, an opening is formed on the dielectric layer 161 to expose the underlying conductive member, a seed layer is formed on the dielectric layer 161 and at the opening, a photoresist having a design pattern is formed on the seed layer, a conductive material in the design pattern and on the seed layer is plated (e.g., electroplated or electroless plated), and portions of the photoresist and the seed layer where the conductive material is not formed are removed. The above process may be repeated a number of times until a target number of dielectric layers 161 and conductive features 165/163 are formed. Other ways of forming the redistribution structure 160 are possible and are fully intended to be included within the scope of embodiments of the present disclosure.

Next, conductive bumps 167 are formed on and electrically coupled with the redistribution structure 160. The conductive bumps 167 may be of any suitable external contact type, such as Ball Grid Array (BGA), micro bumps, copper pillars, copper layers, nickel layers, lead-free (LF) layers, electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layers, cu/LF layers, sn/Ag layers, sn/Pb, combinations thereof, or the like.

As will be readily appreciated by those skilled in the art, a plurality of (e.g., identical) semiconductor packages 150 may be formed simultaneously (e.g., in the same processing step) on carrier 151. These semiconductor packages 150 will be separated by a subsequent dicing process to form individual, stand-alone semiconductor packages 150.

Next, in fig. 8, the carrier 151 is removed by a carrier de-bonding process. The structure of fig. 7 is inverted and the conductive bumps 167 are connected to a dicing tape (not shown). Next, a dicing process is performed along lines 148 to create a plurality of individual (e.g., freestanding) semiconductor packages 150, as shown in fig. 8.

The cutting process may be performed using a blade, or a laser cutting tool, as examples. The cutting is performed to cut or cut along the optical cement 147 such that after the cutting process, a portion of the molding material 157 covering the outer side wall 147S of the optical cement 147 is removed and the outer side wall 147S of the optical cement 147 is exposed as shown in fig. 8.

Fig. 9A, 9B, 9C, 9D, and 9E illustrate various views (e.g., cross-sectional view, plan view) of a semiconductor package 200 according to an embodiment. As shown in fig. 9A, the semiconductor package 200 is formed by connecting (e.g., bonding) the semiconductor package 150 of fig. 8 to the substrate 170. Next, an underfill material 189 is formed to fill the gap between the substrate 170 and the semiconductor package 150. Fig. 9B is an enlarged view of area 183 of fig. 9A, wherein further details are shown.

A substrate 170, which may be a Printed Circuit Board (PCB), includes a dielectric core 171 formed of a dielectric material, such as, in some embodiments, a prepreg, epoxy, silica filler, a flavor build-up film (ABF), polyimide, molding compound, or the like. In some embodiments, dielectric core 171 comprises Bismaleimide Triazine (BT) resin, FR-4 (a composite material consisting of woven fiberglass cloth and epoxy cement with flame retardancy), ceramic, glass, plastic, tape, film, or other support material. A via 173 is formed extending through the dielectric core 171. In some embodiments, the via 173 is formed by drilling a through-hole in the dielectric core 171 and forming (e.g., plating) a conductive material (e.g., copper) along the sidewalls of the through-hole. After the conductive material is formed along the sidewalls of the via, the remainder of the via may be filled with a dielectric material 172, as shown in the example of fig. 9A.

Referring to fig. 9A and 9B, conductive features, such as conductive lines 175A, vias 175B, and conductive pads 174 (not labeled in fig. 9A, but labeled in fig. 9B), are formed on opposite sides of the dielectric core 171 as redistribution layers that redistribute electrical signals from a first location of the substrate 170 to a second location of the substrate 170. The conductive features are formed in a plurality of dielectric layers 177, which may be formed of a suitable dielectric material, such as ABF or prepreg. Fig. 9A further illustrates an uppermost dielectric layer 179 and a lowermost dielectric layer 179 of the substrate 170. The uppermost dielectric layer 179 and the lowermost dielectric layer 179 may be formed of, for example, a solder resist. The conductive pads 174 of the substrate 170 are exposed through openings in the uppermost/lowermost dielectric layer 179. In some embodiments, the conductive bumps 167 of the semiconductor package 150 are aligned with corresponding conductive pads 174 (see fig. 9B) of the substrate 170, and a reflow process is performed to bond the conductive bumps 167 with the respective conductive pads 174 through the solder regions 176. As shown in fig. 9B, during the reflow process, the solder regions 176 completely fill these openings. Note that unlike the trench 191 (into which the filler material 189 flows) discussed below, no filler material 189 flows into these openings (because these openings are filled by the solder regions 176).

As shown in fig. 9A, an optical fiber 185 is attached to the outer sidewall of the optical glue 147 in the photonic package 100 and optically couples with an edge coupler 139 (see fig. 9B) of the photonic package 100 to support optical communication between the photonic package 100 and external devices. Fig. 9A further illustrates a ring 181 attached to the upper surface of the substrate 170 around the semiconductor package 150 using, for example, an adhesive (not shown). The ring 181 may be formed of a rigid material, such as glass, metal, or the like, and may be used to provide structural support and improve the planarity of the substrate 170. External connections 178, such as solder balls, are formed on the lower surface of the substrate 170.

Fig. 9B is an enlarged view of area 183 of fig. 9A. As shown in fig. 9B, the optical fiber 185 is horizontally mounted and connected to the outer side wall 147S of the optical cement 147 by, for example, an optical cement 187. Optical cement 187 may or may not be the same material as optical cement 147. In some embodiments, the height H1 of the optical adhesive 147 is between about 1 micron and about 787 microns, and the thickness W1 of the optical adhesive 147 is greater than 0 microns and less than about 5000 microns.

In fig. 9B, the surface 147T of the optical cement is planar and is flat with the lower surface of the molding material 157. This planar surface 147T may be formed by a CMP process performed after molding material 157 in fig. 7. For example, if surface 147T of optical glue 147 in fig. 6 protrudes further than conductive bumps 145 from the lower surface of photonics die 120, the CMP process performed on molding material 157 in fig. 7 also removes portions of optical glue 147 to form planar surface 147T in fig. 9B. However, if the surface 147T of the optical glue 147 in fig. 6 is closer to the lower surface of the photonic package 120 than the lower surface of the conductive bump 145 in fig. 6, the CMP process performed on the molding material 157 in fig. 7 may not reach the optical glue 147, and thus, the surface 147T of the optical glue 147 may remain in the shape of fig. 6 in the final product (see fig. 10) or may remain in another shape (see fig. 11) after the molding material 157 reshapes the surface 147T.

Note that in fig. 9B, a trench 191 is formed in the uppermost dielectric layer 179 (e.g., solder resist layer) at a position close to the optical paste 147. In some embodiments, the width W2 of the groove 191 is between about 5 microns and about 100 microns, and the depth H2 of the groove 191 is between about 10 microns and about 30 microns. Fig. 9C and 9D further illustrate the location of the groove 191 relative to the photonic package 100, optical glue 147, and edge coupler 139, the details of which will be discussed below.

As shown in fig. 9B, due to the trench 191, the underfill material 189 flows into the trench 191, thereby lowering the height H3 of the rounded corners of the underfill material 189, as measured between the upper surface of the uppermost dielectric layer 179 of the substrate 170 and the uppermost surface of the rounded corners of the underfill material 189 that is located below (e.g., directly below) the optical glue 147. As an example, the rounded corners of the underfill 189 may have an H3 greater than 0 microns and less than about 100 microns. In fig. 9B, rounded portions of the filler material 189 under the optical glue 147 cover (e.g., contact and follow) the lower sidewalls of the redistribution structure 160 and expose the upper sidewalls of the redistribution structure 160. Thus, the outer side wall 147S of the optical glue 147 is fully exposed (e.g., absent) to the underfill material 189, which ensures that the outer side wall 147S of the optical glue 147 is unobstructed, facilitating connection of the optical fibers 185. In some embodiments, the optical fiber 185 is attached to the outer sidewall 147S at a location such that the optical fiber 185 is directed toward the edge coupler 139 to achieve efficient optical coupling.

Fig. 9C is a top view of the semiconductor package 200. For simplicity, not all components of semiconductor package 200 are illustrated. Fig. 9C shows molding material 157 in photonic package 100, electronic die 153, and semiconductor package 150. Fig. 9C also shows rounded corners of the underfill material 189 around the sidewalls of the semiconductor package 150, the uppermost dielectric layer 179 of the substrate 170, and the ring 181 around the semiconductor package 150. Fig. 9C further illustrates edge couplers 139 of photonic package 100, shown in phantom, as they are not visible in a top view. In addition, the trenches 191 in the uppermost dielectric layer 179 are also shown in phantom, as they may be covered by the underfill material 189. To avoid clutter, fig. 9C does not show the optical glue 147. Fig. 9D shows an enlarged view of the portion of fig. 9C, further showing optical cement 147 in photonic package 100 in phantom. Accordingly, fig. 9C (or fig. 9D), in the case where the edge coupler 139, the groove 191, and the optical paste 147 are shown, may also be referred to as a plan view of the semiconductor package 200.

As shown in fig. 9C, the groove 191 is formed beside the edge coupler 139. In the top view of fig. 9C, the central axis 193 of the edge coupler 139 (e.g., the longitudinal axis of the edge coupler 139/nitride waveguide 137) intersects (e.g., bisects) the trench 191. In the exemplary embodiment, grooves 191 are symmetrically disposed about central axis 193. The trench 191 is spaced apart from the right side wall of the photonic package 100 (also the side wall of the semiconductor package 150). FIG. 9C shows two lines A-A and B-B, where line A-A coincides with the central axis 193 of the edge coupler 139 and line B-B is parallel to line A-A but does not intersect the groove 191. Fig. 9B is a sectional view taken along line A-A, and fig. 9E is a sectional view taken along line B-B.

Referring now to fig. 9D, an enlarged view of a portion of fig. 9C is shown. Note that in fig. 9D, the optical glue 147 in the photonic package 100 is shown in phantom. As shown in fig. 9D, the outer sidewall of the optical glue 147 overlaps (is flush with) the sidewall of the photonic package 100. In the example of fig. 9D, the central axis 193 of the edge coupler 130 intersects both the optical glue 147 and the groove 191 (e.g., bisects). In some embodiments, the vertical offset D1 between the central axis 193 and the low sidewall of the groove 191 in fig. 9D is between about 100 microns and about 5 millimeters. The rounded corners of the underfill material 189 may have a width D3 between about 20 microns and about 5 millimeters. In some embodiments, the horizontal offset D2 between the central axis 195 of the groove 191 (e.g., the longitudinal axis of the groove 191 in fig. 9D) and the corresponding sidewall of the photonic package 100 facing the groove 191 is greater than 0 microns and less than about 2 millimeters.

Fig. 9E is a cross-sectional view of the semiconductor package 200 along line B-B in fig. 9C. The trench 191 in the uppermost dielectric layer 179 of the substrate 170 is not in the cross-sectional view of fig. 9E. Note that since the trench 191 is not formed in the portion of the topmost dielectric layer 179 shown in fig. 9E, the rounded corners of the underfill material 189 shown in fig. 9E (which are disposed outside the trench 191) extend along the sidewalls of the redistribution structure 160 to a higher height than the rounded corners of the underfill material 189 shown in fig. 9B (which extend within the trench 191). For example, the rounded corners of the underfill material 189 in fig. 9E may completely cover the sidewalls of the redistribution structure 160, as shown in fig. 9E, or may even cover the lower sidewalls of the photonics die 120, as shown by the dashed line 189' in fig. 9E. In other words, if the groove 191 is not present, the rounded corners of the underfill material 189 of fig. 9B may cover at least a portion of the outer sidewall of the optical glue 147, thereby impeding the connection of the optical fibers 185.

Fig. 10 shows a cross-sectional view of a portion of a semiconductor package 200A according to another embodiment. The semiconductor package 200A is similar to the semiconductor package 200 in fig. 9B, but has a different shape for the surface 147T of the optical cement 147. In fig. 10, a surface 147T of the optical cement 147 is recessed from the lower surface of the molding material 157 and is a curved (e.g., convex) surface. As described above, if the CMP process of the molding material 157 does not reach the optical cement 147, the shape of the surface 147T may retain the original shape in fig. 6.

Fig. 11 shows a cross-sectional view of a portion of a semiconductor package 200B according to another embodiment. The semiconductor package 200B is similar to the semiconductor package 200 in fig. 9B, but has a different shape for the surface 147T of the optical cement 147. In fig. 11, a surface 147T of the optical cement 147 is recessed from the lower surface of the molding material 157 and is a curved (e.g., recessed) surface. The concave shape of the surface 147T may be caused by the formation of the molding material 157 and the thermal energy transferred to the optical cement 147 during the molding material 157 formation process, which molds or remodelles the surface 147T of the optical cement 147. The CMP process of the molding material 157 does not reach the optical cement 147, and thus, the flat surface 147T shown in fig. 9B is not generated.

Fig. 12A, 12B, and 12C illustrate various views of portions of a semiconductor package 200C according to another embodiment. Semiconductor package 200C is similar to semiconductor package 200 in fig. 9B, but trench 191 extends below (e.g., directly below) photonic package 100. Unlike fig. 9B, the groove 191 is disposed laterally outward of the photonic package 100, and the groove 191 in fig. 12A is partially disposed laterally outward of the photonic package 100. In some embodiments, a first sidewall of groove 191 is disposed within the boundary of photonic package 100 (e.g., defined by the sidewalls), while a second, opposite sidewall of groove 191 is disposed outside the boundary of photonic package 100. In some embodiments, the lateral offset D4 between the first sidewall of the groove 191 and the corresponding sidewall (e.g., the closest sidewall) of the photonic package 100 is greater than 0 millimeters and less than 0.5 millimeters.

Fig. 12B shows a top view of the semiconductor package 200C. The top view of semiconductor package 200C is similar to the top view in fig. 9C, but trench 191 extends to the boundary of photonic package 100. Fig. 12C is an enlarged view of a portion of fig. 12B. The optical cement 147 is also shown in phantom in fig. 12C. As shown in fig. 12C, the groove 191 extends to the boundary of the photonic package 100 and may also overlap at least part of the edge coupler 139. Fig. 12C also shows the lateral offset D4 shown in fig. 12A.

Fig. 13 shows a cross-sectional view of a semiconductor package 200D according to another embodiment. The semiconductor package 200D is similar to the semiconductor package 200 of fig. 9A, but one of the photonic packages 100 in fig. 9A is replaced with a photonic package 100A, and the ring 181 in fig. 9A is replaced with a cover 201. The cover 201 has an opening in its top portion to allow connection of, for example, the optical fiber 185 to the photonic package 100/100A. For example, a Fiber Array Unit (FAU) 203 is connected to the photonic package 100 for optical coupling between the vertically mounted optical fibers 185 and the edge coupler 139 of the photonic package 100. In addition, another vertically mounted optical fiber 185 is connected to the photonic package 100A and optically coupled to a photonic component (e.g., a grating coupler) of the photonic package 100A. The cover 201 may be attached to the substrate 170 by, for example, an adhesive material. The central portion of the lid 201 may contact the photonic package 100/100A and the electronic die 153 directly or through a Thermal Interface Material (TIM) to facilitate heat dissipation.

In some embodiments, the photonic package 100A is similar to the photonic package 100 of fig. 6, but the nitride waveguide 137, the edge coupler 139, and the dielectric layer 131 forming the nitride waveguide 137 are replaced with a redistribution structure similar to the redistribution structure 129 of fig. 6. Furthermore, the grating coupler may be integrated in the waveguide 133 of the photonic package 100A. Fig. 13 further illustrates microlenses 209 formed in the substrate of the electronics die of photonic package 100A. The optical fiber 185 is mounted vertically on the back side of the photonic package 100A above the micro-lens 209 using an optical glue 187 and optically coupled to a grating coupler in the waveguide 133 of the photonic package 100A.

The FAU 203 is attached to the back side of the photonic package 100 using an adhesive material 207 and to the outer side wall of the optical glue 147 using an optical glue 205. The vertically mounted optical fiber 185 is attached to the upper surface of the FAU 203 using an optical cement 187. The FAU 203 provides an interface to enable optical coupling between the edge coupler 139 of the photonics die of the photonic package 100 and the vertically mounted optical fiber 185 connected to the FAU 203.

Fig. 14 shows a cross-sectional view of a semiconductor package 200E according to yet another embodiment. The semiconductor package 200E is similar to the semiconductor package 200D of fig. 13, but the right-hand photonic package 100 is also replaced with a photonic package 100A.

Embodiments may realize advantages. For example, by embedding optical glue 147 in photonics die 120, the optical coupling efficiency between edge coupler 139 and external optical fiber 185 is improved. In addition, the grooves 191 in the substrate 170 ensure that the underfill material 189 does not extend high along the sidewalls of the photonic package 100 and ensure that the outer sidewalls of the optical glue 147 are exposed for attachment or coupling to the optical fibers 185. The disclosed structures and methods allow optical coupling with edge couplers 139 of the photonic package (e.g., on the sidewalls of the photonic package through optical glue 147) and grating couplers (e.g., through vertically mounted optical fibers), as shown in fig. 13 and 14. The disclosed semiconductor packages (e.g., 150, 200) enable co-packaged optical (CPO) integration and high bandwidth and ultra low power consumption by integrating photonics die and electronics die in the same package.

Fig. 15 illustrates a flow chart of a method 1000 of forming a semiconductor package according to some embodiments. It should be understood that the implementation shown in fig. 15 is merely an example of many possible implementations. Those of ordinary skill in the art will recognize many variations, alternatives, and modifications. For example, various steps shown in fig. 15 may be added, removed, replaced, rearranged, or repeated.

Referring to fig. 15, at block 1010, a first wafer is bonded to a second wafer, wherein the first wafer includes a plurality of electronic dies and the second wafer includes a plurality of photonic dies. At block 1020, after bonding the first wafer, trenches are formed in the second wafer between adjacent ones of the plurality of photonics dies. At block 1030, the trench is filled with an optical cement. At block 1040, the first wafer and the second wafer are diced to form a plurality of photonic packages, wherein the photonic packages of the plurality of photonic packages include an electronic die, a photonic die bonded to the electronic die, and an optical glue, wherein the optical glue extends along sidewalls of the photonic packages.

According to an embodiment, a method of forming a semiconductor package, the method comprising: bonding a first wafer to a second wafer, wherein the first wafer comprises a plurality of electronic dies and the second wafer comprises a plurality of photonic dies; forming a trench in the second wafer between adjacent ones of the plurality of photonics dies after bonding the first wafer; filling the grooves with an optical cement; and dicing the first wafer and the second wafer to form a plurality of photonic packages, wherein a photonic package of the plurality of photonic packages includes an electronic die, a photonic die bonded to the electronic die, and the optical glue, wherein the optical glue extends along sidewalls of the photonic package. In an embodiment, a first wafer has a first dicing area and the second wafer has a second dicing area, wherein after the first wafer is bonded to the second wafer, the first dicing area is aligned with a corresponding one of the second dicing areas. In an embodiment, the trench is formed along the second cut region. In an embodiment, the trench is formed to extend through the second wafer. In an embodiment, the outer side wall of the optical glue of the photonic package is flush with the side wall of the photonic package. In an embodiment, a photonics die includes a first waveguide and an edge coupler optically coupled to the first waveguide, wherein the edge coupler is proximate a first sidewall of the photonics die facing the optical glue. In an embodiment, the optical cement is formed in contact with and extends along a first sidewall of the photonics die. In an embodiment, the method further comprises: attaching the photonic package to a carrier; attaching a die to the carrier and laterally adjacent to the photonic package; forming a molding material over the carrier and around the photonic package and the die; and forming a first redistribution structure over the die and the photonic package, and the first redistribution structure being electrically coupled with the die and the photonic package. In an embodiment, the method further comprises, after forming the first redistribution structure, performing a cutting process, wherein the cutting process removes portions of the molding material and exposes the outer side walls of the optical glue. In an embodiment, the method further comprises: after performing the dicing process, attaching the first redistribution structure to a first side of a substrate; and forming an underfill material between the first redistribution structure and the substrate, wherein the underfill material exposes the outer sidewalls of the optical glue. In an embodiment, the method further comprises connecting the optical fiber to an outer sidewall of the optical adhesive. In an embodiment, a substrate includes: a dielectric core; a second redistribution structure located on a first side of the dielectric core; and a solder mask layer over a second redistribution structure at the first side of the substrate, wherein a trench is in the solder mask layer, wherein connecting the first redistribution structure includes aligning the optical glue with the trench in the solder mask layer such that, in plan view, a central axis of the edge coupler intersects the optical glue and the trench in the solder mask layer.

According to an embodiment, a method of forming a semiconductor package includes: attaching a photonic package and a semiconductor die to a carrier, wherein the photonic package comprises an electronic die, a photonic die bonded to the electronic die, and an optical paste embedded in the photonic die, wherein a first sidewall of the optical paste is flush with a sidewall of the electronic die; forming a molding material over the carrier surrounding the photonic package and the semiconductor die, the molding material covering the first side wall of the optical adhesive; forming a redistribution structure over the molding material; and removing portions of the molding material after forming the redistribution structure to expose the first side wall of the optical adhesive. In an embodiment, the method further comprises, after removing said portion of said molding material: connecting the redistribution structure to a substrate; and forming an underfill material between the redistribution structure and the substrate. In an embodiment, a substrate includes a dielectric core, a conductive feature extending along a first surface of the dielectric core, and a dielectric layer on the conductive feature, wherein a trench is located in the dielectric layer, wherein the optical paste is adjacent to the trench after connecting the redistribution structure. In an embodiment, the photonics die includes an edge coupler for optical communication, wherein the edge coupler is adjacent to a sidewall of the photonics die facing the optical glue, wherein after connecting the redistribution structure, the edge coupler, the optical glue, and the trench are aligned along a same line in plan view. In an embodiment, the method further comprises optically coupling the external optical fiber to the edge coupler by an optical glue after the underfill material is formed.

According to an embodiment, a semiconductor package includes: a redistribution structure; a photonic package connected to the first face of the redistribution structure, the photonic package comprising an electronic die, a photonic die bonded to the electronic die, and an optical cement embedded in the photonic die, wherein a first sidewall of the optical cement is flush with a sidewall of the electronic die; a molding material on a first side of the redistribution structure, wherein the molding material partially surrounds the photonic package and exposes the first sidewall of the optical adhesive; a substrate connected to a second opposing face of the redistribution structure; and an underfill material between the substrate and the redistribution structure, wherein the underfill material exposes the first side wall of the optical glue. In an embodiment, the substrate includes a dielectric core, a conductive feature extending along a first surface of the dielectric core, and a dielectric layer on the conductive feature, wherein a trench is located in the dielectric layer. In an embodiment, the photonics die comprises an edge coupler for optical communication, wherein the edge coupler is adjacent to a sidewall of the photonics die facing the optical glue, wherein in plan view a central axis of the edge coupler intersects the optical glue and the trench.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the invention. Those skilled in the art will appreciate that they may readily use the embodiments of the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments presented herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method of forming a semiconductor package, the method comprising:

bonding a first wafer to a second wafer, wherein the first wafer comprises a plurality of electronic dies and the second wafer comprises a plurality of photonic dies;

forming a trench in the second wafer between adjacent ones of the plurality of photonics dies after bonding the first wafer;

filling the grooves with an optical cement; and

dicing the first wafer and the second wafer to form a plurality of photonic packages, wherein a photonic package of the plurality of photonic packages includes an electronic die, a photonic die bonded to the electronic die, and the optical glue, wherein the optical glue extends along sidewalls of the photonic package.

2. The method of claim 1, wherein the first wafer has a first dicing area and the second wafer has a second dicing area, wherein after the first wafer is bonded to the second wafer, the first dicing area is aligned with a corresponding one of the second dicing areas.

3. The method of claim 2, wherein the trench is formed along the second cut region.

4. The method of claim 3, wherein the trench is formed to extend through the second wafer.

5. The method of claim 1, wherein an outer sidewall of the optical glue of the photonic package is flush with the sidewall of the photonic package.

6. The method of claim 5, wherein the photonics die includes a first waveguide and an edge coupler optically coupled to the first waveguide, wherein the edge coupler is proximate a first sidewall of the photonics die facing the optical glue.

7. The method of claim 6, wherein the optical paste is formed in contact with and extends along the first sidewall of the photonics die.

8. The method of claim 6, further comprising:

Attaching the photonic package to a carrier;

attaching a die to the carrier and laterally adjacent to the photonic package;

forming a molding material over the carrier and around the photonic package and the die; and

a first redistribution structure is formed over the die and the photonic package, and the first redistribution structure is electrically coupled with the die and the photonic package.

9. A method of forming a semiconductor package, the method comprising:

attaching a photonic package and a semiconductor die to a carrier, wherein the photonic package comprises an electronic die, a photonic die bonded to the electronic die, and an optical paste embedded in the photonic die, wherein a first sidewall of the optical paste is flush with a sidewall of the electronic die;

forming a molding material over the carrier surrounding the photonic package and the semiconductor die, the molding material covering the first side wall of the optical adhesive;

forming a redistribution structure over the molding material; and

after forming the redistribution structure, portions of the molding material are removed to expose the first sidewalls of the optical cement.

10. A semiconductor package, comprising:

a redistribution structure;

a photonic package connected to the first face of the redistribution structure, the photonic package comprising an electronic die, a photonic die bonded to the electronic die, and an optical cement embedded in the photonic die, wherein a first sidewall of the optical cement is flush with a sidewall of the electronic die;

a molding material on a first side of the redistribution structure, wherein the molding material partially surrounds the photonic package and exposes the first sidewall of the optical adhesive;

a substrate connected to a second opposing face of the redistribution structure; and

an underfill material located between the substrate and the redistribution structure, wherein the underfill material exposes the first side wall of the optical glue.