CN1174628A - Multi-valued read-only storage location with improved signal-to noise ratio - Google Patents
Multi-valued read-only storage location with improved signal-to noise ratio Download PDFInfo
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- CN1174628A CN1174628A CN96191959A CN96191959A CN1174628A CN 1174628 A CN1174628 A CN 1174628A CN 96191959 A CN96191959 A CN 96191959A CN 96191959 A CN96191959 A CN 96191959A CN 1174628 A CN1174628 A CN 1174628A
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- 230000005669 field effect Effects 0.000 claims description 21
- 210000000352 storage cell Anatomy 0.000 claims description 14
- 238000009413 insulation Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 238000012163 sequencing technique Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims 13
- 239000002184 metal Substances 0.000 claims 4
- 229910052751 metal Inorganic materials 0.000 claims 4
- 239000002800 charge carrier Substances 0.000 claims 3
- 230000008901 benefit Effects 0.000 abstract description 2
- 230000015654 memory Effects 0.000 abstract 1
- 210000004027 cell Anatomy 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000001154 acute effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 240000001439 Opuntia Species 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005264 electron capture Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention concerns a multi-valued read-only storage location which is constructed symmetrically for storing a first or second state (M, M''') and asymmetrically for storing at least a third state (M', M''). The advantage thereof is above all that the storage capacity is doubled without notably increasing expenditure and without impairing the signal-to-noise ratio with respect to conventional storage locations. The invention is suitable for electrically programmable and mask-programmable read-only memories, in particular for those used in low-voltage technology.
Description
Common storage unit can be stored (Bit) information.Two states of storage unit can be transistorized high or low cut-off voltages in a single transistor cell for example.In a lot of disclosed storage unit, bit line at first is precharged to a definite voltage in readout.Via word line control store unit the time, the bit line that is connected on the storage unit is recharged more or less according to the concrete state of storage unit.In view of the above, the information of storage unit can be read out by high or low level via of bit line.In order to obtain high anti-interference, these two level must have high as far as possible voltage difference, for example have positive feed voltage and zero volt.
In order to increase information density, particularly in read-only storage, also adopt many-valued storage unit sometimes.Many-valued storage unit is that its storage capacity is respectively more than one storage unit.
Its publication No. is the read-only storage (ROM) that the international patent application of WO 82/02977 discloses a kind of available mask sequencing, can store in its storage unit more than only having only two logic states.Wherein, in order to obtain same size and the storage unit size minimum, logic state is to enroll storage unit like this, and the transistorized starting voltage (cut-off voltage) that promptly is in the concrete storage unit is adjusted separately respectively.
Wherein, a plurality of, for example four different magnitudes of voltage or current value must be distinguished reliably.This means for example and must pay higher circuit expense, and mean that at first anti-interference decreases in order to set up stable benchmark voltage.This also can cause yield rate to reduce.Estimate that this is the reason place that many-valued storage unit does not reach the practical stage so far.The modern times, its feed voltage decreases, and for example is that above-mentioned shortcoming is unacceptable especially in 3.3 volts the storer.
Task of the present invention is to provide a kind of many-valued storage unit, wherein, reduces required circuit expense as far as possible and compares with disclosed, many-valued storage unit, and its signal to noise ratio (S/N ratio) is significantly improved.According to the present invention, the technical scheme that solves this task is the feature described in claim 1.
Form of implementation of the present invention, preferred that claim 2 to 8 relates to, and claim 9 and 10 relates separately to the reading method to fixed value storage cell content of the present invention.
Describe the present invention in detail by accompanying drawing below.Accompanying drawing is depicted as:
Fig. 1 is of the present invention, the view of the storage unit under four possible states,
One of Fig. 2 A to 2D is of the present invention, be used to implement the different form of implementation of the MOS transistor npn npn that the storage unit of four different storage states uses,
The another kind of subform of Fig. 3 Fig. 2 D,
First improved storage unit circuit figure of the present invention of Fig. 4,
Fig. 5 is used to illustrate the sectional view of making storage unit shown in Figure 4,
Second improved storage unit circuit figure of the present invention of Fig. 6.
Figure 1 illustrates at four different conditions M, M ', M " and M under program, storage unit of the present invention and concrete unit lead end 1,2 and 3 thereof.Wherein, storage unit with state M is not put the shape mark, storage unit with state M ' has a some shape mark on unit lead end 1, have state M " storage unit a point shape mark is arranged on unit lead end 2, and the storage unit with state M all has a some shape mark on unit lead end 1 and 2.So having the state M of storage and the storage unit of M is symmetrical with regard to unit lead end 1 and 2, and has the state M ' and the M of storage " storage unit with regard to unit lead end 1 and 2, be asymmetric.
Show to Fig. 2 A to 2D illustrative the storage condition in the N channel transistor of one of four states in a storage unit (OTP storage unit) that for example is in a disposable programmable preface.
Wherein, Fig. 2 A shows MOS transistor not programming, symmetry.In the MOS transistor shown in Fig. 2 B, inserted negative charge near the scope of the gate oxide unit lead end 1.In view of the above, in order to set up an inversion channel below this zone, grid voltage VG must be higher than near the voltage of the gate oxide below the unit lead end 2.In brief, this means that near the cut-off voltage VT part the unit lead end 1 raises to some extent.MOS transistor is (drain-source voltage across poles VDS＞when VG-VT) working, realize that conducting is close near the cut-off voltage that only depends on that the source lead end is in the saturation region.According to the rules, the source lead end is that in two unit lead ends 1 or 2 that has the unit lead end of lower voltage.In view of the above, during as source electrode, obtain a high cut-off voltage, during as source electrode, obtain a low cut-off voltage at selected cell lead end 2 at selected cell lead end 1.In fact exactly put upside down in the situation of the unit lead end 1 shown in Fig. 2 C and 2 and the situation shown in Fig. 2 B.Fig. 2 D then shows all upborne situation of cut-off voltage of both sides.
Fig. 3 shows the situation of the cut-off voltage that raises to some extent in the whole piece raceway groove.Aspect electrical specification, Fig. 2 D and transistor shown in Figure 3 equate, but can adopt the distinct program method for designing, and the back also will illustrate in detail to this.
Listed successively in the table below the polarity that is used for Fig. 2 A to 2D or transistorized cut-off voltage (starting voltage) VT shown in Figure 3 and the voltage VDS on unit lead end 1 and 2 relation and affiliated, as the unit information of 2 figure places.Wherein, it is noted that the same with 1 common storage unit, the signal that continues has same high signal to noise ratio (S/N ratio).
The VT unit information of VT VDS=V12＞0 of VDS=V21＞0 o'clock o'clock
Low 00M
Low high 01M '
Height 10M "
High 11M
To state M " and the measure distinguished of M for example can be; on first module lead end 1, put earlier a fixing level; the bit line on the unit lead end 2 is charged to a precharge level in advance; wherein; this precharge level is different with fixed level on the unit lead end 1, and evaluated driving the storage unit variation of pairs of bit line current potential afterwards subsequently.Then this fixed level is placed on the unit lead end 2, the bit line on the unit lead end 1 is carried out the potential change that bit line is also evaluated in precharge once more.
Evaluation also can be carried out like this, promptly at first one first fixed level is placed on the unit lead end 1, and the level of the bit line on the unit lead end 2 evaluated, and subsequently one second fixed level is placed on the unit lead end 1, and once more the level of the bit line on the unit lead end 2 is evaluated.
Storage unit of the present invention for example is specially adapted to the storer (OTP) of disposable programmable preface.Wherein, can be by local to inject one be the oxide-nitride-oxide layer (ONO) of a component part of the insulation course ISO of MOS field effect transistor at least electronics, or by common oxide skin(coating) of the local injection of electronics is finished program composition.Wherein, when injecting " heat " electric charge under the high situation of drain-source voltage across poles VDS, these electric charges are injected near the little scope of drain region.Compare with common oxide skin(coating), the advantage of so-called ONO layer is that the ONO layer has high electron capture probability, and in fact these electric charges do not carry out sideway movement.Can cause state shown in Figure 3 by uniform injection.
Another form of implementation of the present invention is, near the doping of the raceway groove scope lead end is different from the doping of all the other raceway grooves of MOS field effect transistor.This can for example inject mask by one finishes, and the perforate of this injection mask only covers the part of raceway groove scope.Also can before be injected, source/drain electrode under the situation that for example covers the source electrode scope, inject additional doping, and it is diffused into the raceway groove from the transistor drain side in drain electrode.Required for this reason mask is self-adjustment and therefore more not critical.In addition, also can consider to select source-drain electrode to be injected with slow oblique angle or with acute angle.Acute angle injects, and for example spends subscripts by 0 to about 7 and goes into open in standard technique.Provide slow oblique angle from the exploitation of LATID transistor (drain electrode that wide-angle tilt injects), spent the experience that subscripts are gone into as 30 to 60.Comparatively speaking, the mask that is used for injecting with slow oblique angle is not critical, because this mask need only be overlapping with relevant source-drain electrode area in the transition range of gate oxide and can be overlapping arbitrarily with the raceway groove scope.
Improve the scheme of cut-off voltage as an alternative, also can for example reduce cut-off voltage by injecting positive electric charge.
In addition, the not only available certainly n channel transistor of corresponding storage unit is realized, and available p channel transistor is realized.
In order to set up transistorized asymmetry, not only can consider the influence of cut-off voltage, and can consider such as change the thickness of oxide or near drain lead end and source lead end, select different transistor widths for use.
In addition, when storage unit is read, can so distinguish three different transistor states, it is transistor or in linear zone work, (work under the situation of VDS＜VG-VT), less than the grid voltage that has reduced starting voltage VT at drain-source voltage across poles VDS in other words perhaps in saturation region operation.In this case, all lead ends are the reverse of polarity not, and just the size of the pressure reduction of unit lead end 1 and unit lead end 2 changes to some extent.Be listed in the table below in the different starting voltages that the working point produced:
VT unit information during VT V21 ≈ V31 during figure V21＞V31
The low 0M of 2A
2B height 1M '
2D.3 high 2M
Except foundation in MOS field effect transistor T is symmetrical or asymmetric, in another form of implementation,, form symmetry or asymmetric as diode or resistance by the element that is added with.
Figure 4 illustrates a MOS field effect transistor, the diode D1 in its source/drain region links to each other with unit lead end 1, and its leakage/source area links to each other with unit lead end 2 through a diode D2, and its grid lead end links to each other with unit lead end 3.Wherein, according to concrete program design, diode D1 can pass through the line K bridge joint of a conduction, and diode D2 can be by the line K ' bridge joint of a conduction.Can find out from following table four different states are how can be stored in the corresponding storage unit in view of the above.
Be located at as lower unit
Diode V (2) on the lead end-V (1) location mode unit information
-＞0 conducting 00M
＜0 conducting
1＞0 blocks 01M '
＜0 conducting
2＞0 conducting 10M "
＜0 blocks
1 and 2＞0 block 11M
＜0 blocks
Figure 5 illustrates a sectional view of a preferred form of implementation of storage unit shown in Figure 4, wherein, in order to form diode D1, n for example in this figure
+Inserted a p in the source/drain region S/D that mixes
+District, and in order to form diode D2, n for example in this figure
+Inserted a p equally in the leakage/source area D/S that mixes
+The district.In order to carry out program design, in the read-only storage (ROM) of an available mask sequencing, diode can be by the saturating p of corrosion
+The district is until n
+Source/the drain region of mixing or leakage/source area and comprise that the contact hole of contact line K and K ' is bridged.Therefore, sequencing can realize by an additional contact hole mask.
For the method for electricity consumption is programmed, diode must be able to separately and exclusively be bridged.This can for example can be undertaken by adding a high voltage, and this voltage is for example set up lasting conducting connection by burning logical oxide-isolation layer.
Substituting, original conductive connection also can separately and exclusively be disconnected by fusing.
The difference of Fig. 6 and Fig. 4 only is, resistance R 1 and R2 are set, in order to substitute diode D1 and D2.Wherein, setting up asymmetrical measure can be, the electric current that the resistance in the source electrode feeder line causes falls greater than the electric current that resistance caused in the drain electrode feeder line and falls.
The resistance of unit lead-in wire petiolarea can be changed by the density of dopant material and the degree of depth of doped region.The resistance of contact hole also can be by making, and for example the version by potential barrier is influenced.The same with the described form of implementation of Fig. 4, sequencing can be undertaken by an additional mask, and perhaps the method for electricity consumption is carried out.
Claims (10)
1, many-valued fixed value storage cell, this storage unit are used to store one first or second state (M, M ) and make symmetrical structure and be used to store at least one third state (M ', M ") and make unsymmetric structure.
2, according to described, the many-valued fixed value storage cell of claim 1,
Wherein, a first module lead end (1) links to each other with a source/drain region (S/D) that is in the semiconductor (H) of a MOS field effect transistor (T), one second unit lead end (2) links to each other with a leakage/source area (D/S) that is in the semiconductor (H) of MOS field effect transistor (T), and one the 3rd unit lead end (3) links to each other with the grid (G) of MOS field effect transistor, wherein, grid by an insulation course (ISO) and semiconductor electric insulation and
Wherein, MOS field effect transistor itself according to concrete sequencing requirement, with regard to first and second lead ends (1,2) or make symmetrical structure, is perhaps made unsymmetric structure.
3, according to described, the many-valued fixed value storage cell of claim 2,
Wherein, insulation course (ISO) has an oxide-nitride-oxide layer, in order to store first state (M), in this oxide-nitride-oxide layer, do not inject charge carrier, for in the both scopes above source/drain region, scope stored second state (M ) above leakage/source area again, in oxide-nitride-oxide layer, injected charge carrier, for the scope stored third state of (S/D) top (M ') and according to circumstances only in source/drain region, for the scope stored four condition above leakages/source area (D/S) only (M "), in oxide-nitride-oxide layer, injected charge carrier.
4, according to described, the many-valued fixed value storage cell of claim 2,
Wherein, between source/drain region and leakage/source area one is in channel region in the semiconductor (H) in the scope adjacent with source/drain region and in the scope adjacent with leakage/source area, mixed in the same manner in order to store first and second states (M, M ), and in order to store the third state (M ') and according to circumstances to store a four condition (M ") and differently mixed.
5, according to described, the many-valued fixed value storage cell of claim 1,
Wherein, in order to store first state (M), a first module lead end (1) directly is connected with a source/drain region (S/D) that is in the semiconductor (H) of a MOS field effect transistor and one second unit lead end (2) directly is connected with a leakage/source area (D/S) that is in the semiconductor (H) of MOS field effect transistor
Wherein, in order to store second state (M ), a first module lead end (1) links to each other with a source/drain region (S/D) that is in the semiconductor (H) of MOS field effect transistor through an element (D1, R1), and one second unit lead end (2) is connected with a leakage/source area (D/S) that is in the semiconductor (H) of MOS field effect transistor through another element (D2, R2)
Wherein, in order to store a third state (M '), a first module lead end (1) links to each other with a source/drain region (S/D) that is in the semiconductor (H) of MOS field effect transistor through element (D1, R1), and one second unit lead end (2) directly is connected with a leakage/source area (D/S) that is in the semiconductor (H) of MOS field effect transistor
Wherein, according to circumstances, in order to store a four condition (M "), a first module lead end (1) directly be connected with a source/drain region (S/D) that is in the semiconductor (H) of MOS field effect transistor and one second unit lead end (2) through another element (D2, R2) be connected with a leakage/source area (D/S) that is in the semiconductor (H) of MOS field effect transistor and
Wherein, one the 3rd unit lead end (3) is connected with a grid (G) of MOS field effect transistor, and wherein, this grid is by an insulation course (ISO) and semiconductor electric insulation.
6, according to described, the many-valued fixed value storage cell of claim 5,
Wherein, element is one first diode (D1), and another element is one second diode (D2).
7, according to described, the many-valued fixed value storage cell of claim 6,
Wherein, in order to form first diode (D 1), first module lead end (1) links to each other with the source/drain region (S/D) of MOS field effect transistor through one first additional zone (Z1), and in order to form second diode (D2), the second unit lead end (2) is connected with the leakage/source area (D/S) of MOS field effect transistor via one second additional zone (Z2)
Wherein, in order to store first state (M), first additional zone and second additional zone (Z1, Z2) all be by the sunk structure of first and second lead ends (1,2), at least stretch reach source/drain region (S/D) and leakage/source area (D/S), Metal Contact (K, K ') is bridged
Wherein, in order to store second state (M ), first and second additional zone (Z1, Z2) all be only the shallow flat structure by first and second lead ends (1,2), only stretch at least reach two additional zone, Metal Contact obtains contacting,
Wherein, in order to store the third state (M '), have only first additional zone (Z1) be by first lead end (1) a sunk structure, at least stretch reach source/drain region (S/D), Metal Contact is bridged, and
Wherein, according to circumstances, in order to store a four condition (M "), have only second additional zone (Z2) be by first lead end (1) a sunk structure, at least stretch reach leakage/source area (D/S), Metal Contact is bridged.
8, according to described, the many-valued fixed value storage cell of claim 5,
Wherein, element is that one first resistance (R1) and another element are one second resistance (R2).
9, be used to read a method according to described, the many-valued fixed value storage cell of one of claim 2 to 8,
Wherein, between the second unit lead end (2) and first module lead end (1), add a voltage (V21) and try to achieve one first cut-off voltage (VT1),
Relate to lead end (1,2) subsequently and voltage (V21) is carried out reversal and try to achieve one second cut-off voltage (VT2), and
Wherein, from two cut-off voltages, try to achieve a state that is stored in the many-valued fixed value storage cell respectively.
10, be used to read a method according to described, the many-valued fixed value storage cell of one of claim 2 to 4,
Wherein, the mode of trying to achieve one first cut-off voltage (VT1) is, adds a voltage (V21) between the second unit lead end (2) and first module lead end (1), and this voltage is so high, makes the MOS field effect transistor in linear zone work,
Wherein, try to achieve one second cut-off voltage (VT2) subsequently, its mode of trying to achieve is, between the second unit lead end (2) and first module lead end (1), add a voltage (V21), this voltage is so high, makes the MOS field effect transistor in saturation region operation, and
Wherein, from two cut-off voltages, try to achieve a store status in many-valued fixed value storage cell respectively.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19505293.5 | 1995-02-16 | ||
| DE19505293A DE19505293A1 (en) | 1995-02-16 | 1995-02-16 | Multi-value read-only memory cell with improved signal-to-noise ratio |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1174628A true CN1174628A (en) | 1998-02-25 |
| CN1107321C CN1107321C (en) | 2003-04-30 |
Family
ID=7754185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96191959A Expired - Fee Related CN1107321C (en) | 1995-02-16 | 1996-02-05 | Multi-valued read-only storage location with improved signal-to noise ratio |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US5825686A (en) |
| EP (1) | EP0809847B1 (en) |
| JP (1) | JPH11500559A (en) |
| KR (1) | KR19980702220A (en) |
| CN (1) | CN1107321C (en) |
| AR (1) | AR000974A1 (en) |
| DE (2) | DE19505293A1 (en) |
| IN (1) | IN185754B (en) |
| WO (1) | WO1996025741A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100437827C (en) * | 2002-02-15 | 2008-11-26 | 英特尔公司 | Using multiple status bits per cell for handling power failures during write operations |
| CN106782654A (en) * | 2015-11-23 | 2017-05-31 | 爱思开海力士有限公司 | Semiconductor storage and its operating method |
Families Citing this family (104)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6297096B1 (en) * | 1997-06-11 | 2001-10-02 | Saifun Semiconductors Ltd. | NROM fabrication method |
| IL125604A (en) | 1997-07-30 | 2004-03-28 | Saifun Semiconductors Ltd | Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge |
| US6768165B1 (en) * | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
| US5963465A (en) | 1997-12-12 | 1999-10-05 | Saifun Semiconductors, Ltd. | Symmetric segmented memory array architecture |
| US6430077B1 (en) | 1997-12-12 | 2002-08-06 | Saifun Semiconductors Ltd. | Method for regulating read voltage level at the drain of a cell in a symmetric array |
| US6633499B1 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Method for reducing voltage drops in symmetric array architectures |
| US6633496B2 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Symmetric architecture for memory cells having widely spread metal bit lines |
| US6002607A (en) * | 1998-02-24 | 1999-12-14 | National Semiconductor Corporation | Read-only-memory (ROM) having a memory cell that stores a plurality of bits of information |
| US6133101A (en) * | 1998-04-09 | 2000-10-17 | Texas Instruments - Acer Incorporated | Low mask count process to fabricate mask read only memory devices |
| US6030871A (en) | 1998-05-05 | 2000-02-29 | Saifun Semiconductors Ltd. | Process for producing two bit ROM cell utilizing angled implant |
| US6348711B1 (en) * | 1998-05-20 | 2002-02-19 | Saifun Semiconductors Ltd. | NROM cell with self-aligned programming and erasure areas |
| US6215148B1 (en) | 1998-05-20 | 2001-04-10 | Saifun Semiconductors Ltd. | NROM cell with improved programming, erasing and cycling |
| JP4623782B2 (en) * | 1999-10-15 | 2011-02-02 | スパンション エルエルシー | Semiconductor memory device and method of using the same |
| US6240020B1 (en) | 1999-10-25 | 2001-05-29 | Advanced Micro Devices | Method of bitline shielding in conjunction with a precharging scheme for nand-based flash memory devices |
| US6175523B1 (en) | 1999-10-25 | 2001-01-16 | Advanced Micro Devices, Inc | Precharging mechanism and method for NAND-based flash memory devices |
| US6429063B1 (en) | 1999-10-26 | 2002-08-06 | Saifun Semiconductors Ltd. | NROM cell with generally decoupled primary and secondary injection |
| JP4697993B2 (en) * | 1999-11-25 | 2011-06-08 | スパンション エルエルシー | Control method for nonvolatile semiconductor memory device |
| US6222768B1 (en) | 2000-01-28 | 2001-04-24 | Advanced Micro Devices, Inc. | Auto adjusting window placement scheme for an NROM virtual ground array |
| US6272043B1 (en) | 2000-01-28 | 2001-08-07 | Advanced Micro Devices, Inc. | Apparatus and method of direct current sensing from source side in a virtual ground array |
| US6201737B1 (en) | 2000-01-28 | 2001-03-13 | Advanced Micro Devices, Inc. | Apparatus and method to characterize the threshold distribution in an NROM virtual ground array |
| US6243300B1 (en) | 2000-02-16 | 2001-06-05 | Advanced Micro Devices, Inc. | Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell |
| US6215702B1 (en) | 2000-02-16 | 2001-04-10 | Advanced Micro Devices, Inc. | Method of maintaining constant erasing speeds for non-volatile memory cells |
| US6266281B1 (en) | 2000-02-16 | 2001-07-24 | Advanced Micro Devices, Inc. | Method of erasing non-volatile memory cells |
| US6396741B1 (en) | 2000-05-04 | 2002-05-28 | Saifun Semiconductors Ltd. | Programming of nonvolatile memory cells |
| US6490204B2 (en) | 2000-05-04 | 2002-12-03 | Saifun Semiconductors Ltd. | Programming and erasing methods for a reference cell of an NROM array |
| US6477083B1 (en) | 2000-10-11 | 2002-11-05 | Advanced Micro Devices, Inc. | Select transistor architecture for a virtual ground non-volatile memory cell array |
| US6583479B1 (en) | 2000-10-16 | 2003-06-24 | Advanced Micro Devices, Inc. | Sidewall NROM and method of manufacture thereof for non-volatile memory cells |
| JP2002208274A (en) | 2000-11-10 | 2002-07-26 | Hitachi Ltd | Semiconductor memory |
| US6465306B1 (en) | 2000-11-28 | 2002-10-15 | Advanced Micro Devices, Inc. | Simultaneous formation of charge storage and bitline to wordline isolation |
| US6468865B1 (en) | 2000-11-28 | 2002-10-22 | Advanced Micro Devices, Inc. | Method of simultaneous formation of bitline isolation and periphery oxide |
| US6445030B1 (en) | 2001-01-30 | 2002-09-03 | Advanced Micro Devices, Inc. | Flash memory erase speed by fluorine implant or fluorination |
| US6448750B1 (en) | 2001-04-05 | 2002-09-10 | Saifun Semiconductor Ltd. | Voltage regulator for non-volatile memory with large power supply rejection ration and minimal current drain |
| US6584017B2 (en) | 2001-04-05 | 2003-06-24 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
| US6577514B2 (en) | 2001-04-05 | 2003-06-10 | Saifun Semiconductors Ltd. | Charge pump with constant boosted output voltage |
| US6436768B1 (en) | 2001-06-27 | 2002-08-20 | Advanced Micro Devices, Inc. | Source drain implant during ONO formation for improved isolation of SONOS devices |
| US6630384B1 (en) | 2001-10-05 | 2003-10-07 | Advanced Micro Devices, Inc. | Method of fabricating double densed core gates in sonos flash memory |
| US6791396B2 (en) | 2001-10-24 | 2004-09-14 | Saifun Semiconductors Ltd. | Stack element circuit |
| US6643181B2 (en) | 2001-10-24 | 2003-11-04 | Saifun Semiconductors Ltd. | Method for erasing a memory cell |
| US7098107B2 (en) * | 2001-11-19 | 2006-08-29 | Saifun Semiconductor Ltd. | Protective layer in memory device and method therefor |
| US6583007B1 (en) | 2001-12-20 | 2003-06-24 | Saifun Semiconductors Ltd. | Reducing secondary injection effects |
| US6885585B2 (en) * | 2001-12-20 | 2005-04-26 | Saifun Semiconductors Ltd. | NROM NOR array |
| US7221591B1 (en) * | 2002-05-06 | 2007-05-22 | Samsung Electronics Co., Ltd. | Fabricating bi-directional nonvolatile memory cells |
| US6914820B1 (en) | 2002-05-06 | 2005-07-05 | Multi Level Memory Technology | Erasing storage nodes in a bi-directional nonvolatile memory cell |
| US6747896B2 (en) | 2002-05-06 | 2004-06-08 | Multi Level Memory Technology | Bi-directional floating gate nonvolatile memory |
| US6917544B2 (en) | 2002-07-10 | 2005-07-12 | Saifun Semiconductors Ltd. | Multiple use memory chip |
| US6826107B2 (en) | 2002-08-01 | 2004-11-30 | Saifun Semiconductors Ltd. | High voltage insertion in flash memory cards |
| US6707078B1 (en) | 2002-08-29 | 2004-03-16 | Fasl, Llc | Dummy wordline for erase and bitline leakage |
| US7136304B2 (en) | 2002-10-29 | 2006-11-14 | Saifun Semiconductor Ltd | Method, system and circuit for programming a non-volatile memory array |
| US7178004B2 (en) | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
| US7078306B1 (en) | 2003-03-24 | 2006-07-18 | Integrated Device Technology, Inc. | Method for forming a thin film resistor structure |
| WO2005015567A1 (en) | 2003-07-29 | 2005-02-17 | Infineon Technologies Ag | Non-volatile memory element with increased data security |
| FR2871282B1 (en) * | 2004-06-04 | 2006-09-15 | St Microelectronics Sa | PROGRAMMABLE MEMORY DEVICE ONCE ONLY |
| US7638850B2 (en) | 2004-10-14 | 2009-12-29 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
| JP2006252670A (en) * | 2005-03-10 | 2006-09-21 | Matsushita Electric Ind Co Ltd | Method for driving nonvolatile memory and nonvolatile memory used therefor |
| US8053812B2 (en) * | 2005-03-17 | 2011-11-08 | Spansion Israel Ltd | Contact in planar NROM technology |
| US7633128B2 (en) * | 2005-07-15 | 2009-12-15 | Guobiao Zhang | N-ary mask-programmable memory |
| US7821080B2 (en) * | 2005-07-15 | 2010-10-26 | Guobiao Zhang | N-ary three-dimensional mask-programmable read-only memory |
| JP2007027760A (en) | 2005-07-18 | 2007-02-01 | Saifun Semiconductors Ltd | High density nonvolatile memory array and manufacturing method |
| US7921400B1 (en) | 2005-07-20 | 2011-04-05 | Integrated Device Technology, Inc. | Method for forming integrated circuit device using cell library with soft error resistant logic cells |
| US7206214B2 (en) * | 2005-08-05 | 2007-04-17 | Freescale Semiconductor, Inc. | One time programmable memory and method of operation |
| US7668017B2 (en) | 2005-08-17 | 2010-02-23 | Saifun Semiconductors Ltd. | Method of erasing non-volatile memory cells |
| US7221138B2 (en) * | 2005-09-27 | 2007-05-22 | Saifun Semiconductors Ltd | Method and apparatus for measuring charge pump output current |
| US7808818B2 (en) | 2006-01-12 | 2010-10-05 | Saifun Semiconductors Ltd. | Secondary injection for NROM |
| US8253452B2 (en) | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
| US7692961B2 (en) | 2006-02-21 | 2010-04-06 | Saifun Semiconductors Ltd. | Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection |
| US7760554B2 (en) | 2006-02-21 | 2010-07-20 | Saifun Semiconductors Ltd. | NROM non-volatile memory and mode of operation |
| US7638835B2 (en) * | 2006-02-28 | 2009-12-29 | Saifun Semiconductors Ltd. | Double density NROM with nitride strips (DDNS) |
| US7701779B2 (en) | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
| US7678620B2 (en) * | 2006-10-05 | 2010-03-16 | Freescale Semiconductor, Inc. | Antifuse one time programmable memory array and method of manufacture |
| US7590001B2 (en) | 2007-12-18 | 2009-09-15 | Saifun Semiconductors Ltd. | Flash memory with optimized write sector spares |
| US8564070B2 (en) | 2010-05-24 | 2013-10-22 | Chengdu Haicun Ip Technology Llc | Large bit-per-cell three-dimensional mask-programmable read-only memory |
| US9117493B2 (en) | 2011-09-01 | 2015-08-25 | Chengdu Haicun Ip Technology Llc | Discrete three-dimensional memory comprising off-die address/data translator |
| US9123393B2 (en) | 2011-09-01 | 2015-09-01 | HangZhou KiCun nformation Technology Co. Ltd. | Discrete three-dimensional vertical memory |
| US9666300B2 (en) | 2011-09-01 | 2017-05-30 | XiaMen HaiCun IP Technology LLC | Three-dimensional one-time-programmable memory comprising off-die address/data-translator |
| US8890300B2 (en) | 2011-09-01 | 2014-11-18 | Chengdu Haicun Ip Technology Llc | Discrete three-dimensional memory comprising off-die read/write-voltage generator |
| US9559082B2 (en) | 2011-09-01 | 2017-01-31 | HangZhou HaiCun Information Technology Co., Ltd. | Three-dimensional vertical memory comprising dice with different interconnect levels |
| US8699257B2 (en) | 2011-09-01 | 2014-04-15 | HangZhou HaiCun Information Technology Co., Ltd. | Three-dimensional writable printed memory |
| US9299390B2 (en) | 2011-09-01 | 2016-03-29 | HangZhou HaiCun Informationa Technology Co., Ltd. | Discrete three-dimensional vertical memory comprising off-die voltage generator |
| US9024425B2 (en) | 2011-09-01 | 2015-05-05 | HangZhou HaiCun Information Technology Co., Ltd. | Three-dimensional memory comprising an integrated intermediate-circuit die |
| US9508395B2 (en) | 2011-09-01 | 2016-11-29 | HangZhou HaiCun Information Technology Co., Ltd. | Three-dimensional one-time-programmable memory comprising off-die read/write-voltage generator |
| US9396764B2 (en) | 2011-09-01 | 2016-07-19 | HangZhou HaiCun Information Technology Co., Ltd. | Discrete three-dimensional memory |
| US9190412B2 (en) | 2011-09-01 | 2015-11-17 | HangZhou HaiCun Information Technology Co., Ltd. | Three-dimensional offset-printed memory |
| US9305605B2 (en) | 2011-09-01 | 2016-04-05 | Chengdu Haicun Ip Technology Llc | Discrete three-dimensional vertical memory |
| US9558842B2 (en) | 2011-09-01 | 2017-01-31 | HangZhou HaiCun Information Technology Co., Ltd. | Discrete three-dimensional one-time-programmable memory |
| US9093129B2 (en) | 2011-09-01 | 2015-07-28 | Chengdu Haicun Ip Technology Llc | Discrete three-dimensional memory comprising dice with different BEOL structures |
| US8921991B2 (en) | 2011-09-01 | 2014-12-30 | Chengdu Haicun Ip Technology Llc | Discrete three-dimensional memory |
| US9305604B2 (en) | 2011-09-01 | 2016-04-05 | HangZhou HaiCun Information Technology Co., Ltd. | Discrete three-dimensional vertical memory comprising off-die address/data-translator |
| US8679929B2 (en) * | 2011-12-06 | 2014-03-25 | Texas Instruments Incorporated | On current in one-time-programmable memory cells |
| US9001555B2 (en) | 2012-03-30 | 2015-04-07 | Chengdu Haicun Ip Technology Llc | Small-grain three-dimensional memory |
| US9293509B2 (en) | 2013-03-20 | 2016-03-22 | HangZhou HaiCun Information Technology Co., Ltd. | Small-grain three-dimensional memory |
| US10304495B2 (en) | 2014-04-14 | 2019-05-28 | Chengdu Haicun Ip Technology Llc | Compact three-dimensional memory with semi-conductive address line portion |
| US10199432B2 (en) | 2014-04-14 | 2019-02-05 | HangZhou HaiCun Information Technology Co., Ltd. | Manufacturing methods of MOSFET-type compact three-dimensional memory |
| US10079239B2 (en) | 2014-04-14 | 2018-09-18 | HangZhou HaiCun Information Technology Co., Ltd. | Compact three-dimensional mask-programmed read-only memory |
| US10446193B2 (en) | 2014-04-14 | 2019-10-15 | HangZhou HaiCun Information Technology Co., Ltd. | Mixed three-dimensional memory |
| US10304553B2 (en) | 2014-04-14 | 2019-05-28 | HangZhou HaiCun Information Technology Co., Ltd. | Compact three-dimensional memory with an above-substrate decoding stage |
| CN104979352A (en) | 2014-04-14 | 2015-10-14 | 成都海存艾匹科技有限公司 | Mixed Three-dimensional Printed Memory |
| CN104978990B (en) | 2014-04-14 | 2017-11-10 | 成都海存艾匹科技有限公司 | Compact three-dimensional storage |
| US10211258B2 (en) | 2014-04-14 | 2019-02-19 | HangZhou HaiCun Information Technology Co., Ltd. | Manufacturing methods of JFET-type compact three-dimensional memory |
| US10102917B2 (en) | 2016-04-14 | 2018-10-16 | Chengdu Haicun Ip Technology Llc | Multi-bit-per-cell three-dimensional one-time-programmable memory |
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| CN107316869A (en) | 2016-04-16 | 2017-11-03 | 成都海存艾匹科技有限公司 | Three-dimensional longitudinal direction one-time programming memory |
| US10559574B2 (en) | 2016-04-16 | 2020-02-11 | HangZhou HaiCun Information Technology Co., Ltd. | Three-dimensional vertical one-time-programmable memory comprising Schottky diodes |
| US10490562B2 (en) | 2016-04-16 | 2019-11-26 | HangZhou HaiCun Information Technology Co., Ltd. | Three-dimensional vertical one-time-programmable memory comprising multiple antifuse sub-layers |
| US10566388B2 (en) | 2018-05-27 | 2020-02-18 | HangZhou HaiCun Information Technology Co., Ltd. | Three-dimensional vertical memory |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4208780A (en) * | 1978-08-03 | 1980-06-24 | Rca Corporation | Last-stage programming of semiconductor integrated circuits including selective removal of passivation layer |
| GB2157489A (en) * | 1984-03-23 | 1985-10-23 | Hitachi Ltd | A semiconductor integrated circuit memory device |
| JPH07120720B2 (en) * | 1987-12-17 | 1995-12-20 | 三菱電機株式会社 | Nonvolatile semiconductor memory device |
| JP2650775B2 (en) * | 1990-08-11 | 1997-09-03 | シャープ株式会社 | Method for manufacturing semiconductor device |
| JPH05283654A (en) * | 1992-04-03 | 1993-10-29 | Toshiba Corp | Mask rom and manufacture thereof |
| JP2690242B2 (en) * | 1992-07-13 | 1997-12-10 | 松下電子工業株式会社 | Semiconductor fixed storage device |
| DE69316298T2 (en) * | 1992-10-02 | 1998-04-23 | Matsushita Electric Ind Co Ltd | Non-volatile memory cell |
| CA2093111C (en) * | 1993-03-31 | 1997-03-18 | Thomas W. Macelwee | High value resistive load for an integrated circuit |
| JP3317459B2 (en) * | 1993-04-30 | 2002-08-26 | ローム株式会社 | Nonvolatile storage element, nonvolatile storage device using the same, method of driving this storage device, and method of manufacturing this storage element |
| US5469163A (en) * | 1993-05-24 | 1995-11-21 | Texas Instruments Incorporated | Multiple resonant tunneling circuits for positive digit range-4 base-2 to binary conversion |
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1995
- 1995-02-16 DE DE19505293A patent/DE19505293A1/en not_active Withdrawn
- 1995-12-28 IN IN1748CA1995 patent/IN185754B/en unknown
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- 1996-02-05 JP JP8524568A patent/JPH11500559A/en not_active Abandoned
- 1996-02-05 US US08/875,955 patent/US5825686A/en not_active Expired - Lifetime
- 1996-02-05 WO PCT/DE1996/000168 patent/WO1996025741A2/en active IP Right Grant
- 1996-02-05 CN CN96191959A patent/CN1107321C/en not_active Expired - Fee Related
- 1996-02-05 EP EP96901232A patent/EP0809847B1/en not_active Expired - Lifetime
- 1996-02-05 DE DE59600366T patent/DE59600366D1/en not_active Expired - Lifetime
- 1996-02-16 AR ARP960101414A patent/AR000974A1/en unknown
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100437827C (en) * | 2002-02-15 | 2008-11-26 | 英特尔公司 | Using multiple status bits per cell for handling power failures during write operations |
| CN106782654A (en) * | 2015-11-23 | 2017-05-31 | 爱思开海力士有限公司 | Semiconductor storage and its operating method |
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| DE19505293A1 (en) | 1996-08-22 |
| DE59600366D1 (en) | 1998-08-27 |
| CN1107321C (en) | 2003-04-30 |
| WO1996025741A2 (en) | 1996-08-22 |
| US5825686A (en) | 1998-10-20 |
| EP0809847B1 (en) | 1998-07-22 |
| JPH11500559A (en) | 1999-01-12 |
| WO1996025741A3 (en) | 1997-02-06 |
| IN185754B (en) | 2001-04-24 |
| EP0809847A2 (en) | 1997-12-03 |
| KR19980702220A (en) | 1998-07-15 |
| AR000974A1 (en) | 1997-08-27 |
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