CN117413247A

CN117413247A - Data processing method, device and system

Info

Publication number: CN117413247A
Application number: CN202180098836.8A
Authority: CN
Inventors: 吴黎明; 张颇; 朱强; 何江
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-05-31
Filing date: 2021-05-31
Publication date: 2024-01-16
Also published as: WO2022252082A1

Abstract

A data processing method, device and system, wherein a computing device includes a processor and a communication interface, the processor coupled to a storage device through the communication interface, the processor to: the method comprises the steps of obtaining a first address of a first logical partition in storage equipment, wherein the first address is a current initial write-in address of the first logical partition, the first logical partition is any one of a plurality of logical partitions included in the storage equipment, at least one first input/output IO command is sent to the storage equipment, an access address corresponding to each first IO command is located in a first address range, the first address range is a logical address range determined according to the first address and a preset first length in the first logical partition, first information sent by the storage equipment in response to the at least one first IO command is received, the first information is used for the computing equipment to send IO commands corresponding to the second address, and therefore concurrent writing of data to the storage equipment can be achieved without changing a software architecture of a system, and data writing efficiency is effectively improved.

Description

Data processing method, device and system

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a data processing method, device, and system.

Background

With the continuous development of storage technology, solid state disks (solid state drive, SSD) are widely used in various fields due to absolute advantages in performance, reliability, energy consumption and portability, and SSD uses Flash memory (NAND Flash) as a storage medium, and generally, SSD contains a plurality of NAND Flash particles. The host interacts with the conventional SSD in such a way that the host specifies an address in the write IO command, and then the SSD writes data to the address specified by the host according to the write command, but does not support concurrent writing of data. To further improve performance of aspects of solid state disks, partition namespaces (ZNSs) SSDs have been proposed, where the entire logical block address (logical block address, LBA) space of the ZNSs SSD is divided into a plurality of partitions (zones), and the zones are similar to one area of a shingled magnetic recording (shingled magnetic recording, SMR) disk partition, so as to implement partition storage. Because sequential writing is required in a zone, when multiple threads write into the same zone, the problem that the writing speed is limited or the writing position is incorrect due to competition of writing pointers among multiple threads is solved, so ZNS provides a writing mode of additional writing (application), and the matching process of a host (host) and a hard disk in the writing mode is as follows: when a host issues a write IO command to a certain zone in an SSD, the content carried by the write IO command comprises a starting LBA of the zone, the number of LBAs occupied by data and the data, after the ZNS SSD receives the IO, the ZNS SSD autonomously determines the position where the data carried by the IO is actually written into the zone, after the ZNS SSD completes writing operation, the address of the position where the data is actually written into is sent to the host, the host needs to wait for the data to be written into to complete writing, and then the address of the actually written data is recorded.

Disclosure of Invention

The application provides a data processing method, device and system, so that the concurrent writing of data to a storage device by a computing device is realized under the condition that the software architecture of a traditional storage system is not changed, and the data writing efficiency is improved.

In a first aspect, the present application provides a computing device comprising a processor and a communication interface, the processor coupled to a storage device through the communication interface. A processor for: the method comprises the steps of obtaining a first address of a first logical partition in storage equipment, wherein the first address is a current initial write-in address of the first logical partition, the first logical partition is any one of a plurality of logical partitions included in the storage equipment, at least one first input/output IO command is sent to the storage equipment, an access address corresponding to each first IO command is located in a first address range, the first address range is a logical address range determined according to the first address and a preset first length in the first logical partition, first information sent by the storage equipment in response to the at least one first IO command is received, and the first information is used for sending IO commands corresponding to the second address by computing equipment.

According to the embodiment of the application, the computing device writes the data to the appointed address where the first logical partition is according to the IO command by appointing the address where the data is actually written in the IO command, and the write behavior of the first logical partition is consistent with that of the traditional SSD, so that the data can be written to the storage device in parallel without changing the software architecture of the system, unnecessary complexity and workload can be reduced, furthermore, the computing device can issue IO commands of any address in the first address range, and issue IO commands corresponding to the second address as soon as possible according to the first information fed back by the storage device, so that the storage device can continue to operate in a mode of writing the data sequentially, consumption of cache resources can be reduced, and the efficiency of writing the data is effectively improved.

In one possible design, the first length is determined according to a size of a first cache space, where the first cache space is a cache space in a cache in the storage device for caching IO commands for accessing the first logical partition. In the design, the computing equipment can perform data out-of-order writing in a large concurrency mode and is cached in the first cache space, the speed of writing data is mainly influenced by the size of the first cache space, and the number of IO commands has small influence on the speed of writing data.

In one possible design, the processor is further configured to: the size of the first buffer space is configured. By configuring the size of the first buffer space, the number of IO commands issued by the computing device can be limited, so that the data writing efficiency is improved.

In one possible design, the first information includes a result of successfully writing the first data to the first address and a second address, and the second address is different from the first address, the processor further configured to: and sending at least one second IO command to the storage device according to the result of successfully writing the first data into the first address and the second address, wherein the at least one second IO command comprises a second IO command corresponding to the second address. By the design, the IO command of the next new address can be issued as soon as possible under the condition that successful data is written to the first address.

In one possible design, the current starting write address of the first logical partition is a second address, and the access address corresponding to each second IO command in the at least one second IO command is located in a second address range, where the second address range is a logical address range determined according to the second address and the first length in the first logical partition. Through the design, under the condition that the IO command corresponding to the current initial writing address of the first logic partition is not issued yet, the computing device can issue the IO command corresponding to the current initial writing address of the first logic partition as soon as possible.

In one possible design, the current initial write address of the first logical partition is a third address, and the access address corresponding to each second IO command is located in a second address range, where the second address range is a logical address range determined according to the third address and the first length in the first logical partition. Through the design, under the condition that the IO command corresponding to the current initial write address of the first logical partition is issued, the computing device can issue the undelivered IO command corresponding to the access address after the current initial write address of the first logical partition as soon as possible.

In one possible design, the first information further includes at least one of the following second information: the state code of the first cache space corresponding to the first logical partition indicates that the first cache space is full; the remaining capacity of the storage device. A processor, further configured to: and determining whether to continue issuing a second IO command located in a second address range to the storage device according to at least one item of second information included in the first information. By the design, the user can know in time when the first cache space is full or the residual capacity is zero, and data is not issued to the first logic partition any more, so that a back pressure mechanism can be formed, and the situation that the computing equipment issues write data to the first logic partition without limitation is avoided.

In one possible design, the first information further includes at least one of the following third information: the data volume which is cached in the first cache space and is not written into the first logical partition and corresponds to the first logical partition; the residual capacity of the first cache space corresponding to the first logical partition; a remaining capacity of the storage device; the remaining capacity of the first logical partition; a processor, further configured to: and if the second IO commands in the second address range are determined to be continuously issued to the storage device, determining the number of the second IO commands in the second address range issued to the storage device according to at least one item of second information included in the first information. Through the design, the computing device can acquire the related information of the first cache space corresponding to the first logical partition, so that the speed of issuing the IO command by the first logical partition can be controlled.

In one possible design, the first information further includes an IO command that times out in a first cache space corresponding to the first logical partition, and the processor is further configured to: the timeout IO command is resent to the storage device. By the design, the computing equipment can be enabled to know which IO commands need to be retransmitted, and IO commands ending due to write missing timeout are avoided.

In one possible design, the first information further includes a delay duration corresponding to the IO command to be retransmitted that is not successfully buffered in the first buffer space, and the processor is specifically configured to: and retransmitting the IO command to be retransmitted to the storage device after the waiting time length reaches the delay time length. By the design, continuous data issuing can be avoided.

In one possible design, the first information includes a result of a failure to write the first data to the first address and a second address, the second address being the same as the first address, the processor further configured to: and according to the result of the failure of writing the first data into the first address and the first address, sending a first IO command corresponding to the first address to the storage device. By the design, the IO command corresponding to the first address can be issued as soon as possible under the condition that the data writing to the first address fails.

In a second aspect, the present application provides a memory controller comprising a processor and a communication interface, the processor being coupled to a computing device through the communication interface. A processor for: receiving at least one first input/output IO command sent by a computing device, wherein an access address corresponding to each first IO command is located in a first address range, the first address range is a logic address range determined according to a first address and a preset first length in a first logic partition, and the first logic partition is any one of a plurality of logic partitions included in a storage device; storing at least one first IO command in a first cache space; determining a current initial write address of a first logical partition as a first address, selecting and executing a corresponding command from at least one first IO command according to the first address, and sending first information to the computing device, wherein the first information is used for the computing device to issue the IO command corresponding to a second address.

In the embodiment of the application, the address where the data is actually written is specified in the IO command by the computing device, and the storage controller writes the data to the specified address where the first logical partition is located according to the IO command, which is consistent with the writing behavior of the traditional SSD, so that the concurrent writing of the data to the storage controller can be realized without changing the software architecture of the system, thereby reducing unnecessary complexity and workload.

In one possible design, the first length is determined according to a size of a first cache space, where the first cache space is a cache space in a cache in the storage device for caching IO commands for accessing the first logical partition. In the design, the storage device can receive large concurrent issued data of the computing device and buffer the data in the first buffer space, the speed of writing the data is mainly influenced by the size of the first buffer space, and the number of IO commands has small influence on the speed of writing the data.

In one possible design, a size of the first cache space corresponding to the first logical partition is configured for the computing device. The number of IO commands issued by the computing device can be limited by configuring the size of the first cache space by the computing device, so that the data writing efficiency is improved.

In one possible design, if the first IO command corresponding to the first address is found in the first cache space, where the first IO command corresponding to the first address includes first data, the first data is written into the first address, and first information including a result of successfully writing the first data into the first address and a second address is sent to the computing device, where the second address is different from the first address, and the first information is used for the computing device to issue the IO command corresponding to the second address. Through the design, when the data is successfully written into the first address, the IO command corresponding to the address where the data is required to be written next can be acquired as soon as possible, so that the data writing efficiency can be improved.

In one possible design, the processor is further configured to: setting a first duration for each first IO command in at least one first IO command, and deleting the overtime first IO command from the first cache space after the storage duration of any first IO command in the first cache space exceeds the first duration, so that the overtime IO commands can be prevented from consuming cache resources.

In one possible design, the processor is further configured to: receiving at least one second IO command sent by the computing device, wherein the at least one second IO command comprises second IO commands corresponding to second addresses, and an access address corresponding to each second IO command is located in a second address range; if the current initial write address of the first logical partition is a second address, the second address range is a logical address range determined according to the second address and the first length in the first logical partition; or if the current initial write address of the first logical partition is the third address, the second address range is a logical address range determined according to the third address and the first length in the first logical partition. Through the design, the storage device can timely receive the IO command corresponding to the current initial write address of the first logical partition and the undelivered IO command corresponding to the access address after the current initial write address of the first logical partition.

In one possible design, the first information further includes at least one of the following second information: a status code of the first cache space corresponding to the first logical partition, the status code indicating that the first cache space is full; the remaining capacity of the storage device; the first information includes at least one item of second information for determining, by the computing device, whether to continue issuing the second IO command located in the second address range to the storage device. Through the design, the computing device can know in time when the first cache space is full or the residual capacity is zero, and does not issue data to the first logic partition any more, so that a back pressure mechanism can be formed, and the computing device is prevented from issuing write data to the first logic partition without limitation.

In one possible design, the first information further includes at least one of the following third information: the data volume which is cached in the first cache space and is not written into the first logical partition and corresponds to the first logical partition; the capacity of the remaining space of the first cache space corresponding to the first logical partition; the remaining capacity of the storage device; the remaining capacity of the first logical partition; the first information includes at least one item of second information for determining, by the computing device, a number of second IO commands located within the second address range issued to the storage device. Through the design, the computing equipment can acquire the related information of the first cache space corresponding to the first logical partition, so that the speed of issuing the IO command by the first logical partition can be controlled.

In one possible design, the first information further includes an IO command that times out in the first cache space corresponding to the first logical partition; and the overtime IO command in the first cache space corresponding to the first logical partition is used for retransmitting the overtime IO command to the storage equipment. By the design, the computing equipment can be enabled to know which IO commands need to be retransmitted, and IO commands ending due to write missing timeout are avoided.

In one possible design, the first information further includes a delay time length corresponding to the IO command to be retransmitted, which is not successfully cached in the first cache space, where the delay time length is used for retransmitting the IO command to be retransmitted to the storage device after the waiting time length reaches the delay time length. By the design, continuous data issuing can be avoided.

In one possible design, the processor is specifically configured to: if a first IO command corresponding to the first address is not found in the first cache space, data writing to the first logical partition is suspended, first information comprising a result of failure in data writing to the first address and the second address is sent to the computing device, the second address is identical to the first address, and the first information is used for the computing device to issue the first IO command corresponding to the first address. Through the design, when the data is not successfully written into the first address, the IO command corresponding to the first address of the data to be written currently can be acquired as soon as possible, so that the data writing efficiency can be improved.

In a third aspect, the present application provides a storage device, the storage device including a storage medium, a cache, and a storage controller as in any one of the possible designs of the second aspect, the storage medium including a plurality of logical partitions, the plurality of logical partitions including a first logical partition, the cache including a plurality of cache spaces, the plurality of cache spaces including a first cache space, the first cache space being a cache space in a cache in the storage device for caching IO commands for accessing the first logical partition; the storage controller is used for searching an IO command corresponding to a current initial writing address of the first logical partition from the first cache space, and writing data carried by the IO command corresponding to the searched initial writing address into the first logical partition.

In the embodiment of the application, the address where the data is actually written is specified in the IO command by the computing device, and the data is written to the specified address where the first logical partition is located by the storage device according to the IO command, so that the writing behavior of the first logical partition is consistent with that of the traditional SSD, and the concurrent writing of the data to the storage device can be realized without changing the software architecture of the system, thereby reducing unnecessary complexity and workload.

In one possible design, the data in the first logical partition is written by sequential writing.

In one possible design, the storage device is a partition namespace solid state disk, ZNS SSD.

In a fourth aspect, a data processing method is applied to a computing device, the method comprising: acquiring a first address of a first logical partition in storage equipment, wherein the first address is a current initial write-in address of the first logical partition; the first logical partition is any one of a plurality of logical partitions included in the storage device; at least one first input/output IO command is sent to the storage device, wherein an access address corresponding to each first IO command is located in a first address range, and the first address range is a logic address range determined according to a first address and a preset first length in a first logic partition; and receiving first information sent by the storage device in response to at least one first IO command, wherein the first information is used for the computing device to issue the IO command corresponding to the second address.

In one possible design, the first length is determined according to a size of a first cache space, where the first cache space is a cache space in a cache in the storage device for caching IO commands for accessing the first logical partition.

In one possible design, before the first address of the first logical partition in the storage device is obtained, the method further comprises: the size of the first buffer space is configured.

In one possible design, the first information includes a result of successfully writing the first data to the first address and a second address, and the second address is different from the first address, and after receiving the first information sent by the storage device in response to the at least one first IO command, further includes: and sending at least one second IO command to the storage device according to the result of successfully writing the first data into the first address and the second address, wherein the at least one second IO command comprises a second IO command corresponding to the second address.

In one possible design, the current starting write address of the first logical partition is a second address, and the access address corresponding to each second IO command in the at least one second IO command is located in a second address range, where the second address range is a logical address range determined according to the second address and the first length in the first logical partition.

In one possible design, the current initial write address of the first logical partition is a third address, and the access address corresponding to each second IO command is located in a second address range, where the second address range is a logical address range determined according to the third address and the first length in the first logical partition.

In one possible design, the first information further includes at least one of the following second information: the state code of the first cache space corresponding to the first logical partition indicates that the first cache space is full; the remaining capacity of the storage device. The method further comprises the steps of: and determining whether to continue issuing a second IO command located in a second address range to the storage device according to at least one item of second information included in the first information.

In one possible design, the first information further includes at least one of the following third information: the data volume which is cached in the first cache space and is not written into the first logical partition and corresponds to the first logical partition; the residual capacity of the first cache space corresponding to the first logical partition; a remaining capacity of the storage device; the remaining capacity of the first logical partition; the method further comprises the steps of: and if the second IO commands in the second address range are determined to be continuously issued to the storage device, determining the number of the second IO commands in the second address range issued to the storage device according to at least one item of second information included in the first information.

In one possible design, the first information further includes an IO command that times out in a first cache space corresponding to the first logical partition. The method further comprises the steps of: the timeout IO command is resent to the storage device.

In one possible design, the first information further includes a delay time length corresponding to the IO command to be retransmitted that is not successfully buffered in the first buffer space. The method further comprises the steps of: and retransmitting the IO command to be retransmitted to the storage device after the waiting time length reaches the delay time length.

In one possible design, sending at least one first input output, IO, command to a storage device includes: at least one first IO command is concurrently sent to the storage device.

In one possible design, the first information includes a result of a failure to write the first data to the first address and a second address, the second address being the same as the first address; after receiving the first information sent by the storage device in response to the at least one first IO command, the method further includes: and according to the result of the failure of writing the first data into the first address and the first address, sending a first IO command corresponding to the first address to the storage device.

The beneficial effects corresponding to the designs in the fourth aspect are specifically referred to the beneficial effects corresponding to the designs in the first aspect, and will not be repeated here.

In a fifth aspect, the present application provides a data processing method applied to a storage device or a storage controller in a storage device, the method comprising: receiving at least one first input/output IO command sent by a computing device, wherein an access address corresponding to each first IO command is located in a first address range, and the first address range is a logic address range determined according to a first address and a preset first length in a first logic partition; storing at least one first IO command in a first cache space; determining a current initial write address in the first logical partition as a first address, and selecting and executing a corresponding command from at least one first IO command according to the first address; and sending first information to the computing equipment, wherein the first information is used for the computing equipment to send the IO command corresponding to the second address.

In one possible design, before receiving the at least one first input-output IO command sent by the computing device, the method further includes: the size of the first buffer space is configured.

In one possible design, a corresponding command is selected and executed from at least one first IO command according to a first address; transmitting first information to a computing device, comprising: if a first IO command corresponding to the first address is found from the first cache space, the first IO command corresponding to the first address comprises first data, the first data is written into the first address, first information comprising a result of successfully writing the first data into the first address and a second address is sent to the computing device, the second address is different from the first address, and the first information is used for the computing device to issue the IO command corresponding to the second address.

In one possible design, after storing the at least one first IO command in the first cache space, further comprising: setting a first duration for each first IO command in at least one first IO command, and deleting the overtime first IO command from the first cache space after the storage duration of any first IO command in the first cache space exceeds the first duration.

In one possible design, after storing the at least one first IO command in the first cache space, further comprising: receiving at least one second IO command sent by the computing device, wherein the at least one second IO command comprises second IO commands corresponding to second addresses, and an access address corresponding to each second IO command is located in a second address range; if the current initial write address of the first logical partition is a second address, the second address range is a logical address range determined according to the second address and the first length in the first logical partition; or if the current initial write address of the first logical partition is the third address, the second address range is a logical address range determined according to the third address and the first length in the first logical partition.

In one possible design, the first information further includes at least one of the following second information: the state code of the first cache space corresponding to the first logical partition indicates that the first cache space is full; a remaining capacity of the storage device; the first information includes at least one item of second information for the computing device to determine whether to continue issuing second IO commands located within a second address range to the storage device.

In one possible design, the first information further includes at least one of the following third information: the data volume which is cached in the first cache space and is not written into the first logical partition and corresponds to the first logical partition; the capacity of the remaining space of the first cache space corresponding to the first logical partition; a remaining capacity of the storage device; the remaining capacity of the first logical partition; the first information includes at least one item of second information for the computing device to determine a number of second IO commands issued to the storage device that are located within a second address range.

In one possible design, the first information further includes an IO command that times out in a first cache space corresponding to the first logical partition; and the overtime IO command in the first cache space corresponding to the first logical partition is used for retransmitting the overtime IO command to the storage device.

In one possible design, the first information further includes a delay duration corresponding to the IO command to be retransmitted that is not successfully buffered in the first buffer space, where the delay duration is used for retransmitting the IO command to be retransmitted to the storage device after the waiting duration reaches the delay duration.

In one possible design, a corresponding command is selected and executed from at least one first IO command according to a first address; transmitting first information to a computing device, comprising: if the first IO command corresponding to the first address is not found in the first cache space, the writing of data to the first logical partition is paused, first information comprising a result of failure in writing the data to the first address and the second address is sent to the computing device, the second address is identical to the first address, and the first information is used for the computing device to issue the first IO command corresponding to the first address.

The beneficial effects corresponding to the designs in the fifth aspect are specifically referred to the beneficial effects corresponding to the designs in the second aspect, and the detailed description is not repeated here.

In a sixth aspect, embodiments of the present application provide a data processing system, including the computing device according to each of the designs in the first aspect and the storage device according to the first aspect.

In a seventh aspect, embodiments of the present application provide a computer-readable storage medium, in which a computer program is stored, which when run on a computer causes the computer to perform the method described in the designs in the fourth aspect or to perform the method described in the designs in the fifth aspect.

In an eighth aspect, embodiments of the present application provide a computer program product, which when run on a computer, causes the computer to perform the method of the designs in the fourth aspect or to perform the method of the designs in the fifth aspect.

The beneficial effects corresponding to the designs in the sixth aspect to the eighth aspect are specifically referred to the beneficial effects corresponding to the designs in the fourth aspect or the fifth aspect, and are not repeated here.

Drawings

FIG. 1 illustrates a NAND Flash grain schematic;

FIG. 2 illustrates a schematic diagram of an SMR SSD in comparison to a conventional SSD;

FIG. 3 illustrates a schematic diagram of a ZNS SSD in cooperation with a host for writing data;

FIG. 4 schematically illustrates a system architecture to which embodiments of the present application are applicable;

FIG. 5 is a schematic flow chart of a data processing method according to an embodiment of the present application;

FIG. 6 illustrates a single IO command write schematic;

fig. 7 is a schematic structural diagram of an apparatus according to an embodiment of the present application.

Detailed Description

The data processing scheme in the application can be applied to a system comprising a device with a data storage function and a computing device, wherein the device with the data storage function can be a storage device with only the data storage function, such as a memory, or an electronic device with the data storage function and also with other functions. The electronic device may be a portable electronic device that includes functionality such as a personal digital assistant and/or a music player, such as a cell phone, tablet computer, wearable device (e.g., smart watch) with wireless communication functionality, or an in-vehicle device. Exemplary embodiments of portable electronic devices include, but are not limited to, piggy-backOr other operating system. The portable electronic device may also be a portable electronic device such as a Laptop computer (Laptop) having a touch sensitive surface, e.g. a touch panel. It should also be appreciated that in other embodiments of the present application, the electronic device described above may also be a desktop computer having a touch-sensitive surface (e.g., a touch panel). The following embodiments are described in terms of systems including storage devices and computing devices.

The memory may be, for example, volatile memory, non-volatile memory, or may include both volatile and non-volatile memory. But also a hard disk, such as an SSD, composed of these volatile memories or nonvolatile memories. Among other things, the volatile memory may be random access memory (random access memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). The nonvolatile memory may be read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), or electrically erasable PROM

(electrically EPROM, EEPROM) or flash memory. It should be noted that the memory described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

For ease of understanding, the following description will take the storage device as an SSD as an example. It should be understood that the "SSD" appearing hereinafter may be replaced by any other storage device having similar characteristics to the SSD, which is not limited in this application.

The SSD may include a memory controller and a storage medium, wherein the storage medium is formed by a plurality of NAND Flash particles arranged in rows and columns, and the plurality of NAND Flash particles are communicated to the memory controller through a bus. As shown in fig. 1, each NAND Flash granule is composed of a plurality of Die, each Die having a plurality of blocks (blocks), each Block having a plurality of pages (pages). The capacity of a single Die is typically 8GB/16GB/32GB or greater, and if a single NAND Flash Die includes 8 dies, the capacity of a single NAND Die can be 64GB/128GB/256GB or greater.

Currently, in order to improve performance of various aspects of the conventional SSD, an SSD employing a Shingled Magnetic Recording (SMR) technology and a partition naming space (ZNS) technology is proposed, and two SSDs, an SMR SSD and a ZNS SSD, are described below.

First, SMR SSD.

As shown in fig. 2, the SMR SSD partially overlaps the data tracks on the disk, just like the tiles on the roof, and this technique is called a shingled magnetic recording technique, and the SMR SSD employing this technique has very small variations in manufacturing process as compared with the conventional hard disk, but can improve the storage density of the disk and reduce the cost per unit capacity. The read behavior of the SMR SSD is the same as that of a conventional hard disk, but the write behavior of the SMR SSD is greatly changed, namely random write and in-place update write are not supported any more, and only sequential additional write can be performed, because the newly written tracks on the SMR SSD cover all the tracks overlapped with the newly written tracks, thereby destroying the data on the newly written tracks.

The hard disk is divided into concentric tracks, and a certain interval is arranged between the tracks to protect the tracks. The magnetic head of the hard disk is positioned above the disk recording medium and comprises a write head for writing and a read head for reading, and the write head and the read head are independent components. To write data on a disk requires the write head to apply a relatively strong magnetic field to change the recording on the disk, which further requires the write head to be large enough to produce the required write field strength. Thus, if the tracks do not overlap, the number of tracks per inch on the disk that can be accommodated is determined by the width of the write head.

Shingled writing takes advantage of the fact that the magnetic field strength required for disc reading is lower than the magnetic field strength required for writing, the track width required for disc reading can be smaller than the track width required for writing, and writing of data on SMR SSD is written by partially overlapping the previous track while leaving enough space for the narrower read head to read the data of the previous track.

SMR discs divide the track into a number of bands (bands), i.e. contiguously writable zones of sequential tracks, each zone constituting a basic unit that needs to be written sequentially. Band is a physical concept on the SMR disk, and its corresponding logical concept is "zone", which is a sequential write area of the SMR disk that can be seen by upper software.

Second, ZNS SSD.

ZNS is a newly proposed way for a host and disk to mate inside NVMe. The ZNS disk has the following characteristics:

(1) As shown in fig. 3, the entire LBA space of the ZNS SSD is divided into a plurality of zones, and a single zone is, for example, 4MB to 4GB in size, and is somewhat similar to one area of the SMR SSD division.

(2) In a single zone, the host can only write data sequentially, cannot write data randomly, and can read data randomly.

(3) When a certain zone is written from head to tail and then data is written again, the whole zone must be erased first, and then the data can be written from head to tail in sequence, in general, one zone can be corresponding to one or more physical blocks on NAND Flash.

(4) The data of the whole zone are eliminated together, the moving of effective data is not needed, and the disk has no write amplification. The conventional solid-state disk is to find the physical block with the most invalid data, remove the valid data, and erase the block, which involves the removal of the valid data, so that there is a certain write amplification, and the write amplification is eliminated by the ZNS cooperation mode.

The following examples of the present application are presented based on a second ZNS SSD. The method of sequentially writing data by the ZNS SSD requires host to write data serially, and the performance is relatively low, so this concurrent writing method of partition additional writing (zone application) is introduced. As shown in table 1, the concurrent writing manner of the zone application can support the concurrent writing of multiple write commands in a single zone, and the matching process of host and hard disk in the writing mode is as follows: when a host issues a write command to a certain zone in a ZNS SSD, the write command carrying content comprises a starting LBA of the zone, the number of LBAs occupied by data and the data, after the ZNS SSD receives the IO command, the ZNS SSD autonomously determines the position of the data carried by the IO command, which is actually written into the zone, after the ZNS SSD completes writing operation, the starting address of the position of the zone, which is actually written into the data, is sent to a host, and the host records the address of the actually written data.

Table 1 exemplarily shows the content carried by the IO command and response during concurrent writing of zone application:

the terms in Table 1 are first described:

cmd# refers to a plurality of write commands issued concurrently;

ZSBA refers to the start address of the zone;

starting LBA refers to the starting address of the zone carried by each command;

# LBAs refers to the number of LBAs corresponding to the command;

the assigned LBA refers to the starting LBA actually allocated by the SSD to the command, and the LBA is returned to host;

the write pointer refers to the write pointer corresponding to the zone (when writing the command);

the write pointer (after Cmd) refers to the write pointer corresponding to the zone (at the time the command is completed).

This way of mating a host with a ZNS SSD allows host to issue multiple IO commands concurrently for a single zone, but in order to achieve this way of mating a host with a ZNS SSD as described above, it is necessary to migrate the flash translation layer (Flash Translation Layer, FTL) in a conventional SSD from inside the SSD to the host side of the upper layer, that is, it is necessary to redesign the software architecture of the storage system, and it is necessary that additional software is not needed by the conventional drive, thereby introducing unnecessary complexity and additional workload.

The host is required to record the address actually written by the data carried by each IO command, and the host is required to maintain the mapping relation between the data and the storage address, so that unnecessary complexity and extra workload are introduced.

In view of this, the present application proposes a data processing method for implementing concurrent writing of data to a solid state disk without increasing workload of a host.

The present application will be described in further detail with reference to the accompanying drawings. In the description of the present application, "at least one" means one or more, wherein a plurality means two or more. In view of this, the term "plurality" may also be understood as "at least two" in embodiments of the present invention. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/", unless otherwise specified, generally indicates that the associated object is an "or" relationship. And, unless otherwise specified, references to "first," "second," etc. in the embodiments herein are for distinguishing between multiple objects and not for defining the order, timing, priority, or importance of the multiple objects.

Fig. 4 schematically illustrates a system architecture suitable for use in embodiments of the present application, where the system architecture includes a computing device 100 and a storage device 200, as shown in fig. 4.

The computing device 100 is configured to issue an input/output (IO) command to the storage device, and receive a response corresponding to the IO command, where the IO command carries data to be written and a storage address specified for the data to be written, and the response corresponding to the IO command includes first information, where the first information is used by the computing device to issue an IO command corresponding to a next address. Computing device 100 is a device having data processing or computing capabilities, such as a host computer, computing device 100 may include a processor and a communication interface, where the processor may include, but is not limited to, a central processing unit (central processing unit, CPU), a general purpose processor or other processor, etc.

The storage device 200 may include a storage controller 210, a cache 220, and a storage medium 230. Communication between computing device 100 and memory controller 210, and between memory controller 210 and storage medium 230 may be via a bus connection as shown in FIG. 4, or may be via an interconnect or other means.

Wherein, the buffer 220 includes at least one buffer space for buffering an IO command, and the IO command is used to instruct the memory controller 210 to write data into the memory unit. The storage medium 230 may be divided into at least one logical space (or partition), each of which is referred to as a storage unit, which corresponds to the cache space one by one. The storage unit in the embodiment of the present application may be, for example, a zone in a ZNS SSD, a namespace (namespace) in a NVME SSD, etc., and in the following embodiment, the storage unit is taken as the zone for illustration, which will not be described in detail.

The storage controller 210 is configured to receive an IO command sent by the computing device 100, store the IO command in a cache, determine, for a storage unit, an address of a location pointed to by a write pointer of the storage unit, then search, in a cache space corresponding to the storage unit, for the IO command carrying the address of the location pointed to by the write pointer, and then write data carried by the found IO command into the storage unit.

It should be noted that each component shown in fig. 4 may be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and/or application specific integrated circuits, which are not described herein.

The following describes a specific implementation of the data processing method in the present application by means of a specific embodiment in conjunction with the system architecture shown in fig. 4.

Fig. 5 is a schematic flow chart illustrating a data processing method according to an embodiment of the present application, where in the embodiment of the present application, steps performed by a storage device may also be performed by a storage controller, as shown in fig. 5, and the method includes:

s501, the computing device obtains a first address of a first logical partition in the storage device.

The first address is the current initial writing address of the first logical partition, and can be understood as the address where the first data is not written in the first logical partition and the subsequent data can be written in the first logical partition. The first address, the second address, the third address, and the like in this embodiment are Logical Block Addresses (LBAs), and will not be described in detail later.

In an embodiment of the present application, when the storage device includes a plurality of logical partitions, the first logical partition in S501 may be any one of the plurality of logical partitions included in the storage device. It should be understood that, in the embodiment of the present application, the case where the computing device writes data to one logical partition (i.e., the first logical partition) in the storage device is taken as an example, and if the storage device includes multiple logical partitions, the solution of the embodiment of the present application may also be applicable to a scenario of writing data to each logical partition in the storage device.

The storage device may further include a cache including one or more cache spaces therein, the cache including a first cache space therein, the first cache space being a cache space in the cache in the storage device for caching IO commands for accessing the first logical partition. When the storage device comprises a logical partition (i.e., a first logical partition), the size of the buffer space corresponding to the first logical partition is the size of the buffer of the storage device, or may be larger than the size of the buffer of the storage device; when the storage device includes a plurality of logical partitions, the sum of the buffer spaces corresponding to all the logical partitions may be equal to or greater than the size of the buffer. If the storage device detects that the cache is full, a corresponding error code (or referred to as a status code) may be returned to the computing device to prompt the computing device to delay retrying, i.e. delay reissuing the IO command that cannot be stored in the cache due to the full cache.

In one possible implementation, the computing device does not configure the size of the corresponding cache space for each logical partition included in the storage device, and the default cache is shared by all logical partitions, that is, the cache space corresponding to a single logical partition is not constrained in size, but is constrained in size by the cache of only one storage device.

In another possible implementation, before the computing device obtains the first address of the first logical partition in the storage device, the computing device may further configure a corresponding size of the cache space for each logical partition included in the storage device, respectively.

In one example, taking a computing device as a host, the storage device is a ZNS SSD, which includes four first logical partitions, i.e., one zone, i.e., the ZNS SSD includes four zones. In general, the memory of the ZNS SSD may be used as a cache for each zone, for example, 2GB of memory, metadata overhead is 0.5GB, and the remaining 1.5GB of memory may be used as a cache, so that data in the cache space does not need to be protected electrically. The host can configure the size of the buffer space corresponding to each zone for four zones according to actual needs. The size of the buffer space can be configured when the host creates a zone, or a set feature command can be issued to realize that the size of the buffer space is configured for the designated zone independently.

According to the implementation mode, the computing device configures the size of the corresponding cache space for each logical partition, for example, the size of the first cache space is configured for the first logical partition, and the size of the second cache space is configured for the second logical partition, so that the size of each cache space is configured as required, the size of the cache space determines how large address range the computing device can write out of order, and therefore the problem that the multiple logical partitions occupy the space in the cache due to sharing the cache under the condition of writing data concurrently can be avoided, and the concurrent writing capacity of each logical partition is higher.

S502, the computing device sends at least one first IO command to the storage device. Accordingly, the storage device receives at least one first IO command sent by the computing device.

In particular, the computing device may send an indication of a first IO command to a storage controller in the storage device.

The access address corresponding to each first IO command in the at least one first IO command is located in a first address range, and the first address range is a logic address range determined according to the first address and a preset first length in the first logic partition. There may be a field in the first IO command to indicate the logical address of the memory device to which the first IO command accesses.

In one possible implementation manner, the first length is determined according to a size of a first cache space, where the first cache space is a cache space in a cache in the storage device for caching an IO command for accessing the first logical partition, and the first address range is an address range with the first address as a starting address and a size of the first cache space corresponding to the first logical partition as a length.

For one logical partition, the computing device may determine a first address range based on an address to which the write pointer is currently directed and a size of a first cache space corresponding to the first logical partition, where the first address range is an LBA range, and IO commands falling within the first address range may be stored in the first cache space out of order, and generally, the computing device does not issue IO commands exceeding the first address range, because the IO commands exceeding the first address range are stored in the first cache space first even if issued to the storage device, when data is sequentially written to the first logical partition, the IO commands having access addresses exceeding the first address range have not been written to, and the IO commands having access addresses exceeding the first address range have been timed out. In addition, the IO command with the access address in the first address range is allowed to be overwritten as long as the IO command is not written into the first logic partition, and the IO command can be overwritten by the newly issued IO command with the same address. For example, taking the example that the access address carried by the IO command Q is 70M, the IO command Q is not yet written into the first logical partition, the computing device issues the IO command P, and the access address carried by the IO command P is also 70M, so that the IO command Q is covered by the IO command P.

The first address range is described below in connection with examples.

Taking the computing device as host and the first logical partition as zone1 as an example, the size of the first cache space configured by host as zone1 is 50M, the current address pointed by the write pointer is P, then the first address range is P-p+50mb, and assuming that the current address pointed by the write pointer is 10M, then the first address range is in the range of 10-60M. The computing device may send at least one first IO command with an access address in the range of 10-60M to the storage device.

The computing device may issue a first IO command to the storage device, or may issue a plurality of first IO commands, where an access address of each first IO command is in a range of 10 to 60M. When the computing device issues the plurality of first IO commands, the plurality of first IO commands may be sent to the storage device concurrently, thereby implementing concurrent writing of data to the storage device.

S503, the storage device stores at least one first IO command in a first cache space corresponding to the first logical partition.

Specifically, a memory controller in a memory device stores at least one first IO command in a first cache space.

Because the computing device may issue multiple first IO commands to the storage device concurrently, and may issue the multiple first IO commands out of order, as the number of first IO commands stored in the first cache space increases, the storage controller may search for the first IO commands from the first cache space according to the address sequence in the first logical partition, and write the data carried in the searched first IO commands into the first logical partition, for some reasons, some first IO commands may stay in the first cache space for a long time, so that the opportunity of scrubbing is not obtained, for example, the reason that the command P affects the opportunity that the command P cannot be scrubbed in the first cache space may be that the processing speed of the storage controller is slow, or other first IO commands corresponding to addresses before the access address corresponding to the command P are not issued to the storage device, so that other first IO commands after the access address corresponding to the command P in the first cache space are caused to not be written into the first logical partition. For this purpose, in one possible implementation manner, after the storage controller stores at least one first IO command in the first cache space, the storage controller may further set a first duration for each of the at least one first IO command, and after the storage duration of any one first IO command in the first cache space exceeds the first duration, delete the timeout first IO command from the first cache space. Thus, the first IO command overtime can be avoided from consuming cache resources.

In one possible implementation manner, after the storage duration of any first IO command in the first cache space exceeds the first duration, the storage controller may further return a status code for sending the timeout of the first IO command to the computing device, so as to prompt the computing device to delay retransmitting the timeout first IO command. Further, the storage controller may also send a delay duration corresponding to the IO command that needs to be retransmitted by delaying, for example, the delay duration is 5ms, and then the computing device may resend the first IO command that is overtime to the storage controller after 5 ms. Optionally, the status code of the timeout of the first IO command and the delay time corresponding to the IO command that needs to be delayed and retransmitted may be separately sent to the computing device by the storage controller, or may be sent to the computing device together with the first information when the first information needs to be sent.

S504, the storage device determines the current initial write address of the first logical partition as the first address.

In implementations, a memory controller determines a current starting write address of a first logical partition as a first address.

S505, the storage device selects and executes a corresponding command from at least one first IO command according to the first address.

In a specific implementation, the memory controller selects a corresponding command from at least one first IO command according to the first address.

S506, the storage device responds to at least one first IO command and sends first information to the computing device, wherein the first information is used for the computing device to send the IO command corresponding to the second address. Accordingly, the computing device receives first information sent by the storage device in response to the at least one first IO command.

Specifically, the storage device searches whether a first IO command corresponding to the first address is found in the first cache space.

In one possible implementation manner, if the first IO command corresponding to the first address is found in the first cache space, where the first IO command corresponding to the first address includes first data, the first data is written into the first address, and first information including a result of successfully writing the first data into the first address and a second address is sent to the computing device, where the second address is different from the first address, and the second address is used for the computing device to issue the IO command corresponding to the second address, so that the storage device continues to operate in a manner of writing data sequentially.

In one embodiment, the second address may be an address of a location of the first unwritten data that is subsequent to the first address and that is different from an access address corresponding to the IO command in the first cache space. The difference between the second address and the access address corresponding to the IO command in the first cache space may also be understood as: and the IO command corresponding to the first address does not exist in the first cache space corresponding to the first logical partition. When the storage device sends the first information to the computing device, any data is not written in the second address in the first logical partition, and the IO command corresponding to the second address is not found in the first buffer space corresponding to the first logical partition, so that the second address is the next address which the storage device expects to receive the IO command, and the computing device can issue the IO command corresponding to the second address which the storage device expects to receive at once by carrying the second address in the first information.

After the memory controller in the memory device writes the first data to the first address in the first logical partition, there may be two cases, where the first address is the current starting write address of the first logical partition; in the second case, the third address is the current initial write address of the first logical partition, and the second address is different from the third address. For these two cases, the subsequent processing of the storage device is different, and is described as follows:

In case one, the second address is the current starting write address of the first logical partition. That is, after the first address writes the first data, the write pointer points to the second address, where the second address is the address of the first unwritten data, and the IO command corresponding to the second address does not exist in the first buffer space, so the computing device is required to issue the IO command corresponding to the second address.

In one possible implementation, after the computing device receives the first information sent by the storage device in response to the at least one first IO command, the computing device may further determine the at least one second IO command based on a result of successfully writing the first data to the first address and the second address. The at least one second IO command comprises second IO commands corresponding to second addresses, the access address corresponding to each second IO command is located in a second address range, and the second address range is a logic address range determined according to the second address and the first length in the first logic partition.

In this case two, the second address range is an address range with the second address as a start address and the size of the first buffer space corresponding to the first logical partition as a length, and the second address is an address to which the write pointer points when the memory controller successfully writes data at the first address. The specific implementation of the second address range may refer to the related content of the first address range, where the difference is that: the first address range has a first address at its start address and the second address range has a second address at its start address, so that the second address range is slid backward relative to the first address range by the length of the first data written to the first address over the entire address range.

In the second case, the third address is the current initial write address of the first logical partition, and the second address is different from the third address. That is, after the first address writes the first data, the write pointer points to the third address, where the third address is the address of the first unwritten data, in this case, the first buffer space has the IO command corresponding to the third address, and no IO command corresponding to the second address, so the computing device is required to issue the IO command corresponding to the second address.

In one possible implementation, after the computing device receives the first information sent by the storage device in response to the at least one first IO command, the computing device may further determine the at least one second IO command based on a result of successfully writing the first data to the first address and the second address. The at least one second IO command comprises second IO commands corresponding to second addresses, the access address corresponding to each second IO command is located in a second address range, and the second address range is a logic address range determined according to the third address and the first length in the first logic partition.

In this case two, the second address range is an address range with a third address as a start address and the size of the first buffer space corresponding to the first logical partition as a length, and the third address is an address to which the write pointer points when the memory controller successfully writes data at the first address. The specific implementation of the second address range may refer to the related content of the first address range, where the difference is that: the start address of the first address range is the third address and the start address of the second address range is the third address, and therefore the second address range is slid backward relative to the first address range by the length of the first data written to the first address over the entire address range.

For example, the first logical partition includes a plurality of LBAs, namely, LBA0, LBA1, LBA2, LBA3 … … LBAn, each LBA has a length of 4k, and a command 1, a command 2 and a command 3 are stored in a first buffer space (with a size of 40 k) corresponding to the first logical partition, where the command 1 is used to instruct writing of 8k of data 1 into LBA0 and LBA1, the command 2 is used to instruct writing of 4k of data 1 into LBA2, and the command 3 is used to instruct writing of 8k of data 3 into LBA5.

Taking the first address as a starting address LBA0 of the first logical partition as an example, first, the write pointer points to the first address (i.e. LBA 0), the computing device determines that an address range 1 is LBA0 to LBA10 according to the LBA0 pointed by the write pointer and the size of the first buffer space being 40k, and the computing device issues an IO command with an access address in the range of LBA0 to LBA10 to the storage device.

The storage controller may find the IO command corresponding to LBA0 from the first cache space, i.e. find command 1, write data 1 to LBA0 and LBA1, and return a response 1 to the computing device, where the response 1 includes that data 1 has been successfully written to LBA0 and LBA1, and an access address (i.e. LBA 3) corresponding to the IO command that is expected to be received.

And then, the write pointer points to a third address, namely an IO command corresponding to the address (namely LBA 2) of the next unwritten data, the computing device determines that the address range 2 is LBA 2-LBA 12 according to the LBA2 pointed by the write pointer and the size of the first cache space is 40k, and the computing device issues the command with the access address in the range of LBA 2-LBA 12 to the storage device.

The storage controller may look up the IO command carrying LBA2 from the first cache space, i.e. find command 2, and write data 2 to LBA2, where data 1 is actually stored in LBA 2. Then, the write pointer points to the address (i.e., LBA 3) of the next unwritten data, the storage controller searches the IO command corresponding to LBA3 from the first cache space, but does not find the IO command corresponding to LBA3, and waits for the computing device to issue the IO command corresponding to LBA3 to the storage device.

In one possible embodiment, the first information may further include at least one of the following second information in addition to the result of successfully writing the first data to the first address and the second address: the state code of the first cache space corresponding to the first logical partition indicates that the first cache space is full; the remaining capacity of the storage device. The method further comprises the steps of: and determining whether to continue issuing a second IO command located in a second address range to the storage device according to at least one item of second information included in the first information. In this embodiment, the computing device may be enabled to know in time when the first cache space is full or the remaining capacity is zero, and no data is issued to the first logical partition any more, so that a backpressure mechanism may be formed, and unlimited issuing of write data by the computing device to the first logical partition is avoided.

Further, the first information further includes at least one of the following third information: the data volume which is cached in the first cache space and is not written into the first logical partition and corresponds to the first logical partition; the residual capacity of the first cache space corresponding to the first logical partition; a remaining capacity of the storage device; the remaining capacity of the first logical partition; the method further comprises the steps of: and if the second IO commands in the second address range are determined to be continuously issued to the storage device, determining the number of the second IO commands in the second address range issued to the storage device according to at least one item of second information included in the first information. Therefore, the computing device can acquire the related information of the first cache space corresponding to the first logical partition, and the speed of issuing the IO command by the first logical partition can be controlled.

Further, the first information further includes an IO command that is timed out in the first cache space corresponding to the first logical partition. The method further comprises the steps of: the timeout IO command is resent to the storage device. Therefore, the computing device can know which IO commands need to be retransmitted, and IO commands ending in the write-missing timeout are avoided.

Still further, the first information may further include a delay duration corresponding to the IO command to be retransmitted that is not successfully buffered in the first buffer space. The method further comprises the steps of: and retransmitting the IO command to be retransmitted to the storage device after the waiting time length reaches the delay time length. Thus, the continuous data issuing can be avoided.

The buffer capacity of the first buffer space in the storage device may be represented in the identify, for the data amount, the size of the first buffer space may be represented by bits in MB or KB, assuming that the unit is 1MB, the size of the first buffer space may be represented by 8 bits, and the maximum may be represented by 256MB; if the unit is 10MB, the maximum can represent 2560MB; if the represented capacity is exceeded, it is directly represented by the value of full F.

In another possible implementation manner, if the storage device does not find the first IO command corresponding to the first address from the first cache space, writing data to the first logical partition is suspended, and first information including a result of failure to write data to the first address and the second address is sent to the computing device, where the second address is the same as the first address, and the first information is used by the computing device to issue the first IO command corresponding to the first address.

Through the above embodiment, the storage controller selects the command matching with the current write pointer from the first cache space corresponding to the first logical partition to write data into the first logical partition, if the storage device does not receive the IO command corresponding to the address pointed by the write pointer, that is, the IO command corresponding to the address pointed by the write pointer cannot be found in the first cache space, the storage controller pauses writing data into the first logical partition, and can periodically find the IO command corresponding to the address pointed by the write pointer from the first cache space, and can also find the IO command corresponding to the address pointed by the write pointer in real time until the storage device receives the IO command corresponding to the address pointed by the write pointer, and write data into the address pointed by the write pointer. The write pointer then points to the next address in the order of addresses in the first logical partition.

According to the method, the computing device writes the data to the appointed address where the first logical partition is according to the IO command by designating the address where the data is actually written in the IO command, and the write behavior of the storage device is consistent with that of the traditional SSD, so that the data can be written to the storage device in parallel without changing the software architecture of the system, unnecessary complexity and workload can be reduced, furthermore, the computing device can issue IO commands of any address in the first address range, and issue IO commands corresponding to the second address as soon as possible according to the first information fed back by the storage device, so that the storage device can continue to operate in a mode of writing the data sequentially, consumption of cache resources can be reduced, and the efficiency of writing the data is effectively improved.

The data processing method of the present application will be described below with reference to fig. 6, taking the storage device as a ZNS SSD and the first logical partition as partition (zone) X as an example.

FIG. 6 illustrates a single IO command write schematic. As shown in fig. 6, zone X includes a region where writing is completed, a region (100M) where an IO command is being issued to the ZNS SSD, and a region where the IO command is temporarily not allowed to be issued, and the size of the first buffer space corresponding to zone X is 100MB.

As shown in fig. 6 (a), from the position pointed by the current write pointer P, push back 100MB, the IO commands in the address range of P to p+100MB may be issued to the ZNS SSD out of order, assuming that the buffer area corresponding to Zone X has received A, B, C, D, E these 5 commands, command a is a command (data desired to be written by the write pointer) that can be written directly by the disk to the N command AND Fl command Ash, B, C, D, E these 4 commands are data written out of order in the allowable range, temporarily buffered in the first buffer space, AND cannot be written into Zone. And the command G is a command that the ZNS SSD expects to receive the next address after finishing writing of the command A; only after the command G is received, the zone's sequential writing can be advanced, otherwise the following command can only be temporarily cached in the first cache space.

As shown in fig. 6 (b), after the command a is successfully written, the zone of the zone where data can be written into the disk slides back the range of the size of IO corresponding to the command a (CQE of the command a returns the offset of the next IO expected to be received, and this offset can be used as the starting LBA address of the host side allowed to issue IO: P); after the command A returns, host can issue any yet undelivered IO within 100MB of the backward P pointer; the issued IO is cached in the first cache space; only after the IO corresponding to G is issued to SSD, the sequential writing can continue to advance.

The write data flow for FIG. 6 is presented below, including the steps of:

s1, based on the position pointed by a write pointer P of zone X, randomly issuing write IO to a disk by a host in the range of P-P+100 MB, and assuming that 5 IO commands of A, B, C, D, E are issued currently, wherein an access address corresponding to the command A is the same as the address pointed by the write pointer.

S2, based on a write pointer P of the zone X, a storage controller of the ZNS SSD searches whether an IO command corresponding to an address pointed by the write pointer P exists in a first cache space corresponding to the zone X; since the address of the access corresponding to the command a is found to be the same as the address pointed by the write pointer, that is, the IO command corresponding to the address pointed by the write pointer P is the command a, the storage controller writes the data carried in the command a into the address pointed by the write pointer in zone X as shown in (a) of fig. 6.

S3, after the storage controller of the ZNS SSD completes the writing of the data carried by the command A, returning information corresponding to the command A to the host, wherein the information can comprise any one or more of the following contents: 1) The data corresponding to the command A is successfully written; 2) The address carried by the next IO command expected to be received, for example, the command G shown in (a) in fig. 6, is not issued to the ZNS SSD yet, so the command G cannot be found in the first cache space; 3) How much data which is successfully written is cached in the first cache space corresponding to the zone X; 4) How much data can be cached in the first cache space corresponding to the zone X; 4) The entire ZNS SSD can also buffer how much data.

S4, the host continues subsequent processing according to the information corresponding to the command A which is successfully written, for example, extracts an address corresponding to the next IO command expected to be received according to the information corresponding to the command A, and then slides backwards to allow the address range of the IO command to be issued; further, according to the data which can be cached in the first cache space, determining how many IO commands can be issued later; the method can also be used for caching data which is successfully written according to the amount of cached data in the first cache space corresponding to the zone X, and caching the amount of data in the whole ZNS SSD, so that the method can be used for subsequent expansion or statistics and is convenient for grasping relevant information of the first cache space corresponding to the zone X in real time.

In this embodiment of the present application, for a storage device that requires sequentially increasing data writing, the storage device selects an IO command matching with a current write pointer from a first cache space, and writes the data into the first logical partition, and a specific method may refer to the foregoing embodiment. However, for the storage device for writing data out of order, the difference from the above embodiment is that the storage device may arbitrarily select an IO command from the first cache space, write data into the first logical partition, for example, may select data carried by the IO command stored in the first cache space for the longest period of time, and write data into the first logical partition.

According to the foregoing method, fig. 7 is a schematic structural diagram of an apparatus provided in an embodiment of the present application, where the apparatus may be a computing device or a memory controller, and the computing device or the memory controller may also be a chip or a circuit, for example, a chip or a circuit that may be disposed in the computing device or the memory controller. As shown in fig. 7, the apparatus 700 may include a processor 701 and a communication interface 702, and the processor 701 and the communication interface 702 may be connected by a bus in particular.

When the apparatus 700 is a computing device, the processor 701 is coupled to a storage device through the communication interface 702. The processor 701 may implement the methods performed by the computing devices of fig. 5 described above.

When the apparatus 700 is a memory controller, the processor 701 is coupled to a computing device through the communication interface 702. The processor 701 may implement the method performed by the memory controller of fig. 5 described above.

According to the foregoing method, the embodiment of the application further provides a memory device, which may also be a chip or a circuit, for example, a chip or a circuit that may be disposed in the memory device. The storage device may refer to fig. 4 described above, and the storage device 200 includes a storage controller 210, a cache 220, and a storage medium 230, and the storage controller 210 may refer to fig. 7, where a processor 701 in the storage controller 210 is coupled to a computing device through a communication interface 702. The storage device may perform the methods performed by the storage device described above.

It should be appreciated that the processor 701 may be a chip. For example, the processor 701 may be a field programmable gate array (field programmable gate array, FPGA), an application specific integrated chip (application specific integrated circuit, ASIC), a system on chip (SoC), a central processing unit (central processor unit, CPU), a network processor (network processor, NP), a digital signal processing circuit (digital signal processor, DSP), a microcontroller (micro controller unit, MCU), a programmable controller (programmable logic device, PLD) or other integrated chip.

In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 701 or by instructions in the form of software. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor or in a combination of hardware and software modules in the processor 701. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a flash memory array, and the processor 701 reads information in the flash memory array, and performs the steps of the method in combination with hardware.

It should be noted that the processor 701 in the embodiments of the present application may be an integrated circuit chip with signal processing capability. In implementation, the steps of the above method embodiments may be implemented by integrated logic circuits of hardware in a processor or instructions in software form. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, or discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.

It will be appreciated that the memory in embodiments of the present application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

The concepts related to the technical solutions provided in the embodiments of the present application, explanation, detailed description and other steps related to the storage controller refer to the descriptions of these contents in the foregoing methods or other embodiments, and are not repeated herein.

According to the method provided by the embodiment of the application, the application further provides a computer program product, which comprises: computer program code which, when run on a computer, causes the computer to perform the method of the embodiment shown in fig. 5.

According to the method provided in the embodiment of the present application, there is further provided a computer readable storage medium storing a program code, which when run on a computer, causes the computer to perform the method in the embodiment shown in fig. 5. The storage medium may be any available medium that can be accessed by a computer, such as SSD, PCM, or the like.

According to a method provided by an embodiment of the present application, there is further provided a data processing system including a computing device, a memory controller, and a flash memory array as described in any one of the above.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

A computing device, comprising: a processor and a communication interface through which the processor is coupled to a storage device;

the processor is configured to:

acquiring a first address of a first logical partition in the storage device, wherein the first address is a current initial write-in address of the first logical partition; the first logical partition is any one of a plurality of logical partitions included in the storage device;

Transmitting at least one first input/output IO command to the storage device, wherein an access address corresponding to each first IO command is located in a first address range, and the first address range is a logic address range determined according to the first address and a preset first length in the first logic partition;

receiving first information sent by the storage device in response to the at least one first IO command; the first information is used for the computing device to issue IO commands corresponding to the second address.
The computing device of claim 1, wherein the first length is determined according to a size of a first cache space in a cache in the storage device to cache IO commands to access the first logical partition.
The computing device of claim 2, wherein the processor is further to:

and configuring the size of the first cache space.
The computing device of any of claims 1-3, wherein the first information includes a result of successfully writing first data to the first address and a second address, and the second address is different from the first address, the processor further to:

And sending at least one second IO command to the storage device according to the result of the successful writing of the first data into the first address and the second address, wherein the at least one second IO command comprises a second IO command corresponding to the second address.
The computing device of claim 4, wherein the first logical partition current starting write address is the second address, the access address corresponding to each of the at least one second IO command is within a second address range, the second address range being a logical address range in the first logical partition determined from the second address and the first length.
The computing device of claim 4, wherein the first logical partition current starting write address is the third address, and the access address corresponding to each of the second IO commands is within a second address range, the second address range being a logical address range determined in the first logical partition based on the third address and the first length.
The computing device of claim 5 or 6, wherein the first information further comprises at least one of the following second information:

A status code of the first cache space corresponding to the first logical partition, the status code indicating that the first cache space is full;

the remaining capacity of the storage device;

the processor is further configured to:

and determining whether to continue issuing the second IO command positioned in the second address range to the storage equipment according to at least one piece of second information included in the first information.
The computing device of claim 7, wherein the first information further comprises at least one third information of:

the data volume which is cached in the first cache space and is not written into the first logical partition and corresponds to the first logical partition;

the residual capacity of the first cache space corresponding to the first logical partition;

the remaining capacity of the storage device;

the remaining capacity of the first logical partition;

the processor is further configured to:

and if the second IO command in the second address range is determined to be continuously issued to the storage device, determining the number of the second IO commands in the second address range issued to the storage device according to at least one item of second information included in the first information.
The computing device of claim 8, wherein the first information further comprises an IO command to timeout in the first cache space corresponding to the first logical partition, the processor further to:

and retransmitting the overtime IO command to the storage device.
The computing device of any one of claim 7-9,

the first information further includes a delay time length corresponding to the IO command to be retransmitted, which is not successfully cached in the first cache space, and the processor is specifically configured to:

and retransmitting the IO command to be retransmitted to the storage equipment after the waiting time length reaches the delay time length.
The computing device of any of claims 1-3, wherein the first information includes a result of a failure to write first data to the first address and the second address, the second address being the same as the first address, the processor further to:

and according to the result of the failure of writing the first data into the first address and the first address, sending a first IO command corresponding to the first address to the storage equipment.
A storage controller comprising a processor and a communication interface, the processor coupled to a computing device through the communication interface;

The processor is configured to:

receiving at least one first input/output (IO) command sent by the computing device, wherein an access address corresponding to each first IO command is located in a first address range, and the first address range is a logic address range determined according to the first address and a preset first length in the first logic partition; the first logical partition is any one of a plurality of logical partitions included in the storage device;

storing the at least one first IO command in the first cache space;

determining the current initial write address of the first logical partition as a first address, and selecting and executing a corresponding command from the at least one first IO command according to the first address;

and sending first information to the computing equipment, wherein the first information is used for the computing equipment to send the IO command corresponding to the second address.
The memory controller of claim 12, wherein the first length is determined based on a size of a first cache space in a cache in the memory device to cache IO commands to access the first logical partition.
The storage controller of claim 13, wherein a size of the first cache space corresponding to the first logical partition is configured for the computing device.
The memory controller of any of claims 12-14, wherein the processor is specifically configured to:

if a first IO command corresponding to the first address is found out from a first cache space, the first IO command corresponding to the first address comprises first data, the first data is written into the first address, first information comprising a result of successfully writing the first data into the first address and a second address is sent to the computing device, the second address is different from the first address, and the first information is used for the computing device to issue the IO command corresponding to the second address.
The memory controller of any of claims 12-15, wherein the processor is further to:

setting a first duration for each first IO command in the at least one first IO command, and deleting a overtime first IO command from a first cache space after the storage duration of any first IO command in the first cache space exceeds the first duration.
The memory controller of any of claims 12-16, wherein the processor is further to:

receiving at least one second IO command sent by the computing device, wherein the at least one second IO command comprises second IO commands corresponding to the second addresses, and an access address corresponding to each second IO command is located in a second address range;

If the current initial write address of the first logical partition is the second address, the second address range is a logical address range determined according to the second address and the first length in the first logical partition; or if the current initial write address of the first logical partition is a third address, the second address range is a logical address range determined according to the third address and the first length in the first logical partition.
The memory controller of claim 17, wherein the first information further comprises at least one of the following second information:

a status code of the first cache space corresponding to the first logical partition, the status code indicating that the first cache space is full;

the remaining capacity of the storage device;

the first information includes at least one item of second information for determining, by the computing device, whether to continue issuing the second IO command located in the second address range to the storage device.
The memory controller of claim 18, wherein the first information further comprises at least one third information of:

the data volume which is cached in the first cache space and is not written into the first logical partition and corresponds to the first logical partition;

The capacity of the remaining space of the first cache space corresponding to the first logical partition;

the remaining capacity of the storage device;

the remaining capacity of the first logical partition;

the first information includes at least one item of second information for determining, by the computing device, a number of second IO commands located within the second address range issued to the storage device.
The memory controller of claim 19, wherein the first information further comprises an IO command that times out in the first cache space corresponding to the first logical partition; and the overtime IO command in the first cache space corresponding to the first logical partition is used for retransmitting the overtime IO command to the storage equipment.
The memory controller of claim 19, wherein the first information further includes a delay time length corresponding to an IO command to be retransmitted that is not successfully buffered in the first buffer space, the delay time length being used by the computing device to retransmit the IO command to be retransmitted to the memory device after a wait time length reaches the delay time length.
The memory controller of any of claims 12-14, wherein the processor is specifically configured to:

If a first IO command corresponding to the first address is not found in the first cache space, data writing to the first logical partition is suspended, first information comprising a result of failure in data writing to the first address and the second address is sent to the computing device, the second address is identical to the first address, and the first information is used for the computing device to issue the first IO command corresponding to the first address.
A storage device comprising a storage medium, a cache, and a storage controller as recited in any of claims 12-22, the storage medium comprising a plurality of logical partitions, the plurality of logical partitions comprising a first logical partition, the cache comprising a plurality of cache spaces, the plurality of cache spaces comprising a first cache space, the first cache space being a cache space in a cache in the storage device for caching IO commands to access the first logical partition;

the storage controller is configured to search for an IO command corresponding to a current start write address of the first logical partition from the first cache space, and write data carried by the found IO command corresponding to the start write address into the first logical partition.
The storage device of claim 23, wherein the data in the first logical partition is written by sequential writing.
The storage device of claim 23 or 24, wherein the storage device is a partitioned namespace solid state disk, ZNS SSD.
A method of data processing, the method comprising:

acquiring a first address of a first logical partition in a storage device, wherein the first address is a current initial write-in address of the first logical partition; the first logical partition is any one of a plurality of logical partitions included in the storage device;

transmitting at least one first input/output IO command to the storage device, wherein an access address corresponding to each first IO command is located in a first address range, and the first address range is a logic address range determined according to the first address and a preset first length in the first logic partition;

and receiving first information sent by the storage device in response to the at least one first IO command, wherein the first information is used for the computing device to issue the IO command corresponding to the second address.
A method of data processing, the method comprising:

Receiving at least one first input/output IO command sent by a computing device, wherein an access address corresponding to each first IO command is located in a first address range, and the first address range is a logic address range determined according to the first address and a preset first length in the first logic partition;

storing the at least one first IO command in the first cache space;

determining a current initial writing address in the first logical partition as a first address, and selecting and executing a corresponding command from the at least one first IO command according to the first address;

and sending first information to the computing equipment, wherein the first information is used for the computing equipment to send the IO command corresponding to the second address.
A data processing system comprising a computing device according to any of claims 1-11 and a storage device according to any of claims 23-25.
A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a computer program which, when run on a computer, causes the computer to perform the method of claim 26 or to perform the method of claim 27.
A computer program product for causing a computer to perform the method of claim 26 or to perform the method of claim 27 when the computer program product is run on a computer.