CN117371379A - Method and device for generating maximum load of time sequence library, storage medium and electronic device - Google Patents
Method and device for generating maximum load of time sequence library, storage medium and electronic device Download PDFInfo
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Abstract
The embodiment of the invention provides a method and a device for generating a maximum load of a time sequence library, a storage medium and an electronic device, wherein the method for generating the maximum load of the time sequence library comprises the following steps: obtaining a clock tree layout corresponding to the driving clock unit, wherein the clock tree layout is used for indicating a layout mode of connecting the driving clock unit with a target fan-out through a target connecting wire, and the driving performance of the driving clock unit is higher than a target performance threshold; testing the load of a target test circuit meeting the clock tree layout to obtain a target load value, wherein the load of the target test circuit is the total value of the load brought by a target connection line and a target fan-out; the target load value is determined as the maximum load of the time sequence library corresponding to the driving clock unit, and the technical scheme solves the problems of low matching degree between the maximum load of the time sequence library and the driving clock unit and the like in the related technology, and achieves the technical effect of improving the matching degree between the maximum load of the time sequence library and the driving clock unit.
Description
Technical Field
The embodiment of the invention relates to the field of chips, in particular to a method and a device for generating a maximum load of a time sequence library, a storage medium and an electronic device.
Background
Along with the increasing size of the chip, the clock structure of the chip is more and more important for the timing convergence of the whole chip, wherein, the Cell Delay corresponding to the driving clock unit is determined to play a crucial role in the timing convergence process of the chip, and at present, the Cell Delay corresponding to the driving clock unit in a specific Output Load and input transition time is usually determined by means of a timing library, so that a spot is visible in the importance of an accurate timing library in the timing convergence process of the chip;
at present, in the process of generating a timing sequence library corresponding to a large driving clock unit, the maximum load which can be normally driven by the large driving clock unit is automatically calculated by using an EDA (Electronic Design Automation) tool and is used as the maximum load value of the timing sequence library usually based on the specification requirement indicated by Max Transition (maximum signal conversion time) corresponding to the large driving clock unit, however, because the large driving clock unit has strong driving capability, the calculated maximum load is often very large and is far larger than the load value actually used by the large driving clock unit, the maximum load is used as the maximum load value of the timing sequence library, and the excessive load value directly leads to the fact that the created timing sequence library usually only generates a huge useless section, so that the numerical precision in the effective section is lower, and even the situation that the timing sequence evaluation of a chip is inaccurate possibly occurs.
Aiming at the problems of low matching degree between the maximum load of the time sequence library and the driving clock unit and the like in the related art, no effective solution is proposed yet.
Disclosure of Invention
The embodiment of the application provides a method and a device for generating a maximum load of a time sequence library, a storage medium and an electronic device, and aims to at least solve the problems of low matching degree between the maximum load of the time sequence library and a driving clock unit and the like in the related technology.
According to an embodiment of the present application, there is provided a method for generating a maximum load of a timing base, including:
obtaining a clock tree layout corresponding to a driving clock unit, wherein the clock tree layout is used for indicating a layout mode of the driving clock unit connected with a target fan-out through a target connecting line, and the driving performance of the driving clock unit is higher than a target performance threshold;
testing the load of a target test circuit meeting the clock tree layout to obtain a target load value, wherein the load of the target test circuit is the total value of the load brought by the target connecting line and the target fan-out;
and determining the target load value as the maximum load of a time sequence library corresponding to the driving clock unit, wherein the time sequence library is used for carrying out time sequence analysis on a chip provided with the driving clock unit.
In an exemplary embodiment, the testing the load of the target test circuit meeting the clock tree layout to obtain the target load value includes:
acquiring a target delay time corresponding to the driving clock unit and an initial equivalent circuit of the target test circuit, wherein the target delay time corresponds to the driving clock unit and the initial equivalent circuit is included in the target test circuit, and the initial equivalent circuit is equivalent to a driving scene of the driving clock unit;
adjusting the delay time of the initial equivalent circuit to the target delay time to obtain a target equivalent circuit;
and determining the load value of the target equivalent circuit as the target load value.
In an exemplary embodiment, said adjusting the delay time of the initial equivalent circuit to the target delay time, to obtain a target equivalent circuit, includes:
adjusting a load value of an adjustable load included in the initial equivalent circuit, wherein the initial equivalent circuit is equivalent to a driving scene of the driving clock unit through the driving clock unit and the adjustable load which have a connection relationship;
detecting delay time of the driving clock unit in the process of adjusting the load value of the adjustable load;
And determining an equivalent circuit of which the delay time reaches the target delay time as the target equivalent circuit, wherein the current load value of the adjustable load in the target equivalent circuit is the load value of the target equivalent circuit.
In an exemplary embodiment, the obtaining the target delay time corresponding to the driving clock unit included in the target test circuit includes:
extracting a rear simulated netlist of the target test circuit, wherein the rear simulated netlist is used for recording circuit information of the target test circuit;
and simulating the post-simulation netlist to obtain the target delay time.
In an exemplary embodiment, before the testing the load of the target test circuit satisfying the clock tree layout to obtain the target load value, the method further includes:
determining the maximum length of the target connecting line according to the clock tree layout, and the maximum number of target fan-out;
and connecting the maximum number of target fan-outs to the driving clock unit through the target connecting lines with the maximum length according to the layout mode to obtain the target test circuit.
In an exemplary embodiment, said connecting said maximum number of said target fan-outs to said driving clock unit by said target connection lines of said maximum length in said layout manner results in said target test circuit comprising:
connecting the maximum number of target fan-outs to the driving clock unit through the maximum length of target connecting lines in the layout mode to serve as a reference test circuit;
and setting a shielding unit outside the reference test circuit to obtain the target test circuit, wherein the shielding unit is used for shielding interference signals.
In an exemplary embodiment, after the determining the target load value as the maximum load of the timing library corresponding to the driving clock unit, the method further includes:
selecting one or more reference load values from a load range corresponding to the target load value to obtain a load value set, wherein the load value set comprises the target load value and the one or more reference load values;
inputting each load value in the load value set and the signal conversion time corresponding to each load value into a time sequence analysis tool to obtain the delay time corresponding to each load value;
And recording each load value, the signal conversion time and the delay time which have a corresponding relation to obtain the time sequence library.
According to another embodiment of the embodiments of the present application, there is also provided a generating device for generating a maximum load of a timing library, including:
the acquisition module is used for acquiring a clock tree layout corresponding to the driving clock unit, wherein the clock tree layout is used for indicating a layout mode that the driving clock unit is connected with a target fan-out through a target connecting wire, and the driving performance of the driving clock unit is higher than a target performance threshold;
the test module is used for testing the load of the target test circuit meeting the clock tree layout to obtain a target load value, wherein the load of the target test circuit is the total value of the load brought by the target connecting line and the target fan-out;
the first determining module is used for determining the target load value as the maximum load of a time sequence library corresponding to the driving clock unit, wherein the time sequence library is used for carrying out time sequence analysis on a chip on which the driving clock unit is arranged.
According to yet another aspect of the embodiments of the present application, there is also provided a computer readable storage medium having a computer program stored therein, wherein the computer program is configured to execute the method for generating a maximum load of a time base described above when running.
According to still another aspect of the embodiments of the present application, there is further provided an electronic device including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the method for generating the maximum load of the timing base through the computer program.
In the embodiment of the application, a clock tree layout corresponding to a driving clock unit is obtained, wherein the clock tree layout is used for indicating a layout mode that the driving clock unit is connected with a target fan-out through a target connecting wire, and the driving performance of the driving clock unit is higher than a target performance threshold; testing the load of a target test circuit meeting the clock tree layout to obtain a target load value, wherein the load of the target test circuit is the total value of the load brought by a target connection line and a target fan-out; and determining a target load value as the maximum load of a time sequence library corresponding to the driving clock unit, wherein the time sequence library is used for carrying out time sequence analysis on a chip on which the driving clock unit is deployed, namely firstly obtaining a clock tree layout corresponding to the driving clock unit, wherein the clock tree layout indicates a layout mode among the driving clock unit, a target connecting line and a target fan-out, taking the load brought by the target connecting line indicated by the clock tree layout and the target fan-out as the maximum load, and more precisely testing the load value driven by the driving clock unit, so that the load of a target test circuit meeting the clock tree layout, namely testing the total value of the load brought by the target connecting line and the target fan-out, and then determining the target load value as the maximum load of the time sequence library corresponding to the driving clock unit, wherein the parameter range recorded by the time sequence library is the effective range of the driving clock unit. By adopting the technical scheme, the problems of low matching degree of the maximum load of the time sequence library and the driving clock unit and the like in the related technology are solved, and the technical effect of improving the matching degree of the maximum load of the time sequence library and the driving clock unit is realized.
Drawings
Fig. 1 is a block diagram of a hardware structure of a mobile terminal of a method for generating a maximum load of a timing base according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method of generating a timing base maximum load according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a target test circuit according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a timing library according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a method of generating a timing base maximum load according to an embodiment of the present application;
fig. 6 is a block diagram of a timing library maximum load generation apparatus according to an embodiment of the present application.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The method embodiments provided in the embodiments of the present application may be performed in a mobile terminal, a computer terminal or similar computing device. Taking the mobile terminal as an example, fig. 1 is a block diagram of a hardware structure of the mobile terminal according to a method for generating a maximum load of a timing base according to an embodiment of the present invention. As shown in fig. 1, a mobile terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the structure shown in fig. 1 is merely illustrative and not limiting of the structure of the mobile terminal described above. For example, the mobile terminal may also include more or fewer components than shown in fig. 1, or have a different configuration than shown in fig. 1.
The memory 104 may be used to store a computer program, for example, a software program of an application software and a module, such as a computer program corresponding to a method for generating a maximum load of a time sequence library in an embodiment of the present invention, and the processor 102 executes the computer program stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the above-mentioned method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission means 106 is arranged to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is used to communicate with the internet wirelessly.
In this embodiment, a method for generating a maximum load of a time sequence library is provided and applied to the above device terminal, and fig. 2 is a flowchart of a method for generating a maximum load of a time sequence library according to an embodiment of the present application, where the flowchart includes the following steps:
step S202, obtaining a clock tree layout corresponding to a driving clock unit, wherein the clock tree layout is used for indicating a layout mode of the driving clock unit connected with a target fan-out through a target connection line, and the driving performance of the driving clock unit is higher than a target performance threshold;
step S204, testing the load of a target test circuit meeting the clock tree layout to obtain a target load value, wherein the load of the target test circuit is the total value of the load brought by the target connection line and the target fan-out;
step S206, determining the target load value as a maximum load of a timing sequence library corresponding to the driving clock unit, where the timing sequence library is used for performing timing sequence analysis on a chip on which the driving clock unit is disposed.
Through the steps, firstly, the clock tree layout corresponding to the driving clock unit is obtained, wherein the clock tree layout indicates a layout mode among the driving clock unit, the target connection line and the target fan-out, the load caused by the target connection line and the target fan-out indicated by the clock tree layout is taken as the maximum load, and the load value driven by the driving clock unit can be tested more accurately. By adopting the technical scheme, the problems of low matching degree of the maximum load of the time sequence library and the driving clock unit and the like in the related technology are solved, and the technical effect of improving the matching degree of the maximum load of the time sequence library and the driving clock unit is realized.
In the technical solution provided in step S202, the driving Performance of the driving clock unit is higher than the target Performance threshold, which may, but is not limited to, refer to that the main body corresponding to the method for generating the maximum load of the timing base in the present application may be a large driving clock unit, because the large driving clock unit has a very strong driving capability, the maximum load automatically calculated according to the method for calculating the maximum load value of the timing base in the background art may be very large, which greatly increases the convergence difficulty of the electromigration failure analysis, if the risk of electromigration failure needs to be completely released, the Area of the large driving clock unit may need to be increased, or the Performance of the large driving clock unit may be actively reduced, so that the PPA (Power consumption, performance, area) loss may be brought, and even the large driving clock unit itself may not complete convergence, and additional P & R resources may need to be consumed; in order to minimize clock delay in an actual clock tree, the output load of each large driving clock unit is often reasonably optimized and limited, for example, the clock line length driven by each large driving clock unit is limited within a certain length, and the number of next stage units (Fan-out) driven is also strictly limited, so that the maximum load in a time sequence library is often only a huge useless interval, but rather, the numerical precision in an effective interval is lower, and the time sequence evaluation is possibly inaccurate. Aiming at the problems in the large driving clock unit, the method for generating the maximum load of the time sequence library can obtain the maximum load in the time sequence library of the more accurate large driving clock unit, so that on one hand, the convergence difficulty of electromigration failure analysis can be reduced, and further, the competitive advantage of the large driving clock unit and an application chip on PPA is improved, on the other hand, the output load in the two-dimensional time sequence library can be ensured to be in an effective interval, the precision of the time sequence library is improved, the accuracy of time sequence analysis of a chip clock tree is ensured, and further, the better chip performance is obtained.
Alternatively, in the present embodiment, the clock tree layout may, but is not limited to, generate a connection scheme based on a given one of the source nodes and the N target nodes, and connect the source nodes and the N target nodes. Balancing the delay on each path branch of the clock by inserting inverters or buffers, i.e. Skew, is small enough while minimizing the delay; the clock tree layout is actually to meet the global SDC (Synopsys design constraints, timing constraint). And meanwhile, the influence of the clock tree comprehensive scheme on power consumption, area and the like is considered. May include, but is not limited to: balanced trees, H-trees, and meshes, etc.
In the solution provided in step S204, the total value of the load of the target test circuit brought by the target connection line and the target fan-out may, but is not limited to, be that the source of the load may include two parts: targeting links and targeting fanouts, because targeting links typically only provide the required length parameter, but because of their own resistance, actually also carry a load.
Optionally, in this embodiment, fig. 3 is a schematic diagram of a target test circuit according to an embodiment of the present invention, and as shown in fig. 3, two scenarios are provided, where a test circuit a is a scenario where the target fan-out is 4 and the wire length is 4L; the test circuit b is a wire with the target fan-out of 2 and the length of the wire of 2L, and the load in the test circuit a is derived from the wires with the length of 4 target fan-outs and 4L; the load in test circuit b originates from 2 target fan-outs and a 2L length of wiring.
In one exemplary embodiment, the load of a target test circuit that satisfies the clock tree layout may be tested, but is not limited to, to a target load value, by: acquiring a target delay time corresponding to the driving clock unit and an initial equivalent circuit of the target test circuit, wherein the target delay time corresponds to the driving clock unit and the initial equivalent circuit is included in the target test circuit, and the initial equivalent circuit is equivalent to a driving scene of the driving clock unit; adjusting the delay time of the initial equivalent circuit to the target delay time to obtain a target equivalent circuit; and determining the load value of the target equivalent circuit as the target load value.
Alternatively, in the present embodiment, the target Delay time may refer to Cell Delay, which refers to the time from input to output of a signal. The transistors in the Cell require a certain time to switch, so a change in Input of the Cell requires a certain time to cause an Output to change.
Alternatively, in the present embodiment, the initial equivalent circuit may be regarded as, but not limited to, a circuit including a driving clock unit in a target test circuit, the delay time of the initial equivalent circuit is adjusted, and in the case where the delay time reaches the target delay time, the initial equivalent circuit may be regarded as a target equivalent circuit, at which time the load value of the load to which the initial equivalent circuit is connected may be determined as the target load value.
In one exemplary embodiment, the delay time of the initial equivalent circuit may be adjusted to the target delay time by, but not limited to,: adjusting a load value of an adjustable load included in the initial equivalent circuit, wherein the initial equivalent circuit is equivalent to a driving scene of the driving clock unit through the driving clock unit and the adjustable load which have a connection relationship; detecting delay time of the driving clock unit in the process of adjusting the load value of the adjustable load; and determining an equivalent circuit of which the delay time reaches the target delay time as the target equivalent circuit, wherein the current load value of the adjustable load in the target equivalent circuit is the load value of the target equivalent circuit.
Optionally, in this embodiment, the manner of adjusting the delay time of the initial equivalent circuit may, but is not limited to, connecting an adjustable load after a driving clock unit included in the initial equivalent circuit, and changing the delay time of the initial equivalent circuit to the target delay time by adjusting the load size to obtain a target equivalent circuit, where the current load value of the adjustable load in the target equivalent circuit is the load value of the target equivalent circuit, for example, the target delay time D1 from the input end to the output end of the driving clock unit in the known target equivalent circuit is 30ps; adding an adjustable load to the output end of a driving clock unit of the initial equivalent circuit to obtain delay time (D2) from the input end to the output end; when the size of the load c2 was 4pf, the size of D2 was 30ps and was equal to D1. At this time, the value of c2, 4pf, is the current load value (4 pf) of the adjustable load, which is the load value of the target equivalent circuit.
In one exemplary embodiment, the target delay time corresponding to the driving clock unit included in the target test circuit may be, but is not limited to, obtained by: extracting a rear simulated netlist of the target test circuit, wherein the rear simulated netlist is used for recording circuit information of the target test circuit; and simulating the post-simulation netlist to obtain the target delay time.
Optionally, in this embodiment, the post-netlist may include, but is not limited to, all information of the target test circuit, for example, device parameters and connection modes included in the target test circuit, and the post-netlist may be understood as a virtual circuit representing the target test circuit, and the post-netlist may be simulated to obtain the target delay time, that is, the post-netlist is used to obtain the target delay time in a manner different from the real test, and the simulation method may not only obtain the required data similarly, but also has convenience.
In an exemplary embodiment, before the load of the target test circuit meeting the clock tree layout is tested to obtain the target load value, the method may further include, but is not limited to: determining the maximum length of the target connecting line according to the clock tree layout, and the maximum number of target fan-out; and connecting the maximum number of target fan-outs to the driving clock unit through the target connecting lines with the maximum length according to the layout mode to obtain the target test circuit.
Optionally, in this embodiment, the objective test circuit may, but is not limited to, connect the maximum number of objective fan-outs to the driving clock unit through the objective connection line with the maximum length according to the layout manner indicated by the clock tree layout, for example, may determine, according to the actual chip clock tree layout, an application scenario of the maximum load of the driving clock unit as follows: the maximum fan-out number of the large driving clock unit to be driven is 4, and the length L of the clock tree connecting line between the large driving unit and the fan-out is 4000um; and then designing a target test circuit according to the application scene of the maximum load, namely connecting 4 fan-out units at the output end of the driving clock unit, wherein the fan-out units are large driving clock units, and the length of a clock tree connecting line between the large driving clock units and the fan-out units is 4000um.
In one exemplary embodiment, the maximum number of the target fanouts may be connected to the driving clock unit through the target wiring of the maximum length in the layout manner, resulting in the target test circuit, but is not limited to, by: connecting the maximum number of target fan-outs to the driving clock unit through the maximum length of target connecting lines in the layout mode to serve as a reference test circuit; and setting a shielding unit outside the reference test circuit to obtain the target test circuit, wherein the shielding unit is used for shielding interference signals.
Optionally, in this embodiment, the shielding unit may be, but is not limited to, a shielding unit designed by shielding, so as to shield the reference test circuit from the external interference signal, so that the test result obtained by the target test circuit is more accurate.
In the solution provided in step S206, fig. 4 is a schematic diagram of a timing library according to an embodiment of the present invention, as shown in fig. 4, where the two-dimensional timing library gives a cell delay of a cell under a specific output load and input transition time, for example, in a case where the output load of the cell is 0.100pF and the input transition time is 1.00ns, the corresponding cell delay is 0.700ns.
Optionally, in this embodiment, the target load value is determined as the maximum load of the timing sequence library corresponding to the driving clock unit, so that the output load in the two-dimensional timing sequence library is ensured to be in an effective interval, the precision of the timing sequence library is improved, and the accuracy of the timing sequence analysis of the chip clock tree is ensured, thereby obtaining better chip performance.
In an exemplary embodiment, after the target load value is determined as the maximum load of the timing base corresponding to the driving clock unit, the method may further include, but is not limited to, selecting one or more reference load values from a load range corresponding to the target load value to obtain a load value set, where the load value set includes the target load value and the one or more reference load values; inputting each load value in the load value set and the signal conversion time corresponding to each load value into a time sequence analysis tool to obtain the delay time corresponding to each load value; and recording each load value, the signal conversion time and the delay time which have a corresponding relation to obtain the time sequence library.
Alternatively, in this embodiment, taking the target load value as 0.200pF as an example, after taking 0.200pF as the maximum load of the timing library, one or more reference load values (0.005, 0.050, 0.100 and 0.150) may be selected in a load range corresponding to 0.200pF, the specific selection may be determined according to the actual requirement, and then, based on the specification requirements indicated by different input transition times, the corresponding delay time is obtained by the timing analysis tool, for example, the output load is 0.100pF, the input transition time is 1.00ns is input to the timing analysis tool, and the corresponding unit delay is 0.700ns.
In order to better understand the process of generating the maximum load of the time sequence library, the following description is provided with reference to an alternative embodiment, but is not limited to the technical solution of the embodiment of the present application.
In this embodiment, a method for generating a maximum load of a timing base is provided, and fig. 5 is a schematic diagram of a method for generating a maximum load of a timing base according to an embodiment of the present application, as shown in fig. 5, mainly including the following steps:
step S501: determining an application scene of the maximum load of a large driving clock unit according to the actual chip clock tree layout, wherein the application scene comprises the maximum connection length (L) of the clock and the maximum fan-out number;
Step S502: designing a test circuit (A) according to the application scene of the maximum load, namely connecting corresponding fan-out number at the output end of the large driving clock unit, wherein the fan-out number is generally 2-4, and the input capacitance of each fan-out unit is not less than that of the large driving clock unit;
step S503: drawing a layout of a test circuit (A), wherein a connection line is formed between a tested large driving clock unit and a fan-out by using the longest clock tree connection line length (L), and a shielding (shielding) design is performed on the connection line;
step S504: extracting a rear netlist N1 of the test circuit (A) and a rear netlist N2 of a single large driving clock unit;
step S505: the post simulation netlist N1 of the simulation test circuit (A) is used for obtaining delay time (D1) from the input end to the output end of the large driving clock unit;
step S506: the method comprises the steps that a load c2 is added to an output end while a post simulated netlist N2 of a single large driving clock unit is simulated, so that delay time (D2) from the input end to the output end is obtained;
step S507: and c2 is regulated until D2 is equal to D1, and the value of c2 at the moment is read, namely the maximum load value required in the time sequence base of the large driving clock unit.
The invention determines the application scene of the maximum load of the large driving clock unit according to the maximum clock tree connection length and the maximum fan-out number in the clock tree layout in the actual chip, further designs a test circuit (A) of the large driving clock unit and the layout thereof, extracts the simulated netlist for simulation, and obtains the delay time (D1) of the large driving clock unit; in addition, the post-simulation netlist of a single large driving clock unit is simulated, and a load (c 2) with adjustable size is added to the output end of the post-simulation netlist, so that delay time (D2) is obtained. When the delay time (D2) is equal to the delay time (D1), the load (c 2) corresponding to the delay time (D2) is considered to be the equivalent load of the output end of the large driving clock unit in the test circuit (a), and the maximum load required in the timing base of the large driving clock unit is obtained. On one hand, the convergence difficulty of electromigration failure analysis can be reduced, and the competitive advantages of a large driving clock unit and an application chip on PPA are further improved, on the other hand, the output load in the two-dimensional time sequence library can be ensured to be in an effective interval, the precision of the time sequence library is improved, the accuracy of time sequence analysis of a chip clock tree is ensured, and therefore better chip performance is obtained.
From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), comprising several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method of the embodiments of the present application.
FIG. 6 is a block diagram of a timing base maximum load generation apparatus according to an embodiment of the present application; as shown in fig. 6, includes:
the obtaining module 602 is configured to obtain a clock tree layout corresponding to a driving clock unit, where the clock tree layout is used to indicate a layout mode that the driving clock unit is connected with a target fan-out through a target connection line, and driving performance of the driving clock unit is higher than a target performance threshold;
The test module 604 is configured to test a load of a target test circuit that meets the clock tree layout to obtain a target load value, where the load of the target test circuit is a total value of loads caused by the target connection line and the target fan-out;
a first determining module 606, configured to determine the target load value as a maximum load of a timing sequence library corresponding to the driving clock unit, where the timing sequence library is used to perform timing sequence analysis on a chip where the driving clock unit is deployed.
Through the above embodiment, firstly, the clock tree layout corresponding to the driving clock unit is obtained, wherein the clock tree layout indicates a layout manner among the driving clock unit, the target connection line and the target fan-out, the load caused by the target connection line and the target fan-out indicated by the clock tree layout is taken as the maximum load, and the load value driven by the driving clock unit can be tested more accurately. By adopting the technical scheme, the problems of low matching degree of the maximum load of the time sequence library and the driving clock unit and the like in the related technology are solved, and the technical effect of improving the matching degree of the maximum load of the time sequence library and the driving clock unit is realized.
In one exemplary embodiment, the test module includes:
the acquisition unit is used for acquiring target delay time corresponding to the driving clock unit and an initial equivalent circuit of the target test circuit, wherein the target delay time corresponds to the driving clock unit and the initial equivalent circuit is equivalent to a driving scene of the driving clock unit;
the adjusting unit is used for adjusting the delay time of the initial equivalent circuit to the target delay time to obtain a target equivalent circuit;
and the determining unit is used for determining the load value of the target equivalent circuit as the target load value.
In an exemplary embodiment, the adjusting unit is configured to:
adjusting a load value of an adjustable load included in the initial equivalent circuit, wherein the initial equivalent circuit is equivalent to a driving scene of the driving clock unit through the driving clock unit and the adjustable load which have a connection relationship;
detecting delay time of the driving clock unit in the process of adjusting the load value of the adjustable load;
and determining an equivalent circuit of which the delay time reaches the target delay time as the target equivalent circuit, wherein the current load value of the adjustable load in the target equivalent circuit is the load value of the target equivalent circuit.
In an exemplary embodiment, the acquiring unit is configured to:
extracting a rear simulated netlist of the target test circuit, wherein the rear simulated netlist is used for recording circuit information of the target test circuit;
and simulating the post-simulation netlist to obtain the target delay time.
In an exemplary embodiment, the apparatus further comprises:
the second determining module is used for determining the maximum length of the target connection line and the maximum number of the target fan-out according to the clock tree layout before the load of the target test circuit meeting the clock tree layout is tested to obtain a target load value;
and the connection module is used for connecting the maximum number of target fan-outs to the driving clock unit through the target connecting lines with the maximum length according to the layout mode to obtain the target test circuit.
In one exemplary embodiment, the connection module includes:
the connection unit is used for connecting the maximum number of target fan-outs to the driving clock unit through the target connecting lines with the maximum length in the layout mode to serve as a reference test circuit;
And the setting unit is used for setting a shielding unit outside the reference test circuit to obtain the target test circuit, wherein the shielding unit is used for shielding interference signals.
In an exemplary embodiment, the apparatus further comprises:
the selecting module is used for selecting one or more reference load values from a load range corresponding to the target load value after the target load value is determined to be the maximum load of the time sequence library corresponding to the driving clock unit, so as to obtain a load value set, wherein the load value set comprises the target load value and the one or more reference load values;
the input module is used for inputting each load value in the load value set and the signal conversion time corresponding to each load value into the time sequence analysis tool to obtain the delay time corresponding to each load value;
and the recording module is used for recording each load value, the signal conversion time and the delay time which have a corresponding relation to obtain the time sequence library. Embodiments of the present application also provide a storage medium including a stored program, wherein the program performs the method of any one of the above when run.
Alternatively, in the present embodiment, the above-described storage medium may be configured to store program code for performing the steps of:
s1, obtaining a clock tree layout corresponding to a driving clock unit, wherein the clock tree layout is used for indicating a layout mode of the driving clock unit connected with a target fan-out through a target connecting line, and the driving performance of the driving clock unit is higher than a target performance threshold;
s2, testing the load of a target test circuit meeting the clock tree layout to obtain a target load value, wherein the load of the target test circuit is the total value of the load brought by the target connection line and the target fan-out;
and S3, determining the target load value as the maximum load of a time sequence library corresponding to the driving clock unit, wherein the time sequence library is used for carrying out time sequence analysis on a chip on which the driving clock unit is arranged.
Embodiments of the present application also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
Optionally, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Alternatively, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
s1, obtaining a clock tree layout corresponding to a driving clock unit, wherein the clock tree layout is used for indicating a layout mode of the driving clock unit connected with a target fan-out through a target connecting line, and the driving performance of the driving clock unit is higher than a target performance threshold;
s2, testing the load of a target test circuit meeting the clock tree layout to obtain a target load value, wherein the load of the target test circuit is the total value of the load brought by the target connection line and the target fan-out;
and S3, determining the target load value as the maximum load of a time sequence library corresponding to the driving clock unit, wherein the time sequence library is used for carrying out time sequence analysis on a chip on which the driving clock unit is arranged.
Alternatively, in the present embodiment, the storage medium may include, but is not limited to: a U-disk, a Read-Only Memory (ROM), a random access Memory (RandomAccess Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Alternatively, specific examples in this embodiment may refer to examples described in the foregoing embodiments and optional implementations, and this embodiment is not described herein.
It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be centralized on a single computing device, or distributed across a network of computing devices, or they may alternatively be implemented in program code executable by computing devices, such that they may be stored in a memory device for execution by the computing devices and, in some cases, the steps shown or described may be performed in a different order than what is shown or described, or they may be implemented as individual integrated circuit modules, or as individual integrated circuit modules. Thus, the present application is not limited to any specific combination of hardware and software.
The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application and are intended to be comprehended within the scope of the present application.
Claims (10)
1. A method for generating a maximum load of a timing library, comprising:
obtaining a clock tree layout corresponding to a driving clock unit, wherein the clock tree layout is used for indicating a layout mode of the driving clock unit connected with a target fan-out through a target connecting line, and the driving performance of the driving clock unit is higher than a target performance threshold;
testing the load of a target test circuit meeting the clock tree layout to obtain a target load value, wherein the load of the target test circuit is the total value of the load brought by the target connecting line and the target fan-out;
and determining the target load value as the maximum load of a time sequence library corresponding to the driving clock unit, wherein the time sequence library is used for carrying out time sequence analysis on a chip provided with the driving clock unit.
2. The method of claim 1, wherein testing the load of the target test circuit that satisfies the clock tree layout to obtain a target load value comprises:
acquiring a target delay time corresponding to the driving clock unit and an initial equivalent circuit of the target test circuit, wherein the target delay time corresponds to the driving clock unit and the initial equivalent circuit is included in the target test circuit, and the initial equivalent circuit is equivalent to a driving scene of the driving clock unit;
Adjusting the delay time of the initial equivalent circuit to the target delay time to obtain a target equivalent circuit;
and determining the load value of the target equivalent circuit as the target load value.
3. The method of claim 2, wherein said adjusting the delay time of the initial equivalent circuit to the target delay time results in a target equivalent circuit, comprising:
adjusting a load value of an adjustable load included in the initial equivalent circuit, wherein the initial equivalent circuit is equivalent to a driving scene of the driving clock unit through the driving clock unit and the adjustable load which have a connection relationship;
detecting delay time of the driving clock unit in the process of adjusting the load value of the adjustable load;
and determining an equivalent circuit of which the delay time reaches the target delay time as the target equivalent circuit, wherein the current load value of the adjustable load in the target equivalent circuit is the load value of the target equivalent circuit.
4. The method according to claim 2, wherein the obtaining the target delay time corresponding to the driving clock unit included in the target test circuit includes:
Extracting a rear simulated netlist of the target test circuit, wherein the rear simulated netlist is used for recording circuit information of the target test circuit;
and simulating the post-simulation netlist to obtain the target delay time.
5. The method of claim 1, wherein prior to testing the load of the target test circuit that satisfies the clock tree layout to obtain a target load value, the method further comprises:
determining the maximum length of the target connecting line according to the clock tree layout, and the maximum number of target fan-out;
and connecting the maximum number of target fan-outs to the driving clock unit through the target connecting lines with the maximum length according to the layout mode to obtain the target test circuit.
6. The method of claim 5, wherein said connecting said maximum number of said target fanouts to said drive clock unit by said target connection lines of said maximum length in said layout manner results in said target test circuit comprising:
connecting the maximum number of target fan-outs to the driving clock unit through the maximum length of target connecting lines in the layout mode to serve as a reference test circuit;
And setting a shielding unit outside the reference test circuit to obtain the target test circuit, wherein the shielding unit is used for shielding interference signals.
7. The method according to any one of claims 1 to 6, wherein after the determining the target load value as the maximum load of the timing library to which the driving clock unit corresponds, the method further comprises:
selecting one or more reference load values from a load range corresponding to the target load value to obtain a load value set, wherein the load value set comprises the target load value and the one or more reference load values;
inputting each load value in the load value set and the signal conversion time corresponding to each load value into a time sequence analysis tool to obtain the delay time corresponding to each load value;
and recording each load value, the signal conversion time and the delay time which have a corresponding relation to obtain the time sequence library.
8. A timing library maximum load generation apparatus, comprising:
the acquisition module is used for acquiring a clock tree layout corresponding to the driving clock unit, wherein the clock tree layout is used for indicating a layout mode that the driving clock unit is connected with a target fan-out through a target connecting wire, and the driving performance of the driving clock unit is higher than a target performance threshold;
The test module is used for testing the load of the target test circuit meeting the clock tree layout to obtain a target load value, wherein the load of the target test circuit is the total value of the load brought by the target connecting line and the target fan-out;
the first determining module is used for determining the target load value as the maximum load of a time sequence library corresponding to the driving clock unit, wherein the time sequence library is used for carrying out time sequence analysis on a chip on which the driving clock unit is arranged.
9. A computer-readable storage medium, characterized in that the computer-readable storage medium comprises a stored program, wherein the program when run performs the method of any one of claims 1 to 7.
10. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to execute the method according to any of claims 1 to 7 by means of the computer program.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210765716.5A CN117371379A (en) | 2022-06-30 | 2022-06-30 | Method and device for generating maximum load of time sequence library, storage medium and electronic device |
| PCT/CN2023/101512 WO2024001891A1 (en) | 2022-06-30 | 2023-06-20 | Method and apparatus for generating maximum load of timing library, and storage medium and electronic apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210765716.5A CN117371379A (en) | 2022-06-30 | 2022-06-30 | Method and device for generating maximum load of time sequence library, storage medium and electronic device |
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| CN117371379A true CN117371379A (en) | 2024-01-09 |
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| CN (1) | CN117371379A (en) |
| WO (1) | WO2024001891A1 (en) |
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| US5197015A (en) * | 1990-12-20 | 1993-03-23 | Vlsi Technology, Inc. | System and method for setting capacitive constraints on synthesized logic circuits |
| JP2000048053A (en) * | 1998-07-27 | 2000-02-18 | Toshiba Corp | Method for analyzing timing |
| US6769104B2 (en) * | 2002-05-08 | 2004-07-27 | Agilent Technologies, Inc. | Method and apparatus for minimizing clock skew in a balanced tree when interfacing to an unbalanced load |
| CN102169515B (en) * | 2010-02-26 | 2014-04-16 | 国际商业机器公司 | Estimation method and system of clock tree delay time in specified integrated circuit |
| CN110738019B (en) * | 2019-09-26 | 2022-05-24 | 北京华大九天科技股份有限公司 | Method and device for repairing time sequence violation by utilizing automatic clustering of load units |
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