CN117335807A - Analog-to-digital conversion circuit, control method, chip and electronic equipment - Google Patents
Analog-to-digital conversion circuit, control method, chip and electronic equipment Download PDFInfo
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Abstract
The application provides an analog-to-digital conversion circuit, a control method, a chip and electronic equipment, and belongs to the technical field of electronics. The analog-to-digital conversion circuit comprises a first analog-to-digital conversion module, a second sigma-delta analog-to-digital conversion module and a control module; the first analog-to-digital conversion module is configured to periodically convert an input signal according to a first conversion period and output a first conversion result; the second sigma-delta analog-to-digital conversion module is configured to convert an input signal in a first number of second conversion periods and output a second conversion result, wherein the first number is an integer greater than 1; the control module is configured to determine a target conversion result of the input signal according to the second conversion result and at least two first conversion results. By adopting the method and the device, the conversion precision of the analog-to-digital conversion circuit can be improved.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to an analog-to-digital conversion circuit, a control method, a chip, and an electronic device.
Background
Sigma-delta Analog-to-Digital Converter (sigma-delta ADC) is often used as the primary choice for low-speed, high-precision measurement, and is widely used for measuring low-frequency signals, even direct-current signals.
The sigma-delta analog-to-digital conversion circuit has the same input for multiple measurements of the dc signal, and when the circuit noise is much smaller than the quantization error, the quantization error for each conversion period does not substantially change for the same input. For some applications where the input signal is a dc signal, higher accuracy may be required, such as when the system is calibrated, and thus, an analog-to-digital conversion circuit is needed to improve the accuracy of converting the dc signal.
Disclosure of Invention
In order to solve the problems in the prior art, the embodiment of the application provides an analog-to-digital conversion circuit, a control method, a chip and electronic equipment, which can improve conversion accuracy. The technical proposal is as follows:
according to an aspect of the present application, there is provided an analog-to-digital conversion circuit comprising a first analog-to-digital conversion module, a second sigma-delta analog-to-digital conversion module, and a control module;
the first analog-to-digital conversion module is configured to periodically convert an input signal according to a first conversion period and output a first conversion result;
The second sigma-delta analog-to-digital conversion module is configured to convert an input signal in a first number of second conversion periods and output a second conversion result, wherein the first number is an integer greater than 1;
the control module is configured to determine a target conversion result of the input signal according to the second conversion result and at least two first conversion results.
Optionally, the control module is configured to:
obtaining a reference conversion result, the reference conversion result being determined based on the first conversion result of at least one historical first conversion period that is continuous with a current first conversion period;
and determining that the target conversion result is the first conversion result or the second conversion result of the current first conversion period according to the difference value between the first conversion result of the current first conversion period and the reference conversion result.
Optionally, the control module is configured to:
determining that the target conversion result is the first conversion result of the current first conversion period when the difference between the first conversion result of the current first conversion period and the reference conversion result is greater than a first difference threshold;
And determining the target conversion result as the second conversion result when the difference value between the first conversion result and the reference conversion result of the current first conversion period is not greater than a first difference value threshold.
Optionally, the control module is further configured to:
updating the reference conversion result to the first conversion result of the current first conversion period when the difference value between the first conversion result of the current first conversion period and the reference conversion result is larger than a first difference value threshold value.
Optionally, the first analog-to-digital conversion module is configured to reset when the conversion of each first conversion period is completed.
Optionally, the second sigma-delta analog-to-digital conversion module is configured to:
and during the conversion period of the input signal in the first number of second conversion periods, if the difference value between the first conversion result and the reference conversion result of the current first conversion period is not larger than a second difference value threshold value, not resetting.
Optionally, the control module is configured to:
and when the difference value between the first conversion result and the reference conversion result of the current first conversion period is larger than a second difference value threshold value, controlling the second sigma-delta analog-to-digital conversion module to reset.
Optionally, when the difference between the first conversion result and the reference conversion result in the current first conversion period is not greater than a second difference threshold, the state of the input signal is used as a target state;
the second sigma-delta analog-to-digital conversion module is further configured to:
resetting is performed upon completion of a transition of the input signal during a second number of consecutive transition periods during which the input signal is continuously in the target state, wherein the second number is an integer greater than or equal to the first number.
Optionally, the control module is configured to:
and counting a second conversion period of the second sigma-delta analog-to-digital conversion module after conversion is completed during the period that the input signal is continuously in the target state, and controlling the second sigma-delta analog-to-digital conversion module to reset when the count is greater than or equal to the second number.
Optionally, the control module is further configured to:
and controlling the second sigma-delta analog-to-digital conversion module to enable when the difference value between the first conversion result and the reference conversion result of the current first conversion period is not greater than a third difference value threshold.
Optionally, the control module is further configured to:
And when the difference value between the first conversion result and the reference conversion result of the current first conversion period is larger than a third difference value threshold value, controlling the second sigma-delta analog-to-digital conversion module to be closed.
Optionally, the first analog-to-digital conversion module is any one circuit type or a combination of any multiple circuit types of sigma-delta ADC, successive approximation ADC, flash ADC and pipeline ADC.
According to another aspect of the present application, there is provided a control method of an analog-to-digital conversion circuit, the analog-to-digital conversion circuit including a first analog-to-digital conversion module, a second sigma-delta analog-to-digital conversion module, and a control module, the method comprising:
the first analog-to-digital conversion module is controlled to periodically convert an input signal according to a first conversion period and output a first conversion result;
controlling the second sigma-delta analog-to-digital conversion module to convert input signals in a first number of second conversion periods and output a second conversion result, wherein the first number is an integer greater than 1;
and determining a target conversion result of the input signal according to the second conversion result and at least two first conversion results through the control module.
According to another aspect of the present application, a chip is provided, including the above-mentioned analog-to-digital conversion circuit.
According to another aspect of the present application, an electronic device is provided, including the above-mentioned analog-to-digital conversion circuit.
The analog-to-digital conversion circuit comprises a first analog-to-digital conversion module, a second sigma-delta analog-to-digital conversion module and a control module. The first analog-to-digital conversion module can output a first conversion result obtained by converting an input signal of each first conversion period, the second sigma-delta analog-to-digital conversion module can output a second conversion result obtained by converting input signals of a plurality of second conversion periods, and the control module can determine a target conversion result of the input signal according to the two conversion results. If the input signal is a direct current signal or a signal with a gentle change in signal amplitude, the quantization error of the second conversion result is smaller, so that the quantization error of the target conversion result of the input signal is smaller, and the conversion accuracy of the analog-to-digital conversion circuit can be improved.
Drawings
Further details, features and advantages of the present application are disclosed in the following description of exemplary embodiments, with reference to the following drawings, wherein:
Fig. 1 shows a schematic diagram of an analog-to-digital conversion circuit provided according to an exemplary embodiment of the present application;
FIG. 2 shows a schematic diagram of an analog-to-digital conversion circuit provided in accordance with an exemplary embodiment of the present application;
FIG. 3 illustrates a schematic diagram of an analog-to-digital conversion circuit workflow provided in accordance with an exemplary embodiment of the present application;
fig. 4 shows a flowchart of a control method of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is to be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and examples of the present application are for illustrative purposes only and are not intended to limit the scope of the present application.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below. It should be noted that the terms "first," "second," and the like herein are merely used for distinguishing between different devices, modules, or units and not for limiting the order or interdependence of the functions performed by such devices, modules, or units.
It should be noted that references to "one" or "a plurality" in this application are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to be interpreted as "one or more" unless the context clearly indicates otherwise.
The names of messages or information interacted between the various devices in the embodiments of the present application are for illustrative purposes only and are not intended to limit the scope of such messages or information.
The embodiment of the application provides an analog-to-digital conversion circuit, which can be integrated in a chip or arranged in electronic equipment.
Referring to the analog-to-digital conversion circuit schematic shown in fig. 1, the analog-to-digital conversion circuit may include a first analog-to-digital conversion module, a second sigma-delta analog-to-digital conversion module, and a control module. The first analog-to-digital conversion module and the second sigma-delta analog-to-digital conversion module are connected in parallel, the input ends can be used for receiving input signals, and the output ends can be connected with the control module.
The first analog-to-digital conversion module may be configured to periodically convert the input signal according to a first conversion period and output a first conversion result.
The second sigma-delta analog-to-digital conversion module may be configured to convert the input signal for a first number of second conversion periods and output a second conversion result, wherein the first number may be an integer greater than 1. The second switching period may be the same as or different from the first switching period.
The control module may be configured to determine a target conversion result of the input signal based on the second conversion result and the at least two first conversion results. Specifically, it may be determined whether the input signal is a direct current signal whose amplitude is unchanged (or whose variation is very gentle) according to at least two first conversion results, and then the target conversion result is confirmed in the last first conversion result and the second conversion result. Wherein, when the input signal is not a direct current signal, the at least two first conversion results may include a current first conversion period and a first conversion result of a previous first conversion period. When the input signal is a direct current signal, the at least two first conversion results may include a current first conversion period and first conversion results within any one or more of the previous first conversion periods.
The second sigma-delta analog-to-digital conversion module may be implemented based on the principle of sigma-delta averaging, and may be a sigma-delta ADC or a derivative circuit thereof, and the specific circuit type adopted by the second sigma-delta analog-to-digital conversion module is not limited in this embodiment.
Alternatively, the first analog-to-digital conversion module may be any one circuit type or a combination of any multiple circuit types of sigma-delta ADC, successive approximation ADC, flash ADC and pipelined ADC.
As an embodiment, the circuit configuration of the first analog-to-digital conversion module and the second sigma-delta analog-to-digital conversion module may be different, i.e. the first analog-to-digital conversion module may be a non-sigma-delta structured analog-to-digital conversion module.
As another implementation mode, the first analog-to-digital conversion module and the second sigma-delta analog-to-digital conversion module have the same circuit structure, and on the basis, the uniformity of the conversion result can be ensured, so that the subsequent circuit can process based on the target conversion result output by the analog-to-digital conversion circuit.
In one possible implementation, the input signal may be a voltage signal and the analog-to-digital conversion circuit may convert the voltage signal of the input circuit. For example, in the battery power management system, after the current to be detected is converted into a corresponding voltage signal, the voltage signal is input into the analog-to-digital conversion circuit, and the conversion result is output after the conversion is performed by the analog-to-digital conversion circuit, so that the average current in a period of time can be determined based on the conversion result. The specific application scenario of the analog-to-digital conversion circuit in this embodiment is not limited.
In the analog-to-digital conversion circuit provided by the application, the input signal can be connected into the first analog-to-digital conversion module and the second sigma-delta analog-to-digital conversion module, and meanwhile, the input signal is converted through the first analog-to-digital conversion module and the second sigma-delta analog-to-digital conversion module.
Taking a sigma-delta ADC as an example, in the first analog-to-digital conversion module, the modulation code of the current clock cycle may be determined on the basis of the modulation code determined in the previous clock cycle and the current input signal in each clock cycle. The modulation code referenced in the first clock period after the first analog-to-digital conversion module is reset may be an initial value, for example, may be 0. After n clock cycles, that is, after n samples are completed, n modulation codes can be converted, and after conversion, an average value of n samples is used as a corresponding first conversion result. Where n is an integer greater than 0, may be referred to as the oversampling rate (Oversampling Ratio, OSR).
The above n clock cycles are referred to as a first transition cycle in this embodiment. That is, the first analog-to-digital conversion module may be configured to perform a general conversion process on the input signal, and output a corresponding first conversion result when the conversion of each first conversion period is completed. Alternatively, the first analog-to-digital conversion module may be configured to reset upon completion of the conversion of each first conversion period.
Similarly, the second sigma-delta analog-to-digital conversion module may also be used for the conversion process performed on the input signal. The conversion period of the second Σ - Δ analog-to-digital conversion module is referred to as a second conversion period, which may be the same as or different from the first conversion period described above.
The second sigma-delta analog-to-digital conversion module may also output a corresponding second conversion result when the conversion of the first number of second conversion periods is completed. The difference from the first analog-to-digital conversion module is that the second sigma-delta analog-to-digital conversion module may not be reset after completion of one second conversion cycle. Further, in the next second conversion period, the modulation code referred to by the first clock period may be the last modulation code of the last second conversion period. After the first number of second conversion periods, the second conversion result output by the second sigma-delta analog-to-digital conversion module may be a conversion result obtained by converting the input signal in the first number of second conversion periods. On this basis, if the input signal is a direct current signal or a signal whose signal amplitude changes smoothly, the magnitude of the signal amplitude is hardly changed, and the larger the number of second conversion cycles is, the larger the number of sampling times for averaging is, and the smaller the quantization error is. In the present embodiment, the plurality of second conversion periods may correspond to one conversion period having a longer time length than the first conversion period and occupying a larger number of clock cycles than the first conversion period.
Finally, in the control module, whether the input signal is a direct current signal or not or whether the variation of the signal amplitude of the input signal is gentle or not can be judged according to the first conversion results of at least two continuous first conversion periods. If yes, a second conversion result output by the second sigma-delta analog-to-digital conversion module can be selected as a target conversion result of the input signal; if not, the first conversion result output by the first analog-to-digital conversion module can be selected as a target conversion result of the input signal. On the basis, for the direct current signal or the input signal with gentle signal amplitude variation, the analog-to-digital conversion circuit can output a second conversion result with smaller quantization error, so that the conversion accuracy is improved.
In some embodiments, the target conversion result may be determined by reference to the conversion result, and the control module may be configured to, accordingly:
obtaining a reference conversion result;
and determining the target conversion result as the first conversion result or the second conversion result according to the difference value between the first conversion result and the reference conversion result of the current first conversion period.
Wherein the reference conversion result may be determined based on the first conversion result of at least one historical first conversion period consecutive to the current first conversion period. As an example, the reference conversion result corresponding to the 3 rd first conversion period may be determined based on the first conversion result of the previous first conversion period (i.e., the 2 nd first conversion period), or may be determined based on the first conversion results of the previous two first conversion periods (i.e., the 1 st, 2 nd first conversion periods).
In one possible embodiment, the first conversion result of the previous first conversion period may be used as the reference conversion result of the current first conversion period, and the difference between the first conversion result of the current first conversion period and the reference conversion result may be calculated. Based on the difference value, it is possible to determine whether the input signal is a direct current signal or whether the variation in signal amplitude of the input signal is gentle, thereby selecting the first conversion result or the second conversion result as the target conversion result.
Specifically, the conversion result may be determined using a first difference threshold, and accordingly, the control module may be configured to:
when the difference value between the first conversion result of the current first conversion period and the reference conversion result is larger than a first difference value threshold value, determining that the target conversion result is the first conversion result;
and when the difference value between the first conversion result of the current first conversion period and the reference conversion result is not greater than the first difference value threshold value, determining that the target conversion result is the second conversion result.
That is, if the absolute value of the difference between the two is larger than the first difference threshold value set in advance, it is considered that the input signal at this time is not a direct current signal or a signal whose change in signal amplitude is gentle, but a signal which changes, for example, may be a fluctuation signal or a periodic signal, and at this time, the real-time performance requirement for the conversion is high, the first conversion result is outputted as the target conversion result. If the absolute value of the difference between the two is smaller than or equal to a preset first difference threshold, the input signal is considered to be a direct current signal or a signal with gentle change of the signal amplitude, the second conversion result is output as a target conversion result, and the conversion precision is improved by the second sigma-delta analog-digital conversion module.
Optionally, the control module may be further configured to update the reference conversion result to the first conversion result of the current first conversion period when a difference between the first conversion result of the current first conversion period and the reference conversion result is greater than a first difference threshold. That is, the control module determines whether the input signal is a direct current signal or a signal with a gentle change in signal amplitude according to whether the difference between the first conversion results of every two adjacent first conversion periods is greater than a first difference threshold.
In one possible embodiment, when the control module determines that the difference between the first conversion result of the current first conversion period and the reference conversion result is greater than the first difference threshold, the reference conversion result may be updated to the current first conversion result so as to determine that the input signal is a direct current signal or a signal with a gentle change in signal amplitude based on the first conversion result in the next first conversion period. When the control module judges that the difference value between the first conversion result and the reference conversion result is not greater than the first difference value threshold value, the reference conversion result can not be updated, and system resources are saved.
The resetting procedure of the second sigma-delta analog-to-digital conversion module is described below.
Optionally, the second sigma-delta analog-to-digital conversion module may be configured to not reset during converting the input signal for the first number of second conversion periods if the difference between the first conversion result of the current first conversion period and the reference conversion result is not greater than a first difference threshold. That is, the reset condition of the second sigma-delta analog-to-digital conversion module is adapted to the input signal, and if the input signal is a direct current signal or a signal with a gentle change in signal amplitude, the second sigma-delta analog-to-digital conversion module may not reset, so that the input signal is converted once in the plurality of second conversion periods, and a conversion result corresponding to an average value of the input signal in the plurality of second conversion periods is obtained.
Alternatively, the second sigma-delta analog-to-digital conversion module reset may be controlled by a control module, and accordingly, the control module may be configured to: and when the difference value between the first conversion result and the reference conversion result of the current first conversion period is larger than a second difference value threshold value, controlling the second sigma-delta analog-to-digital conversion module to reset.
The second difference threshold may be preset, and may be the same as or different from the first difference threshold, which is not limited in this embodiment. In this embodiment, the second difference threshold is used to determine whether the second sigma-delta analog-to-digital conversion module is reset.
That is, if the absolute value of the difference between the two is greater than the preset second difference threshold, it may be considered that the input signal at this time is not a direct current signal or a signal with a gentle change in signal amplitude, for example, may be a ripple signal, and the control module may send a reset signal to the second sigma-delta analog-to-digital conversion module to control the second sigma-delta analog-to-digital conversion module to reset.
On the basis, when the input signal is a direct current signal or a signal with gentle change of the signal amplitude, the second sigma-delta analog-to-digital conversion module can be reset when the conversion of one second conversion period is completed, and when the signal amplitude of the input signal is changed greatly, the second sigma-delta analog-to-digital conversion module can be reset.
Optionally, for convenience of description, when the difference between the first conversion result of the current first conversion period and the reference conversion result is not greater than the first difference threshold, the state of the input signal is taken as a target state, and the target state indicates that the input signal at this time is a direct current signal or a signal with a gentle change of the signal amplitude; correspondingly, when the difference between the first conversion result of the current first conversion period and the reference conversion result is larger than a first difference threshold, the state of the input signal is taken as a non-target state, and the non-target state indicates that the input signal is not a direct current signal and a signal with gentle change of the signal amplitude.
On the basis, the second sigma-delta analog-to-digital conversion module may be further configured to reset when the conversion of the input signal is completed within a second consecutive number of second conversion periods, which is an integer greater than or equal to the first number, during a period in which the input signal is continuously in the target state.
Wherein the input signal being continuously in the target state may mean that the difference between the first conversion result and the reference conversion result is not greater than a first difference threshold in consecutive at least two first conversion periods.
In the time period corresponding to the continuous at least two first conversion periods, if the second sigma-delta analog-to-digital conversion module does not reset for a long time, the performance of the circuit may be affected, so the maximum number of periods (i.e. the second number) that the second sigma-delta analog-to-digital conversion module can continuously convert may be preset, or the upper limit of the number of bits of the code value that the filter in the second sigma-delta analog-to-digital conversion module can process may be preset to the second number. When the continuous conversion reaches the number, the second sigma-delta analog-to-digital conversion module may be reset, thereby avoiding excessive conversion periods of the continuous conversion of the second sigma-delta analog-to-digital conversion module. As an example, the second number may be set according to an upper limit of the number of bits of the code value that can be processed by the filter in the second sigma-delta analog-to-digital conversion module. For example, if the second sigma-delta analog-to-digital conversion module performs n ' sampling and generates n ' modulation codes in each second conversion period, the digital filter in the second sigma-delta analog-to-digital conversion module can process m-bit modulation codes at most, and the second number may be less than or equal to m/n ', so that after the second number of second conversion periods, the number of bits of the modulation codes continuously generated does not exceed the processing range of the filter, and normal operation of the filter can be ensured.
Alternatively, the counting may be performed by the control module, and correspondingly, the control module may be configured to count a second conversion period in which the conversion of the second sigma-delta analog-to-digital conversion module is completed during the period in which the input signal is continuously in the target state, and when the count is greater than or equal to the second number, control the second sigma-delta analog-to-digital conversion module to reset.
In one possible implementation, the control module may count the second conversion period completed by the second sigma-delta analog-to-digital conversion module during a period when the input signal is continuously in the target state, and may increment the count by 1 each time the second sigma-delta analog-to-digital conversion module completes the conversion of one second conversion period. When the count is greater than or equal to the second number, the control module may send a reset signal to the second sigma-delta analog-to-digital conversion module, control the second sigma-delta analog-to-digital conversion module to reset, and may zero the count. Alternatively, the count may be set to 0 when the input signal jumps from the target state to the non-target state, i.e. the difference between the first transition result of the current first transition period and the reference transition result is greater than a first difference threshold. On this basis, excessive conversion cycles of the second sigma-delta analog-to-digital conversion module can be avoided.
Alternatively, the control module may be further configured to count the modulation codes determined by the second sigma-delta analog-to-digital conversion module during a period when the input signal is continuously in the target state, and when the count is greater than or equal to the second number, control the second sigma-delta analog-to-digital conversion module to reset.
In one possible implementation, the control module may count the modulation codes determined by the second sigma-delta analog-to-digital conversion module during a period in which the input signal is continuously in the target state, and may increment the count by 1 each time the modulation codes are determined by the second sigma-delta analog-to-digital conversion module. When the count is greater than or equal to the second number, that is, the upper processing limit of the filter in the second sigma-delta analog-to-digital conversion module is reached, the control module may send a reset signal to the second sigma-delta analog-to-digital conversion module, control the second sigma-delta analog-to-digital conversion module to reset, and may clear the count. Alternatively, the count may be set to 0 when the input signal jumps from the target state to the non-target state, i.e. the difference between the first transition result of the current first transition period and the reference transition result is greater than a first difference threshold. On the basis, too many conversion periods of the second sigma-delta analog-to-digital conversion module can be avoided.
Alternatively, whether the second sigma-delta analog-to-digital conversion module is enabled may be controlled by the control module, and accordingly, the control module may be further configured to control the second sigma-delta analog-to-digital conversion module to be enabled when the difference between the first conversion result of the current first conversion period and the reference conversion result is not greater than a third difference threshold. That is, if the input signal at this time is a direct current signal or a signal whose change in signal amplitude is gentle, the second sigma-delta analog-to-digital conversion module can be enabled, and the conversion accuracy can be improved by the second sigma-delta analog-to-digital conversion module.
Still further optionally, the control module may be further configured to control the second sigma-delta analog-to-digital conversion module to be turned off when a difference between the first conversion result of the current first conversion cycle and the reference conversion result is greater than a third difference threshold. That is, if the input signal at this time is not a direct current signal or a signal whose change in signal amplitude is gentle, the second sigma-delta analog-to-digital conversion module may be turned off, thereby reducing power consumption.
The third difference threshold may be the same as or different from the first difference threshold or the second difference threshold.
The embodiment of the application can at least obtain the following beneficial effects:
The analog-to-digital conversion circuit comprises a first analog-to-digital conversion module, a second sigma-delta analog-to-digital conversion module and a control module. The first analog-to-digital conversion module can output a first conversion result obtained by converting an input signal of each first conversion period, the second sigma-delta analog-to-digital conversion module can output a second conversion result obtained by converting input signals of a plurality of second conversion periods, and the control module can determine a target conversion result of the input signal according to the two conversion results. If the input signal is a direct current signal or a signal with a gentle change in signal amplitude, the quantization error of the second conversion result is smaller, so that the quantization error of the target conversion result of the input signal is smaller, and the conversion accuracy of the analog-to-digital conversion circuit can be improved.
The embodiment of the application provides a specific analog-to-digital conversion circuit, and introduces the principle of improving the conversion precision by referring to the analog-to-digital conversion circuit.
Taking the first analog-to-digital conversion module as a sigma-delta ADC as an example, referring to the schematic analog-to-digital conversion circuit shown in fig. 2, the circuit may be composed of two sigma-delta ADCs and one control module (corresponding to the control module described above). One sigma-delta ADC in fig. 2 is referred to as isd_adc1 (corresponding to the first analog-to-digital conversion module) and the other sigma-delta ADC is referred to as isd_adc2 (corresponding to the second sigma-delta analog-to-digital conversion module).
The circuit structures of isd_adc1 and isd_adc2 may be the same, and, taking a first-order differential delta sigma-delta ADC as an example, the first amplifying unit 201, the second amplifying unit 202, the third amplifying unit 203, the summing unit 204, the integrating unit 205, the Quantizer 206 (Quantizer), and the filter 207 may be included, respectively. An input terminal of the first amplifying unit 201 may be configured to receive the input voltage Vin, and an output terminal thereof is connected to a first input terminal of the summing unit 204, and the amplification factor may be a (a may take any value). A first input of the summing unit 204 is connected to an output of the first amplifying unit 201; the second input end is connected with the output end of the third amplifying unit 203; the output is connected to the input of the second amplification unit 202. The input end of the second amplifying unit 202 may be connected to the output end of the summing unit 204, the output end is connected to the input end of the integrating unit 205, and the amplification factor may be b (b may take any value). The input of the integrating unit 205 is connected to the output of the second amplifying unit 202, and the output is connected to the input of the quantizer 206. The quantizer 206 has an input connected to the output of the integrating unit 205, and an output connected to the input of the third amplifying unit 203 and the input of the filter 207, respectively. The input end of the third amplifying unit 203 may be connected to the output end of the quantizer 206, the output end is connected to the input end of the control module, and the amplification factor may be c (c may take any value). An input of the filter 207 may be connected to an output of the quantizer 206, and an output may be connected to an input of the control module, wherein an output of the isd_adc1 outputs Out1 (corresponding to the first conversion result) and an output of the isd_adc2 outputs Out2 (corresponding to the second conversion result).
The input end of the control module is connected with the output ends of the ISD_ADC1 and the ISD_ADC2, and the output end is used for outputting a final conversion result Out (corresponding to the target conversion result) of the sigma-delta analog-digital conversion circuit. The control module may output Reset signals Reset1 and Reset2, reset1 for controlling isd_adc1 Reset and Reset2 for controlling isd_adc2 Reset.
The implementation principle of the circuit is as follows:
referring to the schematic workflow diagram of the analog-to-digital conversion circuit shown in fig. 3, the circuit is powered on and initialized, temp (corresponding to the above reference conversion result) is initialized to 0, num (corresponding to the above count) is initialized to 0, and Reset signals Reset1 and Reset2 are respectively sent to isd_adc1 and isd_adc2, so as to control isd_adc1 and isd_adc2 to Reset.
The ISD_ADC1 and ISD_ADC2 sample the input signal Vin n times at the same time, convert Vin into n PDM (Pulse Duration Modulation, pulse width modulation) codes D [0], D [1], … …, D [ n-1], set the PDM code of ISD_ADC1 as D1, and set the PDM code of ISD_ADC2 as D2. The filters of ISD_ADC1 can convert D1[0], D1[1], … …, D1[ n-1] to corresponding first conversion results Out1, and the filters of ISD_ADC2 can convert D2[0], D2[1], … …, D2[ n-1] to corresponding second conversion results Out2.
Assuming that the conversion periods of isd_adc1 and isd_adc2 are the same and each include n clock periods, and isd_adc2 is not reset in Num conversion periods, the conversion principle of the first-order differential delta sigma-delta ADC on the direct current signal can be obtained:
wherein Vref is the reference voltage of the analog-to-digital conversion circuit. At this time, the quantization error of Out1 isThe quantization error of Out2 is +.>
As can be seen from the expressions Δq1 and Δq2, when Num > 1 (i.e., isd_adc2 is not reset), max (Δq2) < max (Δq1), that is, the quantization error of isd_adc2 is smaller than isd_adc1, and the conversion accuracy is higher than isd_adc1.
Referring to the workflow shown in fig. 3, after isd_adc1 outputs Out1, the control module may compare Out1 with Temp.
If the input signal is converted for the first time, it is possible to satisfy that the absolute value of the difference between Out1 and Temp is greater than the threshold Vth (corresponding to the above-mentioned first and second difference thresholds, which are the same at this time), and further, the control module may set Out to Out1 and output, set Temp to Out1, num to 0, and reset isd_adc1 and isd_adc2.
After this, isd_adc1 and isd_adc2 may enter the next conversion cycle, repeat the above process, and continue to convert the input signal Vin.
If the absolute value of the difference between Out1 and Temp is not greater than the threshold Vth, the input signal can be considered as a direct current signal, and the control module can set Out to Out2 and output after ISD_ADC2 is output, or output Out2 which is the last time as Out; resetting isd_adc1, not resetting isd_adc2; adding 1 to Num, judging whether Num is larger than or equal to Nth (corresponding to the second number), if Num is larger than or equal to Nth, resetting Num, resetting ISD_ADC2 and entering the next conversion period, otherwise, directly entering the next conversion period. Wherein, temp may be unchanged, or Temp may be set to Out1.
If the absolute value of the difference between Out1 and Temp is greater than the threshold Vth, the control module may consider the input signal not to be a dc signal, at which time it may clear Num and set Out to Out1 and output, temp to Out1, reset isd_adc1 and isd_adc2, and enter the next conversion cycle.
Through the above workflow, the isd_adc1 may output a conversion result Out1 of one conversion period, and when the input signal includes a dc signal, the isd_adc2 may output a conversion result Out2 obtained by converting the input signal of a plurality of conversion periods, and further, the control module may output Out1 when the input signal is not a dc signal, and output Out2 when the input signal is a dc signal. When the input signal is a direct current signal, the quantization error of Out2 output by the control module is smaller than that of unselected Out1, so that the conversion precision of the analog-to-digital conversion circuit can be improved.
The embodiment of the application also provides a control method of the analog-to-digital conversion circuit, which can be used for controlling the analog-to-digital conversion circuit. The specific processing of the control method is the same as that described above, and the description is omitted in this embodiment.
Referring to the control method flowchart of the analog-to-digital conversion circuit shown in fig. 4, the method may be as follows:
step 401, controlling a first analog-to-digital conversion module to periodically convert an input signal according to a first conversion period, and outputting a first conversion result;
step 402, controlling a second sigma-delta analog-to-digital conversion module to convert the input signal in a first number of second conversion periods and output a second conversion result, wherein the first number is an integer greater than 1;
step 403, determining, by the control module, a target conversion result of the input signal according to the second conversion result and the at least two first conversion results.
Optionally, the determining the target conversion result of the input signal according to the second conversion result and at least two first conversion results includes:
obtaining a reference conversion result, the reference conversion result being determined based on the first conversion result of at least one historical first conversion period that is continuous with a current first conversion period;
And determining that the target conversion result is the first conversion result or the second conversion result of the current first conversion period according to the difference value between the first conversion result of the current first conversion period and the reference conversion result.
Optionally, the determining that the target conversion result is the first conversion result or the second conversion result of the current first conversion period according to the difference value between the first conversion result and the reference conversion result of the current first conversion period includes:
determining that the target conversion result is the first conversion result of the current first conversion period when the difference between the first conversion result of the current first conversion period and the reference conversion result is greater than a first difference threshold;
and determining the target conversion result as the second conversion result when the difference value between the first conversion result and the reference conversion result of the current first conversion period is not greater than a first difference value threshold.
Optionally, the method further comprises:
updating the reference conversion result to the first conversion result of the current first conversion period when the difference value between the first conversion result of the current first conversion period and the reference conversion result is larger than a first difference value threshold value.
Optionally, the method further comprises:
and controlling the first analog-to-digital conversion module to reset when the conversion of each conversion period is completed.
Optionally, during the conversion of the input signal in the first number of second conversion periods, if the difference between the first conversion result and the reference conversion result in the current first conversion period is not greater than a second difference threshold, the second sigma-delta analog-to-digital conversion module does not reset.
Optionally, the method further comprises:
and when the difference value between the first conversion result and the reference conversion result of the current first conversion period is larger than a second difference value threshold value, the control module controls the second sigma-delta analog-to-digital conversion module to reset.
Optionally, when the difference between the first conversion result and the reference conversion result in the current first conversion period is not greater than a second difference threshold, the state of the input signal is used as a target state;
the method further comprises the steps of:
and during the period that the input signal is continuously in the target state, when the second sigma-delta analog-to-digital conversion module finishes converting the input signal in a second continuous number of second conversion periods, controlling the second sigma-delta analog-to-digital conversion module to reset, wherein the second number is an integer greater than or equal to the first number.
Optionally, the controlling the second sigma-delta analog-to-digital conversion module to reset when the second sigma-delta analog-to-digital conversion module finishes converting the input signal in a second consecutive number of second conversion periods during the period that the input signal is continuously in the target state includes:
during the period that the input signal is continuously in the target state, counting a second conversion period after the conversion of the second sigma-delta analog-to-digital conversion module by the control module, and controlling the second sigma-delta analog-to-digital conversion module to reset when the count is greater than or equal to the second number
Optionally, the method further comprises:
and controlling the second sigma-delta analog-to-digital conversion module to enable by the control module when the difference value between the first conversion result and the reference conversion result of the current first conversion period is not greater than a third difference value threshold.
Optionally, the method further comprises:
and when the difference value between the first conversion result and the reference conversion result of the current first conversion period is larger than a third difference value threshold value, controlling the second sigma-delta analog-to-digital conversion module to be closed by the control module.
Optionally, the first analog-to-digital conversion module is any one circuit type or a combination of any multiple circuit types of sigma-delta ADC, successive approximation ADC, flash ADC and pipeline ADC.
In an embodiment of the present application, the analog-to-digital conversion circuit includes a first analog-to-digital conversion module, a second sigma-delta analog-to-digital conversion module, and a control module. The first analog-to-digital conversion module can output a first conversion result obtained by converting an input signal of each first conversion period, the second sigma-delta analog-to-digital conversion module can output a second conversion result obtained by converting input signals of a plurality of second conversion periods, and the control module can determine a target conversion result of the input signal according to the two conversion results. If the input signal is a direct current signal or a signal with a gentle change in signal amplitude, the quantization error of the second conversion result is smaller, so that the quantization error of the target conversion result of the input signal is smaller, and the conversion accuracy of the analog-to-digital conversion circuit can be improved.
The embodiment of the application also provides a chip comprising the analog-to-digital conversion circuit. The Chip (Integrated Circuit, IC) is also referred to as a Chip, which may be, but is not limited to, a SOC (System on Chip) Chip, SIP (System in package ) Chip. By configuring the analog-to-digital conversion circuit, the conversion precision of the analog-to-digital conversion circuit is improved, so that the performance of the chip is correspondingly improved.
The embodiment of the application also provides electronic equipment, which comprises an equipment main body and the chip arranged in the equipment theme. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutritional scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a quick charger, an on-board charger, an adapter, a display, a USB (Universal Serial Bus ) docking station, a stylus, a real wireless headset, a car center screen, a car, a smart wearable device, a mobile terminal, a smart home device. The intelligent wearing equipment comprises, but is not limited to, an intelligent watch, an intelligent bracelet and a cervical vertebra massage instrument. Mobile terminals include, but are not limited to, smartphones, notebook computers, tablet computers, POS (point of sales terminal, point of sale terminal) machines. The intelligent household equipment comprises, but is not limited to, an intelligent socket, an intelligent electric cooker, an intelligent sweeper and an intelligent lamp. According to the electronic equipment, the analog-to-digital conversion circuit is configured, so that the conversion precision of the analog-to-digital conversion circuit is improved, and the performance of the electronic equipment is correspondingly improved.
The foregoing description is not intended to limit the preferred embodiments of the present application, but is not intended to limit the scope of the present application, and any such modifications, equivalents and adaptations of the embodiments described above in accordance with the principles of the present application should and are intended to be within the scope of the present application, as long as they do not depart from the scope of the present application.
Claims (15)
1. An analog-to-digital conversion circuit is characterized by comprising a first analog-to-digital conversion module, a second sigma-delta analog-to-digital conversion module and a control module;
the first analog-to-digital conversion module is configured to periodically convert an input signal according to a first conversion period and output a first conversion result;
the second sigma-delta analog-to-digital conversion module is configured to convert an input signal in a first number of second conversion periods and output a second conversion result, wherein the first number is an integer greater than 1;
the control module is configured to determine a target conversion result of the input signal according to the second conversion result and at least two first conversion results.
2. The analog-to-digital conversion circuit of claim 1, wherein the control module is configured to:
obtaining a reference conversion result, the reference conversion result being determined based on the first conversion result of at least one historical first conversion period that is continuous with a current first conversion period;
and determining that the target conversion result is the first conversion result or the second conversion result of the current first conversion period according to the difference value between the first conversion result of the current first conversion period and the reference conversion result.
3. The analog-to-digital conversion circuit of claim 2, wherein the control module is configured to:
determining that the target conversion result is the first conversion result of the current first conversion period when the difference between the first conversion result of the current first conversion period and the reference conversion result is greater than a first difference threshold;
and determining the target conversion result as the second conversion result when the difference value between the first conversion result and the reference conversion result of the current first conversion period is not greater than a first difference value threshold.
4. The analog-to-digital conversion circuit of claim 2, wherein the control module is further configured to:
updating the reference conversion result to the first conversion result of the current first conversion period when the difference value between the first conversion result of the current first conversion period and the reference conversion result is larger than a first difference value threshold value.
5. The analog-to-digital conversion circuit of claim 1, wherein the first analog-to-digital conversion module is configured to reset upon completion of conversion for each first conversion period.
6. The analog-to-digital conversion circuit of any one of claims 1-5, wherein the second sigma-delta analog-to-digital conversion module is configured to:
And during the conversion period of the input signal in the first number of second conversion periods, if the difference value between the first conversion result and the reference conversion result of the current first conversion period is not larger than a second difference value threshold value, not resetting.
7. The analog-to-digital conversion circuit of claim 6, wherein the control module is configured to:
and when the difference value between the first conversion result and the reference conversion result of the current first conversion period is larger than a second difference value threshold value, controlling the second sigma-delta analog-to-digital conversion module to reset.
8. The analog-to-digital conversion circuit of claim 6, wherein the state of the input signal is a target state when a difference between the first conversion result of a current first conversion period and the reference conversion result is not greater than a second difference threshold;
the second sigma-delta analog-to-digital conversion module is further configured to:
resetting is performed upon completion of a transition of the input signal during a second number of consecutive transition periods during which the input signal is continuously in the target state, wherein the second number is an integer greater than or equal to the first number.
9. The analog-to-digital conversion circuit of claim 8, wherein the control module is configured to:
and counting a second conversion period of the second sigma-delta analog-to-digital conversion module after conversion is completed during the period that the input signal is continuously in the target state, and controlling the second sigma-delta analog-to-digital conversion module to reset when the count is greater than or equal to the second number.
10. The analog-to-digital conversion circuit of claim 1, wherein the control module is further configured to:
and controlling the second sigma-delta analog-to-digital conversion module to enable when the difference value between the first conversion result and the reference conversion result of the current first conversion period is not greater than a third difference value threshold.
11. The analog-to-digital conversion circuit of claim 1, wherein the control module is further configured to:
and when the difference value between the first conversion result and the reference conversion result of the current first conversion period is larger than a third difference value threshold value, controlling the second sigma-delta analog-to-digital conversion module to be closed.
12. The analog-to-digital conversion circuit of claim 1, wherein the first analog-to-digital conversion module is any one or a combination of any multiple of a sigma-delta ADC, a successive approximation ADC, a flash ADC, and a pipelined ADC.
13. A method of controlling an analog-to-digital conversion circuit, the analog-to-digital conversion circuit comprising a first analog-to-digital conversion module, a second sigma-delta analog-to-digital conversion module, and a control module, the method comprising:
the first analog-to-digital conversion module is controlled to periodically convert an input signal according to a first conversion period and output a first conversion result;
controlling the second sigma-delta analog-to-digital conversion module to convert input signals in a first number of second conversion periods and output a second conversion result, wherein the first number is an integer greater than 1;
and determining a target conversion result of the input signal according to the second conversion result and at least two first conversion results through the control module.
14. A chip comprising an analog to digital conversion circuit as claimed in any one of claims 1 to 12.
15. An electronic device comprising an analog to digital conversion circuit as claimed in any of claims 1 to 12.
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|---|---|---|---|
| CN202210727072.0A CN117335807A (en) | 2022-06-24 | 2022-06-24 | Analog-to-digital conversion circuit, control method, chip and electronic equipment |
| PCT/CN2023/100641 WO2023246630A1 (en) | 2022-06-24 | 2023-06-16 | Analog-to-digital conversion circuit, control method, chip, and electronic device |
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| CN202210727072.0A CN117335807A (en) | 2022-06-24 | 2022-06-24 | Analog-to-digital conversion circuit, control method, chip and electronic equipment |
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| US5030954A (en) * | 1990-09-17 | 1991-07-09 | General Electric Company | Double rate oversampled interpolative modulators for analog-to-digital conversion |
| DE60215463T2 (en) * | 2002-05-22 | 2007-02-08 | Freescale Semiconductor, Inc., Austin | Analog-to-digital converter arrangement and method |
| JP4488951B2 (en) * | 2005-04-26 | 2010-06-23 | 富士通株式会社 | Complex sigma-delta analog-to-digital converter and receiver |
| US8576104B2 (en) * | 2011-06-22 | 2013-11-05 | Linear Technology Corporation | Simultaneously-sampling single-ended and differential two-input analog-to-digital converter |
| US8604960B2 (en) * | 2011-10-28 | 2013-12-10 | Lsi Corporation | Oversampled data processing circuit with multiple detectors |
| JP2015103820A (en) * | 2013-11-20 | 2015-06-04 | 株式会社東芝 | Analog/digital converter and analog/digital conversion method |
| US9654132B2 (en) * | 2015-07-08 | 2017-05-16 | Marvell World Trade Ltd. | Hybrid charge-sharing charge-redistribution DAC for successive approximation analog-to-digital converters |
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