CN117155423A

CN117155423A - 100BASE-TX transceiver and 100BASE-TX transceiving method

Info

Publication number: CN117155423A
Application number: CN202310527998.XA
Authority: CN
Inventors: 徐嘉星; 黄俊嘉
Original assignee: Dafa Technology Co ltd
Current assignee: Dafa Technology Co ltd
Priority date: 2022-05-30
Filing date: 2023-05-11
Publication date: 2023-12-01

Abstract

The invention discloses a 100BASE-TX transceiver and a 100BASE-TX transceiving method. The transceiver includes a receiving circuit, a transmitting circuit and a noise suppressing circuit. The receiving circuit receives an input data according to a receiving clock to generate a receiving data. The transmitting circuit transmits a transmitting data according to a transmitting clock to generate an output data, wherein the transmitting clock is forced to be synchronous with the receiving clock. The noise suppression circuit applies noise suppression to the received data according to the transmitted data to generate noise-suppressed received data.

Description

100BASE-TX transceiver and 100BASE-TX transceiving method

Technical Field

The present invention relates to 100BASE-TX networking, and more particularly to a 100BASE-TX transceiver (transceiver) with a transmit clock synchronized to a receive clock for noise suppression, such as near-end crosstalk cancellation (near-end crosstalk cancellation), and related methods.

Background

100BASE-TX is a technical name of a high-speed ethernet network (Fast Ethernet over twisted pair cable) through twisted pair wires, which was published in 1995 as an 802.3u standard (hereinafter referred to as IEEE 802.3u-1995 standard) made by the institute of electrical and electronics engineers (Institute of Electrical and Electronics Engineers, IEEE), specifically, 100BASE-TX is a high-speed ethernet standard for a local area network (local area network, LAN), where "100" represents a maximum transmission rate of 100 megabits/second (Mbps), "BASE" represents baseband signaling, "T" represents twisted pair-pair intertwining, and "TX" represents that this application employs a category 5 cable (CAT 5), in which two pairs of copper wires would be used to support a transmission rate of 100 megabits/second. In the case of media dependent interface (Medium Dependent Interface, MDI) signals output from a 100BASE-TX transmitter and transmitted over network lines longer than 100 meters, a repeater (repeater) is typically required to extend the transmission distance between two network devices, which, however, increases installation costs and installation difficulty.

Furthermore, the IEEE 802.3u-1995 standard does not formulate a set of clock synchronization mechanisms (e.g., master-slave) for a Transmit (TX) clock used by a 100BASE-TX transmitter and a Receive (RX) clock used by a 100BASE-TX receiver, since the transmit clock and the receive clock do not have the same frequency, near-end crosstalk interference caused by the transmitter cannot be eliminated. With respect to long-distance transmission, near-end crosstalk will deteriorate the signal-to-noise ratio (signal-to-noise ratio) of the connection and become a significant bottleneck for extending the transmission distance.

Thus, there is a need for an innovative 100BASE-TX transceiver design that eliminates or mitigates near-end crosstalk and thus extends transmission distances without the need for any repeaters.

Disclosure of Invention

It is an object of the present invention to provide a 100BASE-TX transceiver and related method having a transmit clock synchronized with a receive clock to achieve noise suppression.

In one embodiment of the present invention, a 100BASE-TX transceiver is disclosed. The 100BASE-TX transceiver includes a receive circuit, a transmit circuit, and a noise suppression circuit. The receiving circuit is used for receiving input data according to a receiving clock so as to generate receiving data. The transmitting circuit is used for transmitting a transmitting data according to a transmitting clock to generate an output data, wherein the transmitting clock is forced to be synchronous with the receiving clock. The noise suppression circuit is used for applying noise suppression to the received data according to the transmitted data so as to generate noise-suppressed received data.

In one embodiment of the invention, a 100BASE-TX transceiving method is disclosed. The 100BASE-TX receiving and transmitting method comprises the following steps: receiving input data according to a receiving clock to generate receiving data; transmitting a transmission data according to a transmission clock to generate an output data, wherein the transmission clock is forced to be synchronous with the receiving clock; and applying noise suppression to the received data according to the transmitted data to generate noise-suppressed received data.

The 100BASE-TX transceiver of the present invention can support a noise suppression function (e.g., near-end crosstalk cancellation) by forcing the transmit clock to synchronize with the receive clock.

Drawings

Fig. 1 is a schematic diagram of a 100BASE-TX transceiver in accordance with an embodiment of the present invention.

Fig. 2 is a schematic diagram of an implementation of a 100BASE-TX transceiver in accordance with an embodiment of the present invention.

Fig. 3 is a flow chart of a 100BASE-TX transceiving method according to an embodiment of the present invention.

[ symbolic description ]

100 200:100BASE-TX transceiver

102:100BASE-TX transmitter

104:100BASE-TX receiver

112:4b/5b encoder circuit

114 serializer circuit

116 124 digital pre-stage circuit

Transmission digital-to-analog converter and driver circuit 118

122 receive front-end and analog-to-digital converter circuit

126 deserializer circuit

128:4b/5b decoder circuit

202 transfer circuit

204 receiving circuit

206 noise suppression circuit

208 clock generator circuit

210 clock and data recovery circuit

212 near-end crosstalk cancellation circuit

214 receive front-end circuitry

216 analog-to-digital converter circuit

218 digital-to-analog converter circuit

220 transfer driver circuit

D_TX: transmit data

D_OUT: output data

D_IN input data

DRX receiving data

DRX noise suppressed received data

CLK_C common clock

CLK_TX transfer clock

CLK_RX receiving clock

302 Step 304, 306, 308

Detailed Description

Certain terms are used throughout the description and claims to refer to particular components. It will be appreciated by those skilled in the art that a hardware manufacturer may refer to the same element by different names, and that the description and claims may not refer to the same element by different names but may refer to the same element by different functional differences. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the terms "couple" or "couple" herein include any direct and indirect electrical connection, and thus, if a first device couples to a second device, that connection may be made directly to the second device, or indirectly to the second device via other devices and connections.

Fig. 1 is a schematic diagram of a 100BASE-TX transceiver in accordance with an embodiment of the present invention. The 100BASE-TX transceiver 100 may be considered a combination of a 100BASE-TX transmitter (transmitter) 102 and a 100BASE-TX receiver (receiver) 104. The 100BASE-TX transmitter 102 includes a 4b/5b encoder circuit (denoted as 4b/5b encoder in the figure) 112, a serializer (serializer) circuit (denoted as serializer in the figure) 114, a digital front-end (D-PMA) circuit (denoted as D-PMA in the figure, which is also known as Digital part of Physical Medium Attachment unit) 116, and a Transmit (TX) digital-to-analog converter (DAC) and a driver circuit (denoted as transmit digital-to-analog converter & driver) 118. The 100BASE-TX receiver 104 includes Receive (RX) front-end and analog-to-digital converter (ADC) circuits (labeled receive front-end & ADC) 122, digital front-end circuits (labeled D-PMA) 124, de-serializer (de-serializer) circuits (labeled de-serializer) 126, and 4b/5b decoder circuits (labeled 4b/5b decoder) 128. Note that only elements relevant to the present invention are shown in fig. 1, and in fact, 100BASE-TX transmitter 102 may include additional elements to perform other functions and/or 100BASE-TX receiver 104 may include additional elements to perform other functions.

The 100BASE-TX transmitter 102 receives media independent interface (medium independent interface, MII) data from the media access control (media access control, MAC) layer and transmits MDI signals over twisted pair wires. The 100BASE-TX receiver 104 receives MDI signals from the twisted pair and outputs MII data to the MAC layer. The main differences between the proposed 100BASE-TX transceiver 100 and the conventional 100BASE-TX transceiver are as follows: by forcing the transmit clock to be synchronized with the receive clock, the digital pre-stage 124 may be configured to support noise suppression functions (e.g., near-end crosstalk cancellation). Since the present invention focuses on the innovative noise suppression design implemented in the 100BASE-TX transceiver 100, further description of the basic operating principles of the 100BASE-TX transmitter 102 and the 100BASE-TX receiver 104 is omitted here for brevity.

Fig. 2 is a schematic diagram of an implementation of a 100BASE-TX transceiver in accordance with an embodiment of the present invention. Note that only the elements related to the present invention are shown in fig. 2, for example, a portion of the 100BASE-TX transceiver 100 shown in fig. 1 may be implemented by the 100BASE-TX transceiver 200 shown in fig. 2. The 100BASE-TX transceiver 200 may include a transmit circuit 202, a receive circuit 204, a noise suppression circuit 206, and a clock generator (clock generator) circuit 208. The receiving circuit 204 is configured to receive input data d_in according to a receiving clock clk_rx to generate receiving data (RX data) d_rx, for example, the input data d_in may be MDI signals received from twisted pair. The transmitting circuit 202 is configured to output transmission data (TX data) d_tx according to a transmission clock clk_tx to generate output data d_out, for example, the transmission data d_tx may be an output of the serializer circuit 116 shown in fig. 1, and the output data d_out may be an MDI signal transmitted by a twisted pair. In the present embodiment, the transmission clock clk_tx is intentionally forced to be synchronized with the reception clock clk_rx, and since the transmission clock clk_tx and the reception clock clk_rx have the same frequency, noise suppression is realized. The 100BASE-TX transceiver 200 with noise suppression may allow long range transmissions in an environment without repeaters, as compared to a conventional 100BASE-TX transceiver without noise suppression. Specifically, the noise suppression circuit 206 is configured to apply noise suppression to the received data d_rx according to the transmitted data d_tx to generate noise-suppressed received data d_rx', which may be used as an input of the deserializer circuit 126 shown in fig. 1, for example.

As described above, the transmit clock clk_tx is intentionally forced to synchronize with the receive clock clk_rx, and in this embodiment, the clock generator 208 is configured to generate a common clock clk_c, wherein the receive clock clk_rx and the transmit clock clk_tx are both set by the same common clock clk_c. Since the receive clock clk_rx and the transmit clock clk_tx are both set by the same common clock clk_c, the transmit clock clk_tx is ensured to be synchronized with the receive clock clk_rx, thereby allowing the noise suppression function to be implemented in the noise suppression circuit 206. For example, the clock generator 208 may be implemented by a clock and data recovery (clock and data recovery) Circuit (CDR) 210, and the clock and data recovery circuit 210 is configured to generate a receive recovery clock (RX recovered clock) according to the received data d_rx and output the receive recovery clock as the common clock clk_c. Any clock and data recovery technique that can derive a receive recovered clock from the received data D_RX can be used by the clock and data recovery circuit 210. After the receiving recovery clock is available, the noise suppression circuit 206 performs noise suppression on the received data d_rx according to the transmitted data d_tx and the receiving recovery clock (e.g. the common clock clk_c), for example, the noise suppression circuit 206 may be a near-end crosstalk cancellation circuit (NC) 212 for applying near-end crosstalk cancellation to the received data d_rx to reduce or mitigate near-end crosstalk caused by the transmitter in the received data d_rx.

The transmit clock CLK TX is intentionally forced to synchronize with the receive clock CLK RX to allow the noise suppression function to be implemented in the noise suppression circuit 206. In this embodiment, the receive circuit 204 may include a receive front-end circuit (RXFE) 214 and an analog-to-digital converter circuit (ADC) 216; and the transmit circuit 202 may include a digital-to-analog converter circuit (labeled DAC) 218 and a transmit driver circuit (labeled transmit driver) 220. The receiving pre-stage 214 is used for receiving the input data D_IN. The analog-to-digital converter circuit 216 is configured to perform analog-to-digital conversion on the input data d_in according to a reception clock clk_rx set by a reception recovery clock (e.g., a common clock clk_c), IN other words, the analog-to-digital converter circuit 216 is configured to convert the input data d_in into the reception data d_rx according to the reception clock clk_rx set by the reception recovery clock (e.g., the common clock clk_c). The dac circuit 218 is configured to perform digital-to-analog conversion on the transmission data d_tx according to the transmission clock clk_tx set by the reception recovery clock (e.g., the common clock clk_c), in other words, the dac circuit 218 is configured to convert the transmission data d_tx into the output data d_out according to the transmission clock clk_tx set by the reception recovery clock (e.g., the common clock clk_c). The transfer driver circuit 220 is used to transfer the output data d_out. Since the transmit clock clk_tx is synchronized with the receive clock clk_rx (i.e., the transmit clock clk_tx and the receive clock clk_rx have the same frequency and phase), near-end crosstalk caused by the transmit circuit 202 can be successfully estimated IN the near-end crosstalk cancellation circuit 212 and can be mitigated/cancelled from the received data d_rx obtained from the receive circuit 204, thereby enabling the input data d_in to be transmitted from the link partner (link partner) to a network device (using the 100BASE-TX transceiver 200 of the present invention) over a longer distance without any repeater.

Fig. 3 is a flow chart of a 100BASE-TX transceiving method according to an embodiment of the present invention. The 100BASE-TX transceiving method may be employed by the 100BASE-TX transceiver 100/200. The steps need not be performed in exactly the order shown in fig. 3, provided that substantially the same results are obtained. In step 302, it is checked whether the received recovered clock has been locked by the clock and data recovery circuit 210, if so, the flow proceeds to step 304, otherwise, the flow returns to step 302. At step 304, the transmit circuit 202 is enabled to use the receive recovery clock as its own transmit clock. In step 306, near-end crosstalk cancellation circuit 212 enables the near-end crosstalk cancellation function to generate and output noise-suppressed received data D_RX'. At step 308, it is checked whether the connection between the 100BASE-TX device and the connection partner is successful, if so, the process ends, otherwise, the process returns to step 302. Since those skilled in the art will readily appreciate the details of these steps after reading the above description of the 100BASE-TX transceiver 100/200, further description is omitted herein for brevity.

The foregoing description is only of the preferred embodiments of the present invention, and all equivalent changes and modifications made in the claims should be construed to fall within the scope of the present invention.

Claims

1. A 100BASE-TX transceiver, comprising:

a receiving circuit for receiving input data according to a receiving clock to generate receiving data;

a transmitting circuit for transmitting the transmission data according to a transmission clock to generate output data, wherein the transmission clock is forced to be synchronous with the receiving clock; and

and a noise suppression circuit for applying noise suppression to the received data according to the transmitted data to generate noise-suppressed received data.

2. The 100BASE-TX transceiver of claim 1, wherein the noise suppression circuit is a near-end crosstalk cancellation circuit and the noise suppression is near-end crosstalk cancellation.

3. The 100BASE-TX transceiver of claim 1, further comprising:

the clock generator circuit is used for generating a common clock, wherein the receiving clock and the transmitting clock are set by the same common clock.

4. The 100BASE-TX transceiver of claim 3, wherein the clock generator circuit is a clock and data recovery circuit for generating a receive recovered clock according to the received data and outputting the receive recovered clock as the common clock.

5. The 100BASE-TX transceiver of claim 4, wherein the noise suppression circuit is configured to apply the noise suppression to the received data based on the transmit data and the receive recovery clock.

6. The 100BASE-TX transceiver of claim 1, wherein the receive circuit comprises:

a receiving front-end circuit for receiving the input data; and

the analog-to-digital converter circuit is used for converting the input data into the received data according to the received clock.

7. The 100BASE-TX transceiver of claim 1, wherein the transmit circuit comprises:

a digital-to-analog converter circuit for converting the transmission data into the output data according to the transmission clock; and

and a transmission driver circuit for transmitting the output data.

8. A 100BASE-TX transceiving method, comprising:

receiving input data according to a receiving clock to generate receiving data;

transmitting the transmission data according to a transmission clock to generate output data, wherein the transmission clock is forced to be synchronous with the receiving clock; and

applying noise suppression to the received data in accordance with the transmitted data to produce noise-suppressed received data.

9. The 100BASE-TX transmit-receive method of claim 8, wherein the noise suppression is near-end crosstalk cancellation.

10. The 100BASE-TX transceiving method of claim 8, further comprising:

generating a common clock; and

the same common clock is used to set the receive clock and the transmit clock.

11. The 100BASE-TX transceiving method according to claim 10, wherein the step of generating said common clock comprises:

performing clock and data recovery according to the received data to generate a received recovered clock; and

the reception recovered clock is output as the common clock.

12. The 100BASE-TX transmit and receive method of claim 11, wherein the noise suppression is applied to the received data based on the transmit data and the receive recovery clock.

13. The 100BASE-TX transceiving method according to claim 8, wherein the step of receiving said input data according to said receive clock comprises:

analog-to-digital conversion is performed according to the receive clock to convert the input data into the receive data.

14. The 100BASE-TX transmitting and receiving method of claim 8, wherein transmitting the transmission data according to the transmission clock comprises:

digital-to-analog conversion is performed according to the transmit clock to convert the transmit data into the output data.