WO2017213138A1

WO2017213138A1 - Reception device

Info

Publication number: WO2017213138A1
Application number: PCT/JP2017/020977
Authority: WO
Inventors: 宣明松平; 岸上　友久
Original assignee: 株式会社デンソー
Priority date: 2016-06-08
Filing date: 2017-06-06
Publication date: 2017-12-14
Also published as: JP2017220820A; JP6524969B2

Abstract

In the present invention a correction processing unit (144) of a receiver (140) learns a correction amount by comparing an output signal from an ADC (142) and an ideal waveform during an arbitration phase of a communication frame. Then, the correction processing unit (144) uses the correction amount learned during the arbitration phase to correct and output the waveform of the output signal from the ADC (142) during a data phase of the communication frame.

Description

Receiver

Cross-reference of related applications

This international application claims priority based on Japanese Patent Application No. 2016-114506 filed with the Japan Patent Office on June 8, 2016, and is based on Japanese Patent Application No. 2016-114506. The entire contents are incorporated by reference into this international application.

The present disclosure relates to a receiving device used in a communication system in which a plurality of communication devices transmit and receive communication signals via a common transmission path.

A bus connection type communication system in which a plurality of communication devices transmit and receive communication signals via a common communication line is known. In this type of communication system, signal reflection occurs due to impedance mismatch at the branch point between the branch line and the communication line to which each communication device is connected and the input / output point of each communication device, and the signal waveform deteriorates. A phenomenon in which a signal waveform is disturbed by such a reflected wave is called ringing.

In response to the above problem, Patent Document 1 discloses that when a signal transitions from dominant to recessive, it is disturbed by ringing by outputting a high level signal for a certain period of time regardless of the received communication signal. A technique for masking the output is described.

JP 2011-135283 A

The technique described in Patent Document 1 is based on the premise that waveform disturbance due to ringing converges within a communication period of one bit of code. That is, assuming that the communication time length for one bit of code is TD and the time length in which waveform distortion due to ringing occurs is TRING, the technique described in Patent Document 1 can be applied only under the condition of TD> TRING. The As a result of the inventor's investigation, if the waveform distortion is to be masked in a situation where TD ≦ TRING, the signal described in Patent Document 1 cannot be applied because all signals for one bit of code are masked. Was found.

In recent years, communication standards such as CAN FD (registered trademark) capable of higher-speed communication than before have been proposed. Note that CAN FD is an abbreviation for Controller-Area-Network-with-Flexible-Data-rate. In this CAN FD, if the conventional CAN (registered trademark), the communication speed of 500 kbps is increased to a maximum of 5 Mbps. That is, the time length per bit of the code is reduced to 1/10. On the other hand, since the time length in which the waveform is disturbed by ringing is the same regardless of the communication speed, it is difficult to apply the technique described in Patent Document 1.

In one aspect of the present disclosure, it is preferable to provide a technique for appropriately self-correcting waveform disturbance due to ringing and realizing high-speed bus communication.
A receiving device according to an aspect of the present disclosure includes: a communication control device provided in a communication device that constructs a communication system in which a plurality of communication devices transmit and receive communication signals via a common communication line; and a common communication line It functions as an interface between them. The receiving device includes an AD conversion unit, a learning unit, and a correction unit.

The AD conversion unit is configured to convert a communication signal received via a common communication line into a digital signal and output the digital signal. The learning unit receives a predetermined communication signal and converts the received signal, which is a waveform of a digital signal when converted by the AD conversion unit, and a given ideal waveform representing a waveform of a reference digital signal corresponding to the communication signal Is configured to create waveform correction information. This waveform correction information is information relating to the difference between the received waveform and the ideal waveform. The learning unit is configured to save the created waveform correction information in the storage unit. The correction unit generates a correction signal that is a signal obtained by correcting the waveform of the digital signal converted by the AD conversion unit after the waveform correction information is stored using the waveform correction information stored in the storage unit, and generates the correction signal. The corrected signal is output to the communication control device.

A receiving apparatus according to an aspect of the present disclosure calculates a waveform correction information based on a difference between a received waveform obtained by digitally converting a received communication signal and a given ideal waveform, thereby reducing a small-scale circuit in a short time. You can learn the amount of waveform correction. By using the waveform correction information acquired by such learning, waveform disturbance due to ringing can be appropriately self-corrected and high-speed bus communication can be realized.

The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The outline of the drawing is as follows.
FIG. 1 is a block diagram illustrating a schematic configuration of a communication system. FIG. 2 is a diagram illustrating a circuit configuration of the ECU. FIG. 3 is a diagram illustrating a circuit configuration of the receiver. FIG. 4 is a diagram illustrating a configuration of a CAN FD communication frame. FIG. 5 is an operation waveform diagram regarding the receiver. FIG. 6 is a diagram illustrating an example of a comparison between an output signal waveform and an ideal waveform. FIG. 7 is an operation waveform diagram regarding the receiver. FIG. 8 is a flowchart showing the procedure of the learning process. FIG. 9 is a diagram illustrating bit time divisions related to CAN FD. FIG. 10 is a diagram illustrating rising noise in the output signal. FIG. 11 is a diagram illustrating falling noise in the output signal. FIG. 12 is a flowchart showing the procedure of the correction process.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In addition, this indication is not limited to the following embodiment, It is possible to implement in various aspects.
[Description of configuration of communication system]
The configuration of the communication system according to the embodiment will be described with reference to FIG. This communication system is configured such that a plurality of ECUs 100 transmit and receive communication signals via a bus 10 that is a common communication line. A communication signal transmitted and received in this communication system is composed of a signal sequence in bit units represented by binary values of Dominant / Recessive. ECU is an abbreviation for Electronic Control Unit.

In this communication system, each ECU 100 functions as a communication device according to the present disclosure. In the present embodiment, it is assumed that CAN FD, which is a well-known standard, is used as a communication protocol between the ECUs 100. The bus 10 used in the communication system of the present embodiment is a two-wire bus composed of a first communication line 11 and a second communication line 12. As illustrated in FIG. 2, Dominant / Recessive is expressed by the potential difference between the potential of the first communication line 11 and the potential of the second communication line 12. Hereinafter, the potential of the first communication line 11 is “Sig-H”, and the potential of the second communication line 12 is “Sig-L”. This communication system is a so-called bus connection type network form. Specifically, in this communication system, a plurality of branch lines are branched from a bus 10 as a trunk line, and an ECU 100 is connected to each branch line.

[Description of ECU configuration]
A configuration common to each ECU 100 will be described with reference to FIG. As illustrated in FIG. 2, one ECU 100 includes a communication controller 110 and a transceiver 120.

The communication controller 110 is an information processing apparatus including a CPU, a ROM, a RAM, and the like. The communication controller 110 is embodied by, for example, a microcontroller that integrates functions as a computer system. The communication controller 110 executes processing for communication control. The communication controller 110 includes a Tx terminal and an Rx terminal as communication terminals. The Tx terminal and the Rx terminal are connected to the communication terminal of the transceiver 120, respectively. Note that the communication controller 110 corresponds to the communication control device according to the present disclosure.

The transceiver 120 is a device that functions as an interface between the bus 10 and the communication controller 110. The transceiver 120 includes a transmitter 130 and a receiver 140. The transmitter 130 and the receiver 140 are respectively connected to both the first communication line 11 and the second communication line 12.

The transmitter 130 has a function of converting a transmission signal output from the Tx terminal of the communication controller 110 into a communication signal and transmitting the communication signal to the first communication line 11 and the second communication line 12. A transmission signal output from the Tx terminal of the communication controller 110 is referred to as a “Tx signal”. Specifically, in the state where the Tx signal is Recessive, the first communication line 11 and the second communication line 12 are not supplied without flowing out the current to the first communication line 11 and drawing the current from the second communication line 12. A communication signal representing Recessive is transmitted by setting the potential difference between and to zero. On the other hand, when the Tx signal is at the Dominant level, a current is flown out to the first communication line 11 and a current is drawn from the second communication line 12, so that the first communication line 11 is connected to the second communication line 12. A communication signal representing Dominant is sent out by generating a potential difference in. Communication is established when communication signals representing Recessive and Dominant generated in this way are transmitted to the receiver 140 of another ECU 100 via the first communication line 11 and the second communication line 12.

The receiver 140 is an electronic circuit corresponding to the receiving device in the present disclosure. The receiver 140 is embodied by a microprocessor specialized in digital signal processing. The receiver 140 demodulates the communication signal received from the first communication line 11 and the second communication line 12 and outputs the received signal to the Rx terminal of the communication controller 110. A reception signal output from the receiver 104 to the Rx terminal of the communication controller 110 is referred to as an “Rx signal”. The receiver 140 has a function of correcting the distortion of the waveform of the communication signal due to the reflected wave generated at the branch point between the branch line and the main line connected to the bus 10 and the input / output point of the ECU 100.

[Description of receiver configuration]
The configuration of the receiver 140 will be described with reference to FIG. As illustrated in FIG. 3, the receiver 140 includes an anti-aliasing filter (hereinafter referred to as AAF) 141, an analog-digital converter (hereinafter referred to as ADC) 142, a learning determination unit 143, and a correction processing unit 144.

The AAF 141 is a low-pass filter that limits the bandwidth of the communication signal input to the ADC 142 and prevents the occurrence of aliasing noise. The ADC 142 is an electronic circuit that converts the communication signal output from the AAF 141 into a digital signal sampled at a predetermined sampling frequency (for example, 5 MHz).

The learning determination unit 143 monitors the code of the CAN FD communication frame represented by the digital signal output from the ADC 142, and sends a signal for determining the learning interval and the correction interval for the communication frame to the correction processing unit 144. This is an electronic circuit to output. The learning section is a section for learning a correction amount for correcting distortion of the signal waveform in the received communication frame. The correction section is a section in which the signal waveform is corrected using the correction amount acquired in the learning section in the received communication frame.

Referring to FIG. 4, a specific example of a learning section and a correction section for communication frames used in the CAN FD protocol will be described. As illustrated in FIG. 4, the communication frame used in the CAN FD protocol includes code regions such as SOF, Identifier, RRS, IDE, FDF, res, BRS, ESI, DLC, Data, and CRC.

The CAN FD protocol communication frame consists of two phases: an arbitration phase and a data phase. The arbitration phase is set to the first bit rate. Specifically, the arbitration phase is set to a bit rate (for example, 500 kbps) equivalent to the conventional CAN. The data phase is set to the second bit rate. Specifically, the data phase is faster than the arbitration phase, and a bit rate up to 5 Mbps can be set.

Note that CAN FD is a communication method conforming to CDMA / CA. In other words, the CAN FD is configured to perform communication timing arbitration with other ECUs 100 using the Identifier. That is, since the waveform of the communication signal is disturbed in the section of the identifier in the arbitration phase due to the collision of the communication signals from the plurality of ECUs 100, this section is not suitable for learning waveform distortion due to ringing. Therefore, in the present embodiment, a section from RRS to BRS in the arbitration phase is used as a learning section. Then, a section from BRS to CRC constituting the data phase on the high speed side is set as a correction section.

In the present embodiment, when the learning determination unit 143 detects a code corresponding to RRS from the output signal of the ADC 142, the learning determination unit 143 switches the learning signal TRen, which is a signal representing the learning section, from the Low level to the High level and outputs it. Next, when the learning determination unit 143 detects a code corresponding to BRS from the output signal of the ADC 142, the learning determination unit 143 switches and outputs the correction signal CRen, which is a signal indicating the correction section, from the Low level to the High level. When the learning determination unit 143 detects a code corresponding to CRC from the output signal of the ADC 142, the learning determination unit 143 switches the learning signal TRen and the correction signal CRen to the low level.

Returning to the explanation of FIG. The correction processing unit 144 is an electronic circuit that selectively performs learning processing and correction processing. The learning process is a process of learning a correction amount for correcting distortion of the output signal from the ADC 142. The correction process is a process of correcting distortion of the output signal based on the correction amount learned by the learning process. The correction processing unit 144 includes a memory 145 as a storage device. Note that the method by which the correction processing unit 144 realizes each function is not limited to software, and some or all of the elements may be realized by using hardware that combines a logic circuit, an analog circuit, and the like.

The correction processing unit 144 is based on a comparison between the waveform of the output signal from the ADC 142 and the ideal waveform when the learning signal TRen output from the learning determination unit 143 indicates a high level, that is, when the learning interval is valid. To learn the correction amount. The correction amount here corresponds to the waveform correction information in the present disclosure. A specific example of the learning process for learning the correction amount will be described with reference to FIGS.

The graph of FIG. 5 is a graph showing an example of a signal waveform for one bit of code in the arbitration phase of the communication frame received by the receiver 140. Among these graphs, the upper stage shows the waveform of the input signal to the ADC 142, and the lower stage shows the waveform of the output signal from the ADC 142.

As illustrated in FIG. 5, in the waveform of the input signal, the waveform is disturbed due to ringing immediately after the rise and fall of the amplitude level. Since the waveform disturbance in the input signal is reflected in the output signal from the ADC 142, the output signal does not form an accurate rectangular wave, and has a distorted shape immediately after rising and falling.

Therefore, as illustrated in FIG. 6, the correction processing unit 144 has an ideal waveform that is a reference digital signal that imitates the waveform of the output signal from the ADC 142 and the accurate signal waveform of one bit in the arbitration phase. And the voltage difference between the waveform of the output signal and the ideal waveform is calculated as a correction amount. Note that a rectangular wave represented by a broken line in the graph of FIG. 6 is an ideal waveform of 500 kbps corresponding to the arbitration phase. In the present embodiment, it is assumed that information representing such an ideal waveform is registered in advance in a memory 145 included in the correction processing unit 144.

As illustrated in FIG. 6, the correction processing unit 144 measures the difference between the amplitude levels of the output signal and the ideal waveform immediately after the amplitude level of the output signal rises above a threshold value Vth (for example, 1 V). The correction processing unit 144 acquires the measured value of the amplitude level difference as the rising correction amount Vrise. Further, the correction processing unit 144 measures the difference between the amplitude levels of the output signal and the ideal waveform immediately after the amplitude level of the output signal drops below the threshold value Vth. The correction processing unit 144 acquires the measured value of the difference in amplitude level as the fall correction amount Vfall. The correction processing unit 144 stores the acquired correction amounts for Vrise and Vfall in the memory 145.

Note that the method of learning the correction amount may be a method of obtaining an average value of correction amounts measured from a plurality of bits. Specifically, the correction processing unit 144 measures Vrise and Vfall from a plurality of codes included in the RRS to BRS areas corresponding to the learning section illustrated in FIG. The correction processing unit 144 stores the average values of Vrise and Vfall in the memory 145 as correction amounts.

On the other hand, the correction processing unit 144 uses the correction amount stored in the memory 145 when the correction signal CRen output from the learning determination unit 143 indicates a high level, that is, when the correction section is valid. The waveform of the output signal from is corrected. A specific example of this correction processing will be described with reference to FIG.

7 is a graph showing an example of a signal waveform in the process of shifting from the arbitration phase (that is, 500 kbps) of the communication frame received by the receiver 140 to the data phase (that is, 5 Mbps). As illustrated in FIG. 7, the correction processing unit 144 starts correction of the amplitude level of the output signal using the correction amounts of Vrise and Vfall when the communication frame enters the data phase and the correction signal CRen becomes High level. To do.

Specifically, as illustrated in the middle graph of FIG. 7, when the amplitude level of the output signal of the ADC 142 increases beyond the threshold value Vth, the correction processing unit 144 increases the amplitude level of the output signal by Vrise. Is added to correct the output signal. When the amplitude level of the output signal of the ADC 142 falls below the threshold value Vth, the output signal is corrected by subtracting the amplitude level from the output signal by Vfall. If the phase of the sampling clock of the ADC 142 is correctly synchronized with the communication frame in the arbitration phase and the data phase, the correction amount learned in the arbitration phase of 500 kbps may be applied to the data phase of 5 Mbps. Is possible. This is because the distortion of the signal waveform due to ringing does not depend on the data rate.

As a result of the above correction, as illustrated in the lower graph of FIG. 7, most of the influence of waveform distortion due to ringing can be removed from the corrected output signal, and a sufficient noise margin with respect to the threshold Vth can be removed. It is possible to generate a digital signal waveform having In the CAN FD, the impedance of the transceiver 120 changes depending on whether the communication signal is Recessive or Dominant. For this reason, the state of reflection that causes ringing changes depending on the rise and fall of the communication signal. Therefore, highly accurate correction can be realized by learning Vrise and Vfall as in the present embodiment.

[Description of learning procedure]
The procedure of the learning process executed by the correction processing unit 144 of the receiver 140 will be described with reference to the flowchart of FIG. This learning process is executed every time a communication frame is received by the receiver 140.

In S100, the correction processing unit 144 determines whether or not the learning signal TRen output from the learning determination unit 143 is at a high level. When the learning signal TRen is at the low level (S100: NO), the correction processing unit 144 repeats the process of S100. When the learning signal TRen is at the high level (S100: YES), the correction processing unit 144 moves the process to S102.

In S102, the correction processing unit 144 determines whether or not a rise in which the amplitude level of the output signal from the ADC 142 (hereinafter, output signal) exceeds the threshold value Vth has been detected. When the rising edge of the output signal is not detected (S102: NO), the correction processing unit 144 repeats the process of S102. When the rising edge of the output signal is detected (S102: YES), the correction processing unit 144 moves the process to S104. In S104, the correction processing unit 144 measures the difference between the amplitude level immediately after the rising of the output signal and the amplitude level immediately after the rising of the ideal waveform, and acquires the measured value as the rising correction amount Vrise.

In S106, the correction processing unit 144 determines whether or not the output signal is maintained at the High level at the sampling point of the bit timing defined in the CAN FD specification. In the CAN FD specification, as illustrated in FIG. 9, the time length for one code is divided into four segments of SYNC_SEG, PROP_SEG, PHASE_SEG1, and PHASE_SEG2. The amplitude level of the output signal recognized at the sampling point corresponding to the boundary between PHASE_SEG1 and PHASE_SEG2 in the time length of one bit of the code is recognized as the code represented by the output signal. .

Returning to the flowchart of FIG. In S106, when it is determined that the output signal is maintained at the High level at the sampling point (S106: YES), the correction processing unit 144 proceeds to S108. In S108, the correction processing unit 144 stores the rising correction amount Vrise acquired in S104 in the memory 145. If it is determined in S106 that the output signal has changed to the Low level at the sampling point (S106: NO), the correction processing unit 144 moves the process to S110.

In S110, the correction processing unit 144 rejects the rising correction amount Vrise acquired in S104 without saving. After the process of S110, the correction processing unit 144 returns the process to S102. The process in S110 will be described in detail with reference to FIG.

As illustrated in FIG. 10, when the output signal rises beyond the threshold value Vth and the amplitude level falls to the low level at the time corresponding to the sample point of the bit time section, the previous rise Is likely to be noise. Therefore, after the rising of the output signal is detected, if the output signal is at a low level at the sampling point, the learning result is rejected.

Returning to the flowchart of FIG. In S112, the correction processing unit 144 determines whether or not a falling edge in which the amplitude level of the output signal falls below the threshold value Vth is detected. When the falling edge of the output signal is not detected (S112: NO), the correction processing unit 144 repeats the process of S112. When the falling edge of the output signal is detected (S112: YES), the correction processing unit 144 moves the process to S114. In S114, the correction processing unit 144 measures the difference between the amplitude level immediately after the fall of the output signal and the amplitude level immediately after the fall of the ideal waveform, and acquires the measured value as the fall correction amount Vfall.

In S116, the correction processing unit 144 determines whether or not the timing at which the falling edge is detected in S112 is included in the PHASE_SEG2 section of the bit timing illustrated in FIG. When the timing at which the falling is detected is not included in the section of PHASE_SEG2 (S116: NO), the correction processing unit 144 moves the process to S118. In S118, the correction processing unit 144 stores the fall correction amount Vfall acquired in S114 in the memory 145.

In S116, when it is determined that the timing at which the falling is detected is included in the section of PHASE_SEG2 (S116: YES), the correction processing unit 144 moves the process to S120. In S120, the correction processing unit 144 rejects the rising correction amount Vfall acquired in S114 without saving it. After the process of S120, the correction processing unit 144 returns the process to S112.

The processing of S120 will be described in detail with reference to FIG. The communication frame received by the receiver 140 is input to the receiver 140 with a delay from the transmission timing on the transmission side. For this reason, the end of the communication signal for one bit of code is usually detected later than PHASE_SEG2 of the bit timing on the receiving side. Therefore, as illustrated in FIG. 11, when a falling edge is detected in the PHASE_SEG2 section of the bit timing, the detected falling edge is likely to be noise. For this reason, when a falling edge is detected in the section of PHASE_SEG2 after the rising edge of the output signal is detected, the learning result relating to the falling edge is rejected.

Returning to the flowchart of FIG. In S122, the correction processing unit 144 determines whether or not the correction signal CRen output from the learning determination unit 143 is at a high level. When the correction signal CRen is at the low level (S122: NO), the correction processing unit 144 returns the process to S102 and repeats the acquisition of Vrise and Vfall for the next code. When the correction signal CRen is at the high level (S122: YES), the correction processing unit 144 moves the process to S124.

In S124, the correction processing unit 144 calculates an average value for each of the rising correction amount Vrise and the falling correction amount Vfall stored in the memory 145 in S108 and S118. Then, the correction processing unit 144 stores the calculated average value of the rising correction amount Vrise and the average value of the falling correction amount Vfall in the memory 145. After S124, the correction processing unit 144 proceeds to the correction processing illustrated in FIG.

Incidentally, the flowchart illustrated in FIG. 8 represents processing assuming that Vrise and Vfall are learned for a code starting from a phase where the amplitude level of the output signal rises from the Low level to the High level. Or the correction process part 144 may be the structure which learns Vfall and Vrise for the code | symbol which starts from the aspect where the amplitude level of an output signal falls from a High level to a Low level.

In that case, it is conceivable that the correction processing unit 144 branches the learning process depending on whether a rising edge or a falling edge is detected at a timing corresponding to the start of the code. Specifically, the correction processing unit 144 branches the learning process into a sequence in which learning is performed on a code starting from a rising edge and a sequence in which learning is performed on a code starting from a falling edge. In addition, also when the code | cord | chord which starts from a fall is made into the object of learning, the correction process part 144 can learn by the procedure similar to the flowchart illustrated in FIG. Specifically, the contents of the flowchart of FIG. 8 are read as follows.

The correction processing unit 144 acquires the fall correction amount Vfall in S104 on condition that the fall is detected in S102. Then, the correction processing unit 144 stores the fall correction amount Vfall in the memory 145 in S108 on the condition that the amplitude level at the sampling point is the Low level in S106. When the amplitude level at the sampling point is the high level in S106, the correction processing unit 144 rejects the correction amount Vfall.

Further, the correction processing unit 144 acquires the rising correction amount Vrise in S114 on condition that the rising is detected in S112. Then, the correction processing unit 144 stores the rising correction amount Vrise in the memory 145 on the condition that the timing at which the rising is detected is not included in the section of PHASE_SEG2. When the rising timing is included in the PHASE_SEG2 section in S112, the correction processing unit 144 rejects the rising correction amount Vrise.

[Description of correction procedure]
The procedure of the correction process performed by the correction processing unit 144 of the receiver 140 will be described with reference to the flowchart of FIG. This correction process is executed following the learning process described above.

In S200, the correction processing unit 144 determines whether or not a rise in which the amplitude level of the output signal of the ADC 142 exceeds the threshold value Vth is detected. When the rising edge of the output signal is not detected (S200: NO), the correction processing unit 144 repeats the process of S200. When the rising edge of the output signal is detected (S200: YES), the correction processing unit 144 moves the process to S202.

In S202, the correction processing unit 144 corrects the waveform of the output signal immediately after the rise using the rise correction amount Vrise stored in the memory 145 in S124 of the above-described correction process. Specifically, the correction processing unit 144 adds the amplitude level of the output signal of the ADC 142 by the rising correction amount Vrise and outputs the Rx signal.

In S204, the correction processing unit 144 determines whether or not a fall in which the amplitude level of the output signal falls below the threshold value Vth is detected. When the falling edge of the output signal is not detected (S204: NO), the correction processing unit 144 repeats the process of S204. When the falling edge of the output signal is detected (S204: YES), the correction processing unit 144 moves the process to S206.

In S206, the correction processing unit 144 corrects the waveform of the output signal immediately after the falling using the falling correction amount Vfall stored in the memory 145 in S124 of the above-described correction processing. Specifically, the correction processing unit 144 subtracts the amplitude level of the output signal of the ADC 142 by the fall correction amount Vfall and outputs the Rx signal.

In S208, the correction processing unit 144 determines whether or not the correction signal CRen output from the learning determination unit 143 is at a low level. When the correction signal CRen is at the high level (S208: NO), the correction processing unit 144 returns the process to S200 and repeats the correction of the output signal. When the correction signal CRen is at the low level (S208: YES), the correction processing unit 144 moves the process to S210.

In S210, the correction processing unit 144 clears data related to the rising correction amount Vrise and the falling correction amount Vfall stored in the memory 145. After the process of S210, the correction processing unit 144 ends the correction process.

By the way, the flowchart illustrated in FIG. 12 represents processing assuming that the waveform of the output signal is corrected for a code starting from a phase in which the amplitude level of the output signal rises from the low level to the high level. Alternatively, the correction processing unit 144 may be configured to correct the waveform of the output signal with respect to a code that starts from a phase in which the amplitude level of the output signal falls from the High level to the Low level.

In that case, it is conceivable that the correction processing unit 144 branches the correction processing depending on whether a rising edge or a falling edge is detected at a timing corresponding to the start of the code. Specifically, the correction processing unit 144 branches the correction processing into a sequence for performing correction for a code starting from a rising edge and a sequence for performing correction for a code starting from a falling edge. Even when the code starting from the falling edge is the target of correction, the correction processing unit 144 can perform learning by a procedure similar to the flowchart illustrated in FIG. Specifically, the contents of the flowchart of FIG. 12 are read as follows.

The correction processing unit 144 corrects the waveform of the output signal immediately after the fall using the fall correction amount Vfall in S202 on the condition that the fall is detected in S200. Then, the correction processing unit 144 corrects the waveform of the output signal immediately after the rise using the rise correction amount Vrise in S206 on the condition that the rise is detected in S204.

[effect]
The communication system according to the embodiment has the following effects.
The correction processing unit 144 of the receiver 140 can learn the rising correction amount Vrise and the falling correction amount Vfall based on the difference between the output signal of the ADC 142 and the ideal waveform during the arbitration phase in the CAN FD communication frame. it can. In the data phase, the correction processing unit 144 corrects the output signal using the rising correction amount Vrise and the falling correction amount Vfall obtained by learning, and appropriately corrects the waveform disturbance due to ringing, High-speed bus communication can be realized.

A comparative large-scale digital circuit such as DFE is known as a circuit for shaping a signal waveform. Note that DFE is an abbreviation for Decision Feedback Equalizer. In general, since DFE has a plurality of multipliers and has a large circuit scale, there is a drawback that the price of a communication device including a transceiver is increased. Moreover, since DFE is a mechanism for adjusting the correction amount by the LMS algorithm, it takes time to learn the correction amount. For this reason, learning cannot be completed in a short time such as the RSS to BRS section in the CAN FD communication frame. LMS is an abbreviation for LeastLMean Square.

On the other hand, in this embodiment, the correction processing unit 144 of the receiver 140 calculates the correction amount by comparing the ideal waveform stored in the correction processing unit 144 with the waveform of the output signal of the ADC 142. it can. With such a configuration, the communication system of the present embodiment can learn the correction amount in a short time with a small circuit.

[Correspondence between each configuration of the embodiment]
The ADC 142 corresponds to an AD conversion unit. The correction processing unit 144 corresponds to a learning unit and a correction unit. The memory 145 corresponds to a storage unit.

[Modification]
The functions of one component in each of the above embodiments may be shared by a plurality of components, or the functions of a plurality of components may be exhibited by one component. Moreover, you may abbreviate | omit a part of structure of each said embodiment. In addition, at least a part of the configuration of each of the above embodiments may be added to or replaced with the configuration of the other above embodiments. In addition, all the aspects included in the technical idea specified from the wording described in the claims are embodiments of the present disclosure.

The present disclosure can also be realized in various forms such as a system including the transceiver 120 including the receiver 140 described above as a constituent element and a program for causing the computer to function as the correction processing unit 144. In addition, the present disclosure can be realized in various forms such as a non-transition actual recording medium such as a semiconductor memory in which the program is recorded, a signal waveform correction method corresponding to the program, and the like.

Claims

A receiving device (140),
The receiving device is a communication control device (110) that is provided in the communication device that constructs a communication system in which a plurality of communication devices (100) transmit and receive communication signals via a common communication line and performs processing for communication control. ) And the common communication line.
An AD converter (142) configured to convert a communication signal received via the common communication line into a digital signal and output the digital signal;
A received waveform that is a waveform of a digital signal when a predetermined communication signal is received and converted by the AD converter, and a given ideal waveform that represents a waveform of a reference digital signal corresponding to the predetermined communication signal; The learning unit (144) configured to create waveform correction information that is information related to a difference between the received waveform and the ideal waveform, and store the generated waveform correction information in the storage unit (145) When,
A correction signal, which is a signal obtained by correcting the waveform of the digital signal converted by the AD conversion unit after the waveform correction information is stored using the waveform correction information stored in the storage unit, is generated. A correction unit (144) configured to output a correction signal to the communication control device;
A receiving device.
The receiving device according to claim 1,
Communication signals received via the common communication line are provided after an arbitration area having a relatively slow data transfer rate and the arbitration area, and set a data transfer rate faster than the data transfer rate of the arbitration area. A frame with possible data areas,
The learning unit represents a reception waveform that is a waveform of a digital signal when a communication signal in the arbitration region is converted by the AD converter, and an ideal digital signal waveform corresponding to the communication signal in the arbitration region It is configured to generate the waveform correction information by comparing with a given ideal waveform,
The correction unit is configured to generate a correction signal that is a signal obtained by correcting the waveform of the digital signal obtained by converting the communication signal in the data area by the AD conversion unit using the waveform correction information. apparatus.
The receiving device according to claim 2,
The arbitration area of communication signals received via the common communication line is configured to sequentially include an ID area that is information for identifying the communication signal and a control area that is information related to the communication signal. And
The learning unit includes a reception waveform which is a waveform of a digital signal when a communication signal in the control region in the arbitration region is converted by the AD conversion unit, and an ideal digital corresponding to the communication signal in the control region. A receiving device configured to generate the waveform correction information by comparing with a given ideal waveform representing a waveform of a signal.
The receiving apparatus according to any one of claims 1 to 3,
The learning unit compares a signal level between a waveform of a rising phase that is a phase in which a signal level rises from a low level to a high level in the received waveform and the ideal waveform corresponding to the rising phase, and The waveform correction information related to the rising phase is created, and the waveform of the falling phase that is a phase where the signal level falls from a high level to a low level in the received waveform and the ideal waveform corresponding to the falling phase Is configured to create the waveform correction information regarding the falling phase by comparing signal levels between
The correction unit generates a correction signal obtained by correcting the waveform of the rising phase using the waveform correction information regarding the rising phase of the digital signal converted by the AD conversion unit, and the waveform of the falling phase is converted to the rising phase. A receiving apparatus configured to generate a correction signal corrected using waveform correction information related to a falling phase.
The receiving apparatus according to any one of claims 1 to 4,
The learning unit creates a plurality of waveform correction information for waveforms corresponding to a plurality of codes constituting the received waveform, and uses the average value of the plurality of waveform correction information as waveform correction information used for correction by the correction unit A receiving device configured to save in the storage unit.
The receiving apparatus according to any one of claims 1 to 5,
The learning unit is configured to create the waveform correction information for a rising phase, which is a phase in which the signal level of the received waveform rises from a low level to a high level, and after the rising of the signal level is detected When the signal level is low in the aspect corresponding to the sampling point at the time interval of one code of the plurality of codes constituting the received waveform, the waveform correction information regarding the rising phase is A receiving device configured to reject.
The receiving apparatus according to any one of claims 1 to 6,
The learning unit is configured to create the waveform correction information for a falling phase in which the signal level of the received waveform falls from a high level to a low level, and the rising of the signal level is detected Thereafter, when the signal level falls from a high level to a low level during a period from the phase corresponding to the sampling point in the time interval corresponding to one bit of the code of the received waveform to the end of the time interval, the waveform correction related to the rising phase A receiving device configured to reject information.