CN117129844A

CN117129844A - Logic analyzer and integrated chip

Info

Publication number: CN117129844A
Application number: CN202311096749.6A
Authority: CN
Inventors: 刘文皎; 荆晓龙; 张亮; 孙华锦
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2023-08-29
Filing date: 2023-08-29
Publication date: 2023-11-28

Abstract

The invention relates to the technical field of logic analyzers, and discloses a logic analyzer and an integrated chip, wherein the logic analyzer comprises: a tracker and at least one timer counter; the timing counter comprises a timing counting controller, a comparison module, a timing counting module and a statistics module; the timing counting controller is used for configuring triggering conditions to the comparison module; the comparison module is used for outputting an enabling signal to the timing counting module under the condition that the monitoring signal meets the triggering condition; the timing counting module is used for performing timing counting after receiving the enabling signal output by the comparison module and sending a timing counting result to the statistics module; the statistics module is used for carrying out statistics processing on the timing counting result, and generating and outputting corresponding statistics information. The invention can output the information obtained by statistics, does not need to record excessive data in the statistics process, can realize statistics even if a logic analyzer is used for long-time testing, and can finish tasks such as stability analysis, performance analysis and the like.

Description

Logic analyzer and integrated chip

Technical Field

The invention relates to the technical field of logic analyzers, in particular to a logic analyzer and an integrated chip.

Background

The logic analyzer can capture monitoring signals of devices to be tested such as chips and the like under certain triggering conditions to form tracking information, so that the devices to be tested can be tested and analyzed. For example, OLA (OnChip Logic Analyzer, on-chip logic analyzer) can sample and process the monitoring signal using an on-chip high-speed clock to form tracking information by capturing the monitoring signal.

However, as the performance of the device under test is enhanced, it often requires a long time of trace information when testing, and the storage depth of the logic analyzer is limited, so that it is difficult to store a large amount of trace information, and it is difficult to complete testing and analysis by using the logic analyzer, which is not suitable for a long-time testing process. For example, with the development of modern chip technology, chip integration level increases exponentially, and the proportion of the development cost of the chip after silicon verification is larger and larger; in chip stability testing or performance testing, it often takes a long time to track information, and conventional logic analyzers are limited in memory depth to accomplish such tasks.

Disclosure of Invention

In view of the above, the present invention provides a logic analyzer and an integrated chip to solve the problem that the logic analyzer is not suitable for long-time testing process.

In a first aspect, the present invention provides a logic analyzer comprising: a tracker and at least one timer counter; the tracker and the timing counter are both used for inputting monitoring signals, and the tracker is used for sampling the monitoring signals and outputting tracking information;

the timing counter comprises a timing counting controller, a comparison module, a timing counting module and a statistics module;

the timing and counting controller is used for configuring triggering conditions for the comparison module;

the comparison module is used for outputting an enabling signal to the timing counting module under the condition that the monitoring signal meets the triggering condition;

the timing counting module is used for performing timing counting after receiving the enabling signal output by the comparison module and sending a timing counting result to the statistics module;

the statistics module is used for carrying out statistics processing on the timing counting result, and generating and outputting corresponding statistics information.

The logic analyzer provided by the invention comprises at least one timing counter besides the tracker, and the timing counter counts when the triggering condition is met by setting the triggering condition, and counts the timing counting result, so that the statistical information which is convenient for stability analysis or performance analysis can be obtained. The time counter is used for outputting information obtained by statistics, and can realize statistics even if a logic analyzer is used for long-time testing without recording excessive data in the statistics process, so that tasks such as stability analysis and performance analysis can be completed.

In some alternative embodiments, the comparison module includes a timing start comparison unit, a timing end comparison unit, and at least one count comparison unit;

the timing start comparison unit is used for outputting a timing start enabling signal to the timing counting module under the condition that the monitoring signal meets a timing start triggering condition;

the timing end comparison unit is used for outputting a timing end enabling signal to the timing counting module under the condition that the monitoring signal meets the timing end triggering condition;

the counting comparison unit is used for outputting a counting enabling signal to the timing counting module under the condition that the monitoring signal meets a counting triggering condition.

According to the invention, by arranging a plurality of comparison units, different triggering conditions are conveniently set according to the requirements, so that the timing and counting module is controlled to work as required, the timing and counting function is realized, and the timing and counting result which can be used for analysis can be obtained.

In some alternative embodiments, the comparing unit is configured to perform masking processing on the monitoring signal, and compare the masked monitoring signal with a preset reference value to determine whether the monitoring signal meets a corresponding triggering condition. By masking the monitor signal, the data of the unimportant bits in the monitor signal can be masked, the bits which are not concerned can be shielded, and the compared data volume can be reduced when the comparison is carried out with the reference value.

In some alternative embodiments, the comparing unit includes: a mask subunit, a plurality of different condition judgment subunits, a multiplexer, and an output subunit;

the mask subunit is used for performing mask processing on the input monitoring signals and outputting masked monitoring signals;

the first input end of the condition judgment subunit is connected with the output end of the mask subunit, and the second input end is used for inputting the reference value; the output end of the condition judgment subunit is connected with one path of input end of the multiplexer;

the output end of the multiplexer is connected with the output subunit;

the output subunit is used for outputting the output result of the multiplexer when the enable control signal is acquired.

In some alternative embodiments, the comparison module includes a plurality of count comparison units, and the comparison module further includes: a logic operation unit;

the output ends of the counting comparison units are respectively connected with the input ends of the logic operation units;

the logic operation unit is used for carrying out logic operation on the output results of the plurality of counting comparison units, and taking the logic operation result as a counting enabling signal of the timing counting module.

In some alternative embodiments, the logic analyzer further comprises: the cascade selection module is used for selecting a plurality of timing counters;

the timing counting module of the first timing counter is used for inputting an overflow mark to the first input end of the cascade selection module, and the comparison module of the second timing counter is connected with the second input end of the cascade selection module; the first timing counter and the second timing counter are two different timing counters;

the output end of the cascade selection module is connected with the enabling end of the timing counting module of the second timing counter;

the cascade selection module is used for controlling the first input end to be conducted with the output end under the cascade condition and controlling the second input end to be conducted with the output end under the non-cascade condition.

The invention can realize the time counting for a longer time by using the first time counter and the second time counter which are cascaded.

The cascade selection module the timer counter further comprises: a frequency divider; the frequency divider is connected with the enabling end of the timing counting module and is used for generating a timing counting enabling signal of the timing counting module; or the timing counting module is also used for sending an overflow mark to the statistics module; and the statistics module determines a final timing counting result according to the result output by the timing counting module and the number of the received overflow marks.

In some alternative embodiments, the statistical information comprises a running average; the counting module is used for recording the last sliding average value, and obtaining the current sliding average value according to the current timing counting result and the last sliding average value under the condition that the current timing counting result is obtained. The statistical module only needs to record the last sliding average value, so that the required storage space can be greatly reduced, and the storage resource can be saved.

In some alternative embodiments, the statistics module includes: the device comprises a subtracter, a right shift register, an adder and an average value memory;

the first input end of the subtracter is used for inputting the current timing counting result, and the second input end is used for inputting the last sliding average value provided by the average value memory; the subtracter is used for calculating the subtraction result of the current timing counting result minus the last sliding average value;

the output end of the subtracter is connected with the input end of the rightward shift register, and the subtraction result is input into the rightward shift register; the output end of the rightward shift register is connected with the first input end of the adder; the right shift register is used for shifting the SLW bit to the right of the input data;

A second input end of the adder is used for inputting the last sliding average value provided by the average value memory; the adder is used for adding the output result of the rightward shift register and the last sliding average value, and the added result is used as a current sliding average value;

the output end of the adder is connected with the input end of the average value memory, and the addition result is input into the average value memory; the average value memory is used for storing the current sliding average value in a covering mode;

the current running average satisfies:

wherein SV (n) represents the current running average, SV (n-1) represents the last running average, NV (n) represents the current timing count result, 2 ^SLW Representing the window size of the moving average.

The invention sets the sliding window size for calculating the sliding average value to 2 ^SLW Therefore, the subtracter, the rightward shift register and the adder are utilized to simply and conveniently realize the recursive operation on the sliding average value, so that the structure of the logic analyzer can be simplified, and the time required for calculating the sliding average value is shortened.

In some alternative embodiments, the statistics module further comprises: a mode selection unit and a count end triggering unit;

The first input end of the mode selection unit is used for inputting a timing end enabling signal;

the output end of the counting end triggering unit is connected with the second input end of the mode selecting unit; the counting end triggering unit is used for outputting a counting end enabling signal consistent with the counting period;

the output end of the mode selection unit is connected with the enabling end of the average value memory; the average value memory is used for outputting a currently stored sliding average value when the timing end enabling signal or the counting end enabling signal is received;

the mode selection unit is used for controlling the first input end to be conducted with the output end under the condition of timing and controlling the second input end to be conducted with the output end under the condition of counting.

In some alternative embodiments, the statistical information further comprises a maximum value and/or a minimum value;

the statistics module further includes: maximum value unit and/or minimum value unit;

the maximum value unit is used for storing the last maximum value, and taking the larger one of the last maximum value and the current timing and counting result as the current maximum value when the current timing and counting result is input, and storing the larger one;

The minimum value unit is used for storing the last minimum value, and when the current timing and counting result is input, the smaller of the last minimum value and the current timing and counting result is used as the current minimum value and stored.

In some alternative embodiments, the timer counter further comprises: a triggering module;

the triggering module is used for outputting an interrupt signal under the condition that the timing counting result output by the timing counting module meets an interrupt condition.

In some alternative embodiments, the tracker includes a sampler and a packer;

the sampler is used for carrying out mask processing on the monitoring signal input to the sampler, and generating a packaging enabling signal of the packer when the masked monitoring signal changes.

In some alternative embodiments, the packer is configured to: collecting a monitoring signal when the packaging enabling signal is received; generating statistical information comprising a packet header, a system time signal and an acquired monitoring signal; or compressing the system time signal and the collected monitoring signal to generate statistical information containing the compressed system time signal and the collected monitoring signal.

In some alternative embodiments, the tracker further comprises a buffer; the buffer is used for storing the statistical information generated by the packer in a circular buffer mode; or the buffer is used for storing the statistical information generated by the packer in a mode of stopping buffering when overflowing.

In some alternative embodiments, the logic analyzer further comprises: a signal processing module; the signal processing module is used for synchronizing the monitoring signal to the clock domain of the logic analyzer under the condition that the source of the monitoring signal and the logic analyzer are in different clock domains, and inputting the synchronized monitoring signal to the tracker and the timing counter.

In a second aspect, the present invention provides an integrated chip comprising: the logic analyzer, the plurality of functional modules, the monitoring signal selector and the interconnection device described in the first aspect;

the logic analyzer and the functional module are respectively connected to the interconnection device;

each functional module is used for inputting a corresponding monitoring signal to the monitoring signal selector;

the monitoring signal selector is used for selecting at least one functional module to be connected with the logic analyzer.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an application architecture of a logic analyzer;

FIG. 2 is a first schematic diagram of a logic analyzer according to an embodiment of the invention;

FIG. 3 is a schematic diagram of a comparison module in a logic analyzer according to an embodiment of the present invention;

FIG. 4 is a schematic diagram showing another structure of a comparison module in the logic analyzer according to the embodiment of the present invention;

FIG. 5 is a schematic diagram showing a structure of a comparison unit in the logic analyzer according to the embodiment of the present invention;

FIG. 6 is a schematic diagram of a cascaded timing counter in a logic analyzer according to an embodiment of the invention;

FIG. 7 is a second schematic diagram of a logic analyzer according to an embodiment of the invention;

FIG. 8 is a schematic diagram of a structure of a statistics module in a logic analyzer according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of another configuration of a statistics module in a logic analyzer according to an embodiment of the present invention;

FIG. 10 is a third schematic diagram of a logic analyzer according to an embodiment of the invention;

FIG. 11 is a timing diagram of a sampler generating a pack enable signal in a logic analyzer according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of a data format of a packer in a logic analyzer in accordance with an embodiment of the invention;

fig. 13 is a schematic diagram of another data format of a packer in a logic analyzer according to an embodiment of the invention.

Reference numerals illustrate:

10. a tracker; 20. a timer counter; 30. a signal processing module; 11. a tracking controller; 12. a comparator; 13. a sampler; 14. a packer; 15. a buffer; 16. an extremum recorder; 21. a timing count controller; 22. a comparison module; 23. a timing counting module; 24. a statistics module; 25. a triggering module; 26. a cascade selection module; 221. a timing start comparison unit; 222. a timing end comparing unit; 223. a count comparing unit; 224. a logic operation unit; 225. a mask subunit; 226. a condition judgment subunit; 227. a multiplexer; 228. an output subunit; 241. a subtracter; 242. a right shift register; 243. an adder; 244. an average value memory; 245. a mode selection unit; 246. a count end trigger unit; 247. a maximum value unit; 248. a minimum value unit; 1. a logic analyzer; 2. a functional module; 3. a monitor signal selector; 4. interconnection means.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the description of the present invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Unless specifically stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.

One application architecture of the logic analyzer can be seen in fig. 1, as shown in fig. 1, the logic analyzer 1 and the plurality of functional modules 2 are connected to an interconnection means 4, which interconnection means 4 may be a bus, a bridge or the like. The functional module 2 may be, for example, a memory controller, a display controller, a graphics processing unit, an image signal processor, a modem, etc.; the number of functional modules 2 may be based on practical circumstances, and fig. 1 shows that there are n functional modules 2 as an example.

The monitor signal selector 3 may be a multi-stage selector, for example, a 3-stage selector; each functional module 2 is connected with one input of the monitoring signal selector 3 respectively, so as to input a corresponding monitoring signal to the monitoring signal selector 3, and the monitoring signal selector 3 can select at least one functional module 2 to be connected with the logic analyzer 1, so that the monitoring signal of the functional module 2 is sent to the logic analyzer 1 for the logic analyzer 1 to analyze the monitoring signal. Typically, the monitoring signal selector 3 selects one of the functional modules 2 to be connected to the logic analyzer 1.

Embodiments of the present invention provide a logic analyzer that may be used in the architecture shown in fig. 1. In the embodiment, a timing counter is added for the logic analyzer to realize the statistical processing of the monitoring signals, and corresponding statistical information can be output; stability testing or performance testing may be achieved based on the statistical information.

In this embodiment, a logic analyzer is provided, and fig. 2 is a schematic structural diagram of the logic analyzer according to an embodiment of the present invention, as shown in fig. 2, the logic analyzer includes: a tracker 10 and at least one timer counter 20. The tracker 10 and the timer counter 20 are used for inputting a monitoring signal, and the tracker 10 is used for sampling the monitoring signal and outputting tracking information. The bit width of the monitoring signals input to the tracker 10 and the timer counter 20 can be flexibly selected according to the requirements; for example, the bit width of the monitor signal may be 16 bits. The tracker 10 may adopt a structure of a conventional logic analyzer, and obtain corresponding tracking information by sampling and packaging the monitoring signal.

As shown in fig. 2, the timer counter 20 includes a timer count controller 21, a comparison module 22, a timer count module 23, and a statistics module 24. Wherein the timing count controller 21 is configured to configure a trigger condition to the comparison module 22; the comparison module 22 is used for outputting an enabling signal to the timing counting module 23 when the monitoring signal meets the triggering condition; the timing counting module 23 is configured to perform timing counting after receiving the enable signal output by the comparing module 22, and send a timing counting result to the statistics module 24; the statistics module 24 is configured to perform statistics processing on the timing count result, and generate and output corresponding statistics information.

In this embodiment, the logic analyzer may include one or more timer counters 20, and the number of timer counters 20 may be flexibly set according to actual requirements; each timer counter 20 corresponds to a timer counting channel. Typically, a plurality of timing counting channels, i.e. a plurality of timing counters 20, are required. For example, the logic analyzer includes 16 timer counters 20, i.e., the logic analyzer has 16 timer counting channels.

The timer count controller 21 is used to realize overall control of the timer counter 20. Wherein the timer count controller 21 may configure the triggering condition of the comparison module 22. For example, the register of the timer count controller 21 contains a control parameter by which the trigger condition of the comparison module 22 can be configured during the debugging process; the setting of the control parameters can be accomplished by a CPU (central processing unit) or JTAG (Joint Test Action Group, joint test working group) interface.

The comparison module 22 may perform a logic comparison based on the input monitoring signal to determine whether the monitoring signal meets a trigger condition; wherein the trigger condition is a condition that the timer counting module 23 is capable of timing or counting. If the monitoring signal meets the triggering condition, it indicates that the timing counting module 23 can perform timing or counting, and the comparing module 22 can output a corresponding enabling signal to the timing counting module 23. For example, the timer count controller 21 may configure the comparison module 22 with a certain reference value, and the trigger condition is an equality condition; if the monitoring signal is equal to the reference value, the monitoring signal meets the triggering condition, and timing counting can be performed.

The timing counting module 23 is a module for realizing timing counting function, and can perform timing counting after receiving the enabling signal output by the comparing module 22, and generate a corresponding timing counting result; the timing and counting module 23 may be implemented by using an existing timer or counter, which is not limited in this embodiment. The timer count controller 21 can effectively set conditions required for debugging by setting appropriate trigger conditions so that the timer count module 23 can perform timer count as required.

The statistics module 24 has a statistics function, and after the timing and counting module 23 sends the timing and counting result to the statistics module 24, the statistics module 24 can count the timing and counting result, so as to generate statistics information capable of representing the counting condition of the timing and counting. For example, the statistics module 24 may count the maximum or minimum of the counts, where the counted maximum or minimum is a type of statistics.

In this embodiment, based on the statistical information obtained by statistics by the statistics module 24, a stability test or a performance test may be implemented. For example, the timing counting module 23 may record the task execution time, and send the task execution time to the statistics module 24 for statistics, so as to complete corresponding analysis; for example, task execution time is the time required for bus access, based on which performance analysis can be achieved; alternatively, the task execution time is the time to go to sleep, based on which power consumption analysis can be performed. Alternatively, the timing counting module 23 may record the occurrence number of the event, send the occurrence number of the event to the statistics module 24 for statistics, and may complete the corresponding analysis; for example, if a hardware failure is suspected to be due to a bus handshake not being completed, a counter may be used to count requests and receipts, respectively, in a bus operation, and by comparing whether the two are equal, the root cause of the problem in the bus system may be readily determined. It will be appreciated that the task execution time and the number of event occurrences are both a type of timing count result.

Note that, the timer counter 20 in this embodiment may be a timer having only a timer function, a counter having only a counter function, or a timer+counter having both a timer function and a counter function, which is not limited in this embodiment. It will be appreciated that the timer counting controller 21 and the timer counting module 23 may be used only for implementing a timer or counting function, or may be used for implementing a timer+counting function; the timing count result includes a timing result and/or a count result. In addition, if the timer counter 20 has a timer function and a counting function, the timer counting module 23 also has a timer function and a counting function, and the timer counting module 23 may include a separate timer module (e.g., timer) and a counting module (e.g., counter), or may be a composite device for timer and counting multiplexing, and the composite device may operate in a timer mode or a counting mode; it will be appreciated that in the timing mode the composite device corresponds to a timing module and in the counting mode the composite device corresponds to a counting module. For example, the timing and counting module 23 may be controlled by the timing and counting controller 21 to operate in a timing mode or a counting mode.

The logic analyzer provided in this embodiment includes at least one timer counter 20 in addition to the tracker 10, and performs timer counting when the trigger condition is satisfied by setting the trigger condition, and performs statistics on the timer counting result, so that statistical information that is convenient for performing stability analysis or performance analysis can be obtained. The timer counter 20 is used for outputting information obtained by statistics, and can perform statistics even if a logic analyzer is used for a long time without recording excessive data in the statistics process, and can complete tasks such as stability analysis and performance analysis.

In this embodiment, there is provided a logic analyzer including: a tracker 10 and at least one timer counter 20. The working principle of the timer counter 20 can be seen from the related description of the embodiment shown in fig. 2, and will not be described herein.

In this embodiment, the comparing module 22 of the timer counter 20 includes a plurality of comparing units. Specifically, referring to fig. 3, the comparison module 22 includes: a timing start comparing unit 221, a timing end comparing unit 222, and at least one count comparing unit 223. Wherein, the timing counting controller 21 can set corresponding triggering conditions for each comparison unit, and the triggering conditions comprise a timing starting triggering condition, a timing ending triggering condition and a counting triggering condition; for example, the timer count controller 21 sets a timer start trigger condition for the timer start comparing unit 221, a timer end trigger condition for the timer end comparing unit 222, and a corresponding count trigger condition for the count comparing unit 223.

Specifically, the timing start comparing unit 221 is configured to output a timing start enable signal to the timing counting module 23 in a case where the monitoring signal satisfies a timing start trigger condition. The timing end comparing unit 222 is configured to output a timing end enable signal to the timing counting module 23 when the monitoring signal satisfies a timing end trigger condition. The count comparing unit 223 is configured to output a count enable signal to the timer count module 23 in a case where the monitoring signal satisfies a count trigger condition.

When the timing function needs to be implemented, the timing counting module 23 is equivalent to a timing module, and the timing counting module 23 can start timing after receiving the timing start enabling signal output by the timing start comparing unit 221; after receiving the timing end enable signal output by the timing end comparing unit 222, the timing is ended, and the recorded time is a timing result.

When the counting function is required to be implemented, the timing and counting module 23 corresponds to a counting module, and the timing and counting module 23 counts, for example, by adding 1 to the count after receiving the count enable signal output by the count comparing unit 223. After stopping counting, the timer counting module 23 may output the currently recorded count result.

In fig. 3, the timing and counting module 23 is divided into a timing module and a counting module, so as to correspond to different modes.

In this embodiment, the comparison module 22 is provided with a timing start comparison unit 221 for judging whether to start timing, a timing end comparison unit 222 for judging whether to end timing, and a count comparison unit 223 for judging whether to count, so that different trigger conditions can be set conveniently according to requirements, and thus the timing counting module 23 is controlled to work as required, a timing counting function is realized, and a timing counting result which can be used for analysis can be obtained.

In some alternative embodiments, the comparing unit is configured to mask the monitoring signal, and compare the masked monitoring signal with a preset reference value to determine whether the monitoring signal meets a corresponding trigger condition. It is to be understood that the above-described timing start comparing unit 221, timing end comparing unit 222, and count comparing unit 223 are all comparing units, and as shown in fig. 3, all of them determine whether the trigger condition is satisfied according to the above-described processing procedure.

Specifically, as shown in fig. 3, the timing start comparing unit 221 performs mask processing on the input monitoring signal, compares the monitoring signal with the first reference value, and if the comparison result of the two indicates that the timing start triggering condition is met, may output a timing start enabling signal to the timing counting module 23. Wherein the first reference value may be set by the timer count controller 21.

The timing end comparing unit 222 performs mask processing on the input monitoring signal, compares the monitoring signal with the second reference value, and if the comparison result of the two indicates that the timing end triggering condition is met, can output a timing end enabling signal to the timing counting module 23. Wherein the second reference value may be set by the timer count controller 21.

The count comparing unit 223 performs a mask process on the input monitoring signal, compares the monitoring signal with the third reference value, and if the comparison result of the two indicates that the count trigger condition is met, may output a count enable signal to the timing counting module 23. Wherein the third reference value may be set by the timer count controller 21.

In this embodiment, by performing masking processing on the monitor signal, the data of the unimportant bits in the monitor signal can be masked, the bits which are not concerned can be shielded, and the compared data amount can be reduced when the comparison is performed with the reference value later. For example, if the lower four bits of the monitor signal are bits that do not require attention, then the lower four bits may be masked. Wherein it may be determined by the timing count controller 21 which bits need to be masked.

Optionally, referring to fig. 4, the comparing module 22 includes a plurality of count comparing units 223, and the comparing module 22 further includes: a logic operation unit 224. Fig. 4 illustrates that the comparison module 22 includes two count comparison units 223.

The output terminals of the plurality of count comparing units 223 are respectively connected with the input terminals of the logic operation unit 224. The logic operation unit 224 is configured to perform a logic operation on the output results of the plurality of count comparison units 223, and use the logic operation result as a count enable signal of the timer count module 23.

In this embodiment, the timing count controller 21 may configure a corresponding reference value and trigger condition for each count comparing unit 223; as shown in fig. 4, the timer count controller 21 sets a third reference value 1 and a count trigger condition 1 for one of the count comparing units 223, and sets a third reference value 2 and a count trigger condition 2 for the other count comparing unit 223. Each count comparing unit 223 outputs a corresponding result when the monitoring signal meets the count trigger condition; for example, if the monitor signal meets the count trigger condition, the count comparing unit 223 outputs a high level, otherwise outputs a low level.

The output result of each count comparing unit 223 is input to the logic operation unit 224, and the logic operation unit 224 can output an appropriate count enable signal by performing a logic operation thereon. The logic operation unit 224 is specifically capable of performing and, or, exclusive or and other logic operations, which may be specific to the actual situation.

For example, when the monitoring signal satisfies two conditions, the counting can be performed, and the counting trigger condition 1 can be set as one condition, and the counting trigger condition 2 can be set as the other condition; and, the logic operation unit 224 is configured to perform an and operation so that the count enable signal can be output to the timer count module 23 when the monitoring signal satisfies two conditions.

By providing a plurality of count comparing units 223 and logic operation units 224, counting under complex conditions can be realized, and more count demands can be satisfied.

In some alternative embodiments, referring to fig. 5, the comparison unit includes: a mask subunit 225, a plurality of different condition judgment subunits 226, a multiplexer 227, and an output subunit 228.

The masking subunit 225 is configured to perform masking processing on the input monitoring signal, and output a masked monitoring signal. The first input terminal of the condition judging subunit 226 is connected to the output terminal of the mask subunit 225, and the second input terminal is used for inputting a reference value; an output of the condition determining subunit 226 is coupled to one input of a multiplexer 227. The output of multiplexer 227 is connected to output subunit 228; the output subunit 228 is configured to output an output result of the multiplexer 227 when the enable control signal is acquired.

In this embodiment, after the monitoring signal is input to the masking subunit 225, the masking subunit 225 may perform masking processing on the monitoring signal, so as to generate a masked monitoring signal, and input the masked monitoring signal to the first input end of the condition determining subunit 226; wherein the mask configuration may be performed by the timing count controller 21 for the mask subunit 225. For example, the last four bits of the monitor signal currently need to be masked, and if the monitor signal is 10110011, the masked monitor signal may be 10110000.

The first input end of each condition judging subunit 226 is used for inputting the masked monitoring signal, the second input end is used for inputting a preset reference value, and the first input end and the second input end are compared to obtain a corresponding comparison result; it will be appreciated that the reference value may be set by the timing count controller 21 and may also be different for different comparison units. Wherein each condition judgment subunit 226 is capable of performing a condition judgment. As shown in fig. 5, the comparison unit includes six condition judgment sub-units 226, whose executable conditions are respectively: equal to (=), unequal to (|=), greater than (>), greater than or equal to (> =), less than (<), less than or equal to (< =).

Each input of the multiplexer 227 is connected to an output terminal of one condition determining subunit 226, and one of the condition determining subunits 226 can be selected according to actual requirements, and the comparison result output by the selected condition determining subunit 226 is sent to the output subunit 228. Wherein the timing count controller 21 can control which way the multiplexer 227 selects to conduct. The working principle of the Multiplexer (MUX) will not be described in detail in this embodiment.

The output subunit 228 is configured to conditionally output the output result of the multiplexer 227. Specifically, the output subunit 228 may be configured with an enable control signal, and when the output subunit 228 acquires the enable control signal, the output subunit 227 outputs the output result. For example, the enable control signal may be a rising edge and/or a falling edge of the monitor signal; in other words, the output subunit 228 outputs a corresponding comparison result when the monitoring signal reaches the rising edge and/or the falling edge, in which case the comparison result output by the output subunit 228 is a trigger pulse.

It will be appreciated that the comparison result output by the output subunit 228 may be used as a corresponding enable signal, for example, a timing start enable signal, a timing end enable signal, etc.; alternatively, the comparison result may be further processed by the logic operation unit 224 to generate the count enable signal.

In this embodiment, the comparing unit is provided with a plurality of different condition judging subunits 226, and one of the condition judging subunits 226 can be turned on by the multiplexer 227 according to the trigger condition, so as to configure the trigger condition for the comparing module 22; based on the enable control signal, the comparison result is selectively output, and a pulse signal can be output at the rising edge and the falling edge of the monitoring signal, so that the timing counting module 23 is enabled conveniently.

In some alternative embodiments, where the logic analyzer includes multiple timer counters 20, cascading may be performed in order to increase the logic analyzer timer counting capability, as longer timer counts are often required in stability tests. Referring to fig. 6, the logic analyzer further includes: the selection module 26 is cascaded and the number of timer counters 20 is a plurality. Wherein two different timer counters 20 are referred to as a first timer counter and a second timer counter, respectively; for example, two adjacent timer counters 20 may be respectively used as the first timer counter and the second timer counter. It is understood that the first timer counter and the second timer counter each have a comparison module and a timer counting module.

As shown in fig. 6, the timer counting module 23a of the first timer counter is configured to input the overflow flag to the first input terminal of the cascade selection module 26, and the comparing module 22b of the second timer counter is connected to the second input terminal of the cascade selection module 26. The output of the cascade selection module 26 is connected to the enable of the timer counting module 23b of the second timer counter. Wherein the cascade selection module 26 is configured to: in the case of cascading, the first input end is controlled to be conducted with the output end, and in the case of non-cascading, the second input end is controlled to be conducted with the output end.

In this embodiment, in the case of cascading, the first input end of the cascade selection module 26 is connected to the output end thereof, that is, the enabling end of the timing counting module 23b of the second timing counter is connected to the overflow flag of the first timing counter, in other words, when the first timing counter overflows, the count of the timing counting module 23b is incremented by one, so as to realize cascading of two timing counters, and by using the cascaded first timing counter and second timing counter, the timing counting can be realized for a longer time. It will be appreciated that at this point two timing and counting channels will be combined into one channel.

In the non-cascade case, the second input terminal of the cascade selection module 26 is connected to the output terminal thereof, i.e. the comparison module 22b of the second timer counter is connected to the timer counting module 23b, so that the comparison module 22b can output a corresponding enabling signal to the timer counting module 23b, so that the timer counting module 23b can perform timer counting alone. The timing counting module 23a of the first timing counter still counts normally, and the overflow flag does not affect the working process of the second timing counter, i.e. the first timing counter and the second timing counter are still two independent timing counters, and the first timing counter and the second timing counter can still form two timing counting channels.

In this embodiment, the operation mode of the cascade selection module 26 may be determined by the cascade enable signal, i.e. it is determined whether or not cascade is required. For example, a cascade enable signal may be sent by the timer count controller 21 to the cascade selection module 26 to determine whether a cascade is required. The cascade selection module 26 may be a two-way selector.

Alternatively, the long-time timing counting can be realized by frequency division or overflow count. Specifically, the timer counter 20 further includes: a frequency divider; the frequency divider is connected with the enabling end of the timing counting module 23 and is used for generating a timing counting enabling signal of the timing counting module 23; for example, the output end of the comparison module 22 (for example, the count comparison unit 223) is connected to the timing counting module 23 through the frequency divider, so as to divide the output signal of the comparison module, and then the divided signal is used as the enabling signal of the timing counting module 23. Alternatively, the timing counting module 23 is further configured to send an overflow flag to the statistics module 24; the statistics module 24 determines the final timing count result based on the result output by the timing count module 23 and the number of overflow flags received.

The frequency divider is used for timing and counting expansion, so that a timing and counting channel is unchanged, but timing and counting precision is affected. For example, if the frequency divider is divided by two, the original count up by 1 is changed to count up by 2, and the timing count precision is sacrificed, so that increasing the frequency divider is suitable for the scene with low precision requirement.

And the final timing and counting result is determined by combining the overflow mark quantity, so that the timing and counting channels are unchanged, the precision loss is avoided, but the software and hardware interaction is frequent, and the method is suitable for scenes with higher requirements on the number of the timing and counting channels and the timing and counting precision.

In some alternative embodiments, referring to fig. 7, the timer counter 20 may further include: a trigger module 25; the triggering module 25 is configured to output an interrupt signal when the timing count result output by the timing count module 23 meets an interrupt condition.

In this embodiment, the timer counter 20 may also generate an interrupt signal based on which it may be determined that the current timer count has reached a certain stage. For example, the interrupt condition may be a timer overflow, a timer stop, a specified count number being reached, a count period being completed, or the like, and a specific form of the interrupt condition may be set by the timer count controller 21.

For example, the current interrupt condition is a timed overflow, and the trigger module 25 may generate an interrupt signal when the timed overflow is timed by the timed count module 23. It will be appreciated that the interrupt signal may also be sent to the first input of the cascade selection module 26, i.e. the interrupt signal is used as an overflow flag.

Optionally, referring to fig. 7, the logic analyzer further includes: a signal processing module 30; the signal processing module 30 is configured to synchronize the monitoring signal to the clock domain of the logic analyzer when the source of the monitoring signal and the logic analyzer are in different clock domains, and input the synchronized monitoring signal to the tracker 10 and the timer counter 20.

In this embodiment, the monitoring signals input to the logic analyzer may come from various modules, such as the functional module 2 shown in fig. 1, and the functional module 2 and the logic analyzer may be in different clock domains, so that the monitoring signals captured by the logic analyzer are not time-synchronized with the logic analyzer, and therefore time synchronization of the monitoring signals is required. Specifically, the signal processing module 30 may synchronize the monitoring signal to the clock domain of the logic analyzer, and then input the synchronized monitoring signal to the tracker 10 and the timer counter 20 for tracking and counting the synchronized monitoring signal.

The signal processing module 30 may also perform edge detection on the monitoring signal to determine a rising edge and a falling edge of the monitoring signal, and send an edge detection result to the tracker 10 and the timer counter 20 at the later stage, so as to be used as a trigger signal, thereby implementing a required trigger function; for example, the edge detection result may be used as an enable control signal of the aforementioned output subunit 228 to output on the rising edge and the falling edge of the monitor signal.

In this embodiment, there is provided a logic analyzer including: a tracker 10 and at least one timer counter 20. The working principle of the timer counter 20 can be seen in the related description of the embodiment shown in fig. 2 or fig. 3, and the description thereof will be omitted herein. And, the statistical information output by the statistical module 24 includes a running average; the sliding average refers to the average of a plurality of timing count results within a sliding window.

In general, when calculating an average value, a memory (e.g., RAM) is required to store all data to be calculated, and the storage depth is determined by the number of data involved in the average calculation; this requires storing all the timing count results within the sliding window, requiring a large memory space. In this embodiment, a recursive manner is adopted to calculate a sliding average value, so as to reduce the required storage space.

Specifically, the statistics module 24 is configured to record a last running average, and obtain a current running average according to the current counting result and the last running average when the current counting result is obtained.

In this embodiment, the last running average is denoted by SV (n-1), the current count result is denoted by NV (n), and the current running average is denoted by SV (n), and since the size of the sliding window is determinable, that is, the number of data in calculating the running average is determinable, the current running average SV (n) can be obtained based on the current count result NV (n) and the last running average SV (n-1). The current counting result NV (n) is data that can be input to the statistics module 24, so the statistics module 24 only needs to record the previous sliding average value SV (n-1), that is, only needs to record one sliding average value, which can greatly reduce the required storage space and save storage resources.

In some alternative embodiments, referring to fig. 8, the statistics module 24 includes: subtractor 241, right shift register 242, adder 243, and average value memory 244.

The subtractor 241 has a first input for inputting the current count result NV (n) and a second input for inputting the last running average value SV (n-1) provided by the average value memory 244; subtractor 241 is configured to calculate a subtraction result of current timing count result NV (n) minus last sliding average value SV (n-1), where the subtraction result is: NV (n) -SV (n-1).

An output terminal of the subtractor 241 is connected to an input terminal of the rightward shift register 242, and a subtraction result is input to the rightward shift register 242; an output of the right shift register 242 is connected to a first input of the adder 243; wherein the right shift register 242 is used for inputting the numberThe SLW bit is shifted to the right. It can be understood that the rightward shift register 242 shifts the subtraction result of the subtractor 241 rightward, which is equivalent to dividing the subtraction result of the subtractor 241; therefore, the subtraction result NV (n) -SV (n-1) of the subtractor 241 is input to the rightward shift register 242, and the shift result is that the rightward shift register 242 shifts the SLW bit to the rightThe shift result may be input to a first input of adder 243.

A second input of the adder 243 is used for inputting the last running average SV (n-1) provided by the average memory 244; the adder 243 adds the output result of the rightward shift register 242 to the previous moving average SV (n-1), and the added result is the current moving average SV (n).

It can be appreciated that the current running average SV (n) satisfies:

wherein SV (n) represents the current running average, SV (n-1) represents the last running average, NV (n) represents the current timing and counting result, 2 ^SLW The window size representing the running average is also the number of values within the running window that need to be counted for the running average, i.e. the number of timer count results.

The output end of the adder 243 is connected with the input end of the average value memory 244, and the addition result is input to the average value memory 244; the average value memory 244 is used to store the current running average value SV (n) in an overlaid manner.

In the present embodiment, before the current running average SV (n) is calculated, the average value memory 244 stores the last running average SV (n-1), and in the process of calculating the current running average SV (n), the average value memory 244 can provide the last running average SV (n-1) to the subtractor 241 and the adder 243. After the current moving average SV (n) is calculated, i.e., after the adder 243 outputs the current moving average SV (n), the average memory 244 may store the current moving average SV (n). The average value memory 244 is configured to store the current running average value SV (n) in a coverage manner, that is, when the current running average value SV (n) is stored, the last running average value SV (n-1) originally stored is replaced by the current running average value SV (n) in a coverage manner, and only one running average value needs to be stored in the average value memory 244 all the time.

The average value memory 244 may store an initial sliding average value SV (0), and SV (0) may take a value of 0. After the statistics module 24 receives the timing count result NV (1) for the first time, a current running average SV (1) can be calculated based on the subtractor 241, the rightward shift register 242, and the adder 243, and then the current running average SV (1) is stored in the average memory 244. It will be appreciated that the determined current running average SV (n) is smaller in the initial stages of calculating the running average; after the sliding window is filled with the timing count results, i.e. the number of timing count results exceeds 2 ^SLW Thereafter, the determined current running average SV (n) gradually approaches the true running average. In the actual use process, the initial determined sliding average value can be omitted, and statistical analysis is performed based on the remaining sliding average value, so that the accuracy of an analysis result is ensured.

The logic analyzer provided in this embodiment sets the sliding window size for calculating the sliding average value to 2 ^SLW Thus, the subtractor 241, the rightward shift register 242, and the adder 243 can simply and conveniently implement a recursive operation on the moving average, and not only can simplify the structure of the logic analyzer, but also can shorten the time required for calculating the moving average.

Optionally, referring to fig. 9, the statistics module 24 further includes: a mode selection unit 245 and a count end trigger unit 246. Wherein, the first input terminal of the mode selection unit 245 is used for inputting a timing end enabling signal; an output terminal of the count-up triggering unit 246 is connected to a second input terminal of the mode selecting unit 245; the count end triggering unit 246 is configured to output a count end enable signal in accordance with the count period.

An output terminal of the mode selection unit 245 is connected to an enable terminal of the average value memory 244; the average value memory 244 is used for outputting a currently stored sliding average value when receiving a timing end enabling signal or a counting end enabling signal; the mode selecting unit 245 is configured to control the first input terminal to be conducted with the output terminal under the timing condition, and control the second input terminal to be conducted with the output terminal under the counting condition.

In this embodiment, the average value memory 244 stores a running average value and can output the running average value to the outside, so as to avoid the repeated output of the same running average value by the average value memory 244, in this embodiment, an enable signal is set at an enable end of the average value memory 244, and when the enable end receives the enable signal, the average value memory 244 outputs the running average value stored currently; for example, upon receiving the enable signal, the average value memory 244 currently stores a moving average value SV (n), which is then output; if the current stored value is a running average SV (n-1), the running average SV (n-1) is outputted.

Wherein, in the timing mode, the moving average is an average of timing results; in the count mode, the moving average is an average of the count results. In different modes, different enable signals need to be used, and the mode selection is implemented by the mode selection unit 245 in this embodiment. In the timer mode, the first input terminal of the mode selection unit 245 is connected to the output terminal, and in the counter mode, the second input terminal of the mode selection unit 245 is connected to the output terminal.

Specifically, in which mode the mode selection unit 245 operates may be controlled by a mode selection signal. In the timer mode, the first input terminal of the mode selection unit 245 is connected to the output terminal, so that the timer end enable signal can be transmitted to the enable terminal of the average value memory 244; the timing end enable signal may be a signal output by the timing end comparing unit 222. In the counting mode, the corresponding counting result needs to be generated after the counting is finished, and the sliding average value at this time is calculated, and the counting end triggering unit 246 is utilized to output the counting end enabling signal consistent with the counting period, so that the counting end triggering unit 246 can output the counting end enabling signal after the counting is finished.

For example, in a timed mode, statistics module 24 may be used to count the average time a task is performed, such as: the average execution time of each stage in the hardware pipeline is counted to be able to clarify the performance bottleneck. In the count mode, the counting module 24 may count the number of occurrences of an event, such as an anomaly, per unit time, by periodically triggering a running average calculation.

Optionally, the statistical information further comprises a maximum value and/or a minimum value. Also, referring to fig. 9, the statistics module 24 further includes: a maximum value unit 247 and/or a minimum value unit 248.

The maximum value unit 247 is configured to store the last maximum value, and when the current count result is input, store the larger of the last maximum value and the current count result as the current maximum value. The minimum value unit 248 is configured to store the last minimum value, and when the current count result is input, use the smaller of the last minimum value and the current count result as the current minimum value, and store the current minimum value.

In this embodiment, the maximum value of the current timing and counting result can be obtained through statistics by the maximum value unit 247; specifically, the maximum value unit 247 stores the last maximum value max (n-1), and when the maximum value unit 247 receives the current count result NV (n), it determines the magnitude relation between the two, and if max (n-1) > NV (n), it takes max (n-1) as the current maximum value max (n), otherwise, it takes NV (n) as the current maximum value max (n). The maximum unit 247 also stores the maxima in an overlapping manner, i.e. the maximum unit 247 only has to store one maximum.

Similarly, the minimum unit 248 stores the last minimum value min (n-1), and when receiving the current count result NV (n), the minimum unit 248 determines the magnitude relation between the two, if min (n-1) > NV (n), then NV (n) is taken as the current minimum value min (n), otherwise, min (n-1) is taken as the current minimum value min (n). The minimum unit 248 also stores the minimum values in an overlapping manner, i.e. the minimum unit 248 only needs to store one minimum value.

The logic analyzer provided by the embodiment can output the statistical information such as the sliding average value, the maximum value, the minimum value and the like by the statistical module, is convenient to analyze based on various statistical information, and is applicable to various analysis scenes.

In this embodiment, there is provided a logic analyzer including: a tracker 10 and at least one timer counter 20. The working principle of the timer counter 20 can be seen in the related description of the embodiment shown in fig. 2 or fig. 3, and the description thereof will be omitted herein.

The tracker 10 can obtain corresponding tracking information by sampling and packaging the monitoring signals. Specifically, as shown in fig. 10, the tracker 10 includes a tracking controller 11, a comparator 12, a sampler 13, a packer 14, and a buffer 15. The comparator 12 has a structure similar to the aforementioned timing start comparing unit 221, timing end comparing unit 222 to control the sampling start and end of the sampler 13. The tracker 10 may also include an extremum recorder 16 that records the extremum of the monitoring signal.

Wherein the tracking controller 11 can force the triggering of the sampling; for example, the sampling start and stop may be controlled by firmware directly through a configuration register, and use in conjunction with comparator 12 may implement a timing trigger function. Alternatively, the tracking controller 11 may event trigger sampling; for example, sampling start and stop are controlled by setting the condition of the comparator 12.

When packing is required, the sampler 13 generates a packing enable signal so that the packer 14 can pack the monitoring signal. In this embodiment, the sampler 13 performs masking processing on the monitor signal input to the sampler 13, and generates a packetizing enable signal of the packetizer 14 when the masked monitor signal changes. When the sampler 13 generates the packet enable signal, the monitoring signal is first masked, and when it is subsequently determined whether the monitoring signal changes, the processing amount can be reduced.

Wherein it is possible to determine when packaging is required based on various signals. Referring to fig. 11, fig. 11 shows a timing diagram of the generation of the pack enable signal by the sampler 13. As shown in fig. 11, the monitoring signals are masked, so that the originally different monitoring signals can be masked to the same signal, that is, the masked monitoring signals are the same; for example, as shown in fig. 11, masking processing is performed on the monitor signals d0 and d1, the masking processing results are the same, and the masked monitor signals are md0, so as to reduce the processing amount.

The comparator 12 can determine when to start tracking, end tracking, which can output a start tracking signal and an end tracking signal, respectively. As shown in fig. 11, tracking is started at the 3 rd time, the tracking signal is started to be at a high level, and the packaging enable signal is set to be at a high level at this time, so as to form a pulse signal for a period of time; similarly, the tracking is ended at the 15 th timing, the end tracking signal is high, and the packet enable signal is also set high. In addition, at the 7 th time, the masked monitoring signal is changed from md0 to md2, which changes, so that the packet enable signal is also set to a high level; at time 8, there is an external event trigger signal, i.e. the event trigger signal is high, and at this time, no matter whether the monitoring signal changes, sampling is required, i.e. the package enable signal needs to be set to a high level.

When the packer 14 receives the packing enable signal, the monitoring signal can be sampled when the packing enable signal is high, so that the monitoring signal at the moment is collected, and then the statistics information is packed and generated.

Optionally, the packer 14 is specifically configured to: upon receiving the package enable signal, a monitoring signal is collected. Generating statistical information comprising a packet header, a system time signal and an acquired monitoring signal; or compressing the system time signal and the collected monitoring signal to generate statistical information containing the compressed system time signal and the collected monitoring signal.

In this embodiment, the packer 14 may select an appropriate format according to the requirement, and generate a data packet in the format. The trace controller 11 may control the packet format of the packetizer 14 and the state information in the HEADER (HEADER), among other things. As shown in fig. 12, the statistics include a HEADER (HEADER), a system time signal (TIMESTAMP, which may also be referred to as a time stamp), and an acquired monitor signal (mon_data), which are all 32 bits.

Alternatively, the system time signal (TIMESTAMP) and the monitor signal (mon_data) may be compressed to reduce the bit width of both and to eliminate the HEADER (HEADER). As shown in fig. 13, the original 32-bit system time signal (TIMESTAMP) and the monitor signal (mon_data) can both be compressed to 16 bits. The format shown in fig. 13 is adopted for storage, so that more data can be stored, and the efficiency is higher when tracking information is output outwards, and the method is suitable for capturing scenes with rapid data change or large storage depth.

Optionally, the buffer 15 is configured to store the statistical information generated by the packer 14 in a circular buffer manner; alternatively, the buffer 15 is used to store the statistical information generated by the packetizer 14 in such a way that the buffer stops when overflowed.

In this embodiment, the buffer 15 may have two storage modes. In one storage mode, the buffer 15 only records the most recent packed data, and when the memory is full, the old data will be overwritten and stored in a loop. In another storage mode, when the storage mode is not empty, tracking information is output to the outside; and when the memory is full, the writing is abandoned, and after the writing overflows, the user can be informed of the data loss and the number of the lost data through the flag bit in the HEADER. The second mode may specifically be a first-in-first-out (fifo) mode.

The embodiment of the invention also provides an integrated chip, which comprises a logic analyzer 1, a plurality of functional modules 2, a monitoring signal selector 3 and an interconnection device 4, wherein the logic analyzer 1 can be the logic analyzer provided by any embodiment. The logic analyzer 1, the functional module 2, the monitoring signal selector 3 and the interconnection device 4 can be realized by digital circuits and integrated in the same chip. The architecture of the integrated chip can be seen in fig. 1.

As shown in fig. 1, a logic analyzer 1 and a functional module 2 are respectively connected to an interconnection device 4; each functional module 2 is used for inputting a corresponding monitoring signal to the monitoring signal selector 3; the monitoring signal selector 3 is used for selecting at least one functional module 2 to be connected with the logic analyzer 1.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims

1. A logic analyzer, comprising: a tracker (10) and at least one timer counter (20); the tracker (10) and the timing counter (20) are both used for inputting a monitoring signal, and the tracker (10) is used for sampling the monitoring signal and outputting tracking information;

the timing counter (20) comprises a timing counting controller (21), a comparison module (22), a timing counting module (23) and a statistics module (24);

-the timing count controller (21) is configured to configure a trigger condition to the comparison module (22);

the comparison module (22) is used for outputting an enabling signal to the timing counting module (23) under the condition that the monitoring signal meets the triggering condition;

the timing counting module (23) is used for performing timing counting after receiving the enabling signal output by the comparison module (22) and sending a timing counting result to the statistics module (24);

The statistics module (24) is used for carrying out statistics processing on the timing counting result, and generating and outputting corresponding statistics information.

2. The logic analyzer according to claim 1, wherein the comparison module (22) comprises a timing start comparison unit (221), a timing end comparison unit (222) and at least one count comparison unit (223);

the timing start comparing unit (221) is configured to output a timing start enabling signal to the timing counting module (23) when the monitoring signal meets a timing start triggering condition;

the timing end comparison unit (222) is configured to output a timing end enable signal to the timing counting module (23) when the monitoring signal meets a timing end trigger condition;

the count comparing unit (223) is configured to output a count enable signal to the timing counting module (23) when the monitoring signal satisfies a count trigger condition.

3. The logic analyzer according to claim 2, wherein the comparing unit is configured to mask the monitoring signal, and compare the masked monitoring signal with a preset reference value to determine whether the monitoring signal meets a corresponding trigger condition.

4. A logic analyzer according to claim 3, wherein the comparison unit comprises: a mask subunit (225), a plurality of different condition judgment subunits (226), a multiplexer (227), and an output subunit (228);

the masking subunit (225) is configured to perform masking processing on the input monitoring signal, and output a masked monitoring signal;

a first input end of the condition judging subunit (226) is connected with an output end of the mask subunit (225), and a second input end is used for inputting the reference value; the output end of the condition judging subunit (226) is connected with one input end of the multiplexer (227);

-an output of the multiplexer (227) is connected to the output subunit (228);

the output subunit (228) is configured to output an output result of the multiplexer (227) when the enable control signal is acquired.

5. The logic analyzer according to claim 2, wherein the comparison module (22) comprises a plurality of count comparison units (223), and the comparison module (22) further comprises: a logic operation unit (224);

the output ends of the counting comparison units (223) are respectively connected with the input ends of the logic operation units (224);

The logic operation unit (224) is configured to perform a logic operation on output results of the plurality of count comparison units (223), and use the logic operation result as a count enable signal of the timing count module (23).

6. The logic analyzer of claim 1, further comprising: -a cascade selection module (26), and the number of timer counters (20) is a plurality;

the timing counting module of the first timing counter is used for inputting an overflow mark to the first input end of the cascade selection module (26), and the comparison module of the second timing counter is connected with the second input end of the cascade selection module (26); -the first and second timer counters are two different timer counters (20);

the output end of the cascade selection module (26) is connected with the enabling end of the timing counting module of the second timing counter;

the cascade selection module (26) is used for controlling the first input end to be conducted with the output end under the cascade condition and controlling the second input end to be conducted with the output end under the non-cascade condition.

7. The logic analyzer of claim 1, wherein the timing counter (20) further comprises: a frequency divider; the frequency divider is connected with the enabling end of the timing counting module (23), and is used for generating a timing counting enabling signal of the timing counting module (23);

Or, the timing counting module (23) is further used for sending an overflow mark to the statistics module (24); the counting module (24) determines a final timing counting result according to the result output by the timing counting module (23) and the number of the received overflow marks.

8. The logic analyzer of claim 1, wherein the statistical information comprises a running average;

the statistics module (24) is configured to record a last running average, and obtain a current running average according to the current timing count result and the last running average when the current timing count result is obtained.

9. The logic analyzer of claim 8, wherein the statistics module (24) comprises: a subtractor (241), a rightward shift register (242), an adder (243), and an average value memory (244);

-a first input of said subtractor (241) is adapted to input a current timing count result, -a second input is adapted to input a last running average value provided by said average value memory (244); -said subtractor (241) is configured to calculate a subtraction result of said current timing count result minus said last running average;

The output end of the subtracter (241) is connected with the input end of the rightward shift register (242), and the subtraction result is input into the rightward shift register (242); an output of the rightward shift register (242) is connected to a first input of the adder (243); the right shift register (242) is used for shifting the SLW bit to the right of the input data;

-a second input of said adder (243) is for inputting said last running average provided by said average memory (244); the adder (243) is configured to add the output result of the rightward shift register (242) to the previous running average, and to use the added result as a current running average;

the output end of the adder (243) is connected with the input end of the average value memory (244), and the addition result is input into the average value memory (244); -the average value memory (244) is adapted to store the current running average value in an overlaid manner;

the current running average satisfies:

wherein SV (n) represents the current running averageSV (n-1) represents the last running average, NV (n) represents the current timing count result, 2 ^SLW Representing the window size of the moving average.

10. The logic analyzer of claim 9, wherein the statistics module (24) further comprises: a mode selection unit (245) and a count end trigger unit (246);

a first input terminal of the mode selection unit (245) is used for inputting a timing end enabling signal;

the output end of the counting end triggering unit (246) is connected with the second input end of the mode selecting unit (245); the counting end triggering unit (246) is used for outputting a counting end enabling signal consistent with a counting period;

an output end of the mode selection unit (245) is connected with an enabling end of the average value memory (244); the average value memory (244) is used for outputting a currently stored sliding average value when the timing end enabling signal or the counting end enabling signal is received;

the mode selection unit (245) is used for controlling the first input end to be conducted with the output end under the condition of timing and controlling the second input end to be conducted with the output end under the condition of counting.

11. The logic analyzer of claim 8, wherein the statistical information further comprises a maximum value and/or a minimum value;

the statistics module (24) further comprises: a maximum value unit (247) and/or a minimum value unit (248);

The maximum value unit (247) is used for storing the last maximum value, and taking the larger of the last maximum value and the current timing counting result as the current maximum value when the current timing counting result is input, and storing the larger of the last maximum value and the current timing counting result;

the minimum value unit (248) is configured to store a last minimum value, and when a current time count result is input, use a smaller one of the last minimum value and the current time count result as a current minimum value, and store the current minimum value.

12. The logic analyzer of claim 1, wherein the timing counter (20) further comprises: a trigger module (25);

the triggering module (25) is used for outputting an interrupt signal when the timing counting result output by the timing counting module (23) meets an interrupt condition.

13. The logic analyzer according to claim 1, characterized in that the tracker (10) comprises a sampler (13) and a packer (14);

the sampler (13) is used for masking the monitoring signal input to the sampler (13) and generating a packaging enabling signal of the packaging device (14) when the masked monitoring signal changes.

14. The logic analyzer according to claim 13, wherein the packer (14) is configured to:

collecting a monitoring signal when the packaging enabling signal is received;

generating statistical information comprising a packet header, a system time signal and an acquired monitoring signal; or compressing the system time signal and the collected monitoring signal to generate statistical information containing the compressed system time signal and the collected monitoring signal.

15. The logic analyzer according to claim 13, wherein the tracker (10) further comprises a buffer (15);

the buffer (15) is used for storing the statistical information generated by the packer (14) in a circular buffer mode; alternatively, the buffer (15) is used for storing the statistical information generated by the packer (14) in a mode of stopping buffering when overflowing.

16. The logic analyzer of claim 1, further comprising: a signal processing module (30);

the signal processing module (30) is used for synchronizing the monitoring signal to the clock domain of the logic analyzer under the condition that the source of the monitoring signal and the logic analyzer are in different clock domains, and inputting the synchronized monitoring signal to the tracker (10) and the timing counter (20).

17. An integrated chip, comprising: the logic analyzer (1) of any of claims 1 to 16, a plurality of functional modules (2), a monitoring signal selector (3) and an interconnection means (4);

the logic analyzer (1) and the functional module (2) are respectively connected to the interconnection device (4);

each of the functional modules (2) is used for inputting a corresponding monitoring signal to the monitoring signal selector (3);

the monitoring signal selector (3) is used for selecting at least one functional module (2) to be connected with the logic analyzer (1).