CN112506841A

CN112506841A - Serial data recovery method, interface and electronic equipment

Info

Publication number: CN112506841A
Application number: CN202011460363.5A
Authority: CN
Inventors: 赵建中; 王周; 周玉梅
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2020-12-11
Filing date: 2020-12-11
Publication date: 2021-03-16

Abstract

The invention discloses a serial data recovery method, an interface and electronic equipment, which solve the problem that error data is collected in a data recovery process when data is collected by using a high-speed multiphase clock. The serial data recovery method comprises the following steps: performing multi-phase sampling on the serial data in a clock period to obtain multi-phase sampling data; the multiphase sampling data comprises M sampling data, wherein M is an integer greater than or equal to 2; synchronizing the 0 th sampling data to the (M-1)/2 th sampling data to obtain first synchronization data; synchronizing the M/2 th sampling data to the M-1 th sampling data to obtain second synchronous data; synchronizing the first synchronous data and the second synchronous data to obtain M sampling data of one clock period; determining edge information in a clock period according to the M sampling data; determining the access phase of the clock period according to the edge information; and obtaining the recovered serial data according to the access phase.

Description

Serial data recovery method, interface and electronic equipment

Technical Field

The present invention relates to the field of high-speed serial communication technologies, and in particular, to a serial data recovery method, an interface, and an electronic device.

Background

The rapid development of communication technology further increases the demand for high-speed high-performance transceiver chips, and the traditional parallel data transmission mode cannot meet the demand, so that the high-speed serial data transceiver with extremely high transmission speed has wide application in a high-speed bidirectional data transmission system. Wherein the high-speed bidirectional data transmission system comprises: gigabit ethernet, fiber optic communication networks, network high-speed routing, wireless base stations, and the like.

In a high-speed bidirectional data transmission system, data is converted from serial to parallel and high-speed serial data is transmitted using a channel. Since there is a certain deviation in the clock data at the receiving end of the transceiver, the received and amplified data is not synchronous and contains noise. In order to ensure the synchronization of the subsequent processing of data, a commonly used method for recovering a data clock is as follows: the different phase clocks are selected from the phase clocks for switching, and glitches may occur when the clocks are switched. For example: when the adjacent phase clocks are switched, when the 1 phase clock is switched to the 2 phase clock, the rising edge of the 2 phase clock at the switching moment lags, so that the output clock at the moment is subjected to transient low jump and high rise to generate burrs. It is also possible that a phase step may be generated due to various factors, resulting in a decrease in jitter performance, such that erroneous data may be collected in high speed data recovery.

Disclosure of Invention

The invention aims to provide a serial data recovery method, an interface and electronic equipment, which are used for solving the problem that when data are collected by using a high-speed multi-phase clock, error data are collected due to phase step caused by burrs generated by phase cut or other reasons in the data recovery process.

In a first aspect, the present invention provides a serial data recovery method, including:

performing multi-phase sampling on the serial data in a clock period to obtain multi-phase sampling data; the multiphase sampling data comprises M sampling data, wherein M is an integer greater than or equal to 2;

synchronizing the 0 th sampling data to the (M-1)/2 th sampling data to obtain first synchronization data; synchronizing the M/2 th sampling data to the M-1 th sampling data to obtain second synchronous data;

synchronizing the first synchronous data and the second synchronous data to obtain M sampling data of one clock period;

determining edge information in a clock period according to the M sampling data;

determining the access phase of the clock period according to the edge information; and obtaining the recovered serial data according to the access phase.

Compared with the prior art, the serial data recovery method provided by the invention firstly carries out M-phase sampling on serial data to generate M sampling data, when the adjacent phase delay is too small when the high-speed multi-phase clock acquires data and is smaller than the delay of the fastest trigger unit in a standard unit library, data synchronization can not be carried out, so that the M sampling data are not synchronized once when the sampling clock period is finished, but the M sampling data are synchronized through twice splitting to obtain first synchronization data and second synchronization data; obtaining M sampling data according to the first synchronous data and the second synchronous data; and obtaining edge information in one clock period according to the M sampling data. The phase position of the edge is judged through the edge information in a clock cycle, namely the phase position with inconsistent numerical values collected between the front phase and the rear phase, so that the access phase in the clock cycle is determined, and correct serial data is output, thus eliminating the influence of burrs when the phases are switched.

In a second aspect, the present invention further provides a serial data recovery interface, including: the device comprises a data sampler, a buffer synchronizer, an edge detector, a decision device and a data selector; wherein the content of the first and second substances,

the data sampler is used for performing multi-phase sampling on the serial data in one clock period to obtain multi-phase sampling data; the multiphase sampling data comprises M sampling data, wherein M is an integer greater than or equal to 2;

the buffer synchronizer is used for synchronizing the 0 th sampling data to the (M-1)/2 th sampling data to obtain first synchronization data; synchronizing the M/2 th sampling data to the M-1 th sampling data to obtain second synchronous data; synchronizing the first synchronous data and the second synchronous data to obtain M sampling data of one clock period;

the edge detector is used for determining edge information in one clock period according to the M sampling data;

the decision device is used for determining the access phase of the clock period according to the edge information;

and the data selector is used for acquiring the recovered serial data according to the access phase.

Compared with the prior art, the beneficial effects of the serial data recovery interface provided by the embodiment of the invention are the same as those provided by the serial data recovery method, and are not repeated herein.

In a third aspect, the present invention further provides an electronic device, which includes the serial data recovery interface.

Compared with the prior art, the electronic device provided by the embodiment of the invention has the same beneficial effects as those provided by the serial data recovery interface, and the details are not repeated herein.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 illustrates a first flowchart of a serial data recovery method according to an embodiment of the present invention;

fig. 2 illustrates a second flowchart of a serial data recovery method according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a serial data recovery interface according to an embodiment of the present invention;

fig. 4 illustrates an effect diagram of different numbers of edges included in one clock cycle according to an embodiment of the present invention;

fig. 5 illustrates a schematic structural diagram of an electronic device provided in an embodiment of the present invention;

fig. 6 illustrates a schematic structural diagram of a chip according to an embodiment of the present invention.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

The rapid development of communication technology further increases the demand for high-speed and high-performance transceiver chips, and the traditional parallel data transmission mode cannot meet the demand. High-speed serial data transceivers find wide application in high-speed bi-directional data transmission systems, such as gigabit ethernet, fiber optic communication networks, network high-speed routing, and wireless base stations.

In a high-speed serial communication system, data is converted from serial to parallel, and high-speed serial data is transmitted through a channel. Since there is a certain deviation in the clock data at the receiving end of the transceiver, the received and amplified data is not synchronous and contains noise. In order to ensure the synchronization of the subsequent processing of the data, timing information such as clock must be extracted from the data, and the data needs to be retimed to remove jitter, i.e., noise, accumulated during the data transmission process and recover serial data synchronized with the local clock domain, which is clock data recovery.

In view of the above problems, an embodiment of the present invention provides a serial data recovery method to solve the problem that when data is collected by using a high-speed multi-phase clock, erroneous data is collected due to phase step caused by a glitch generated by phase cut or other reasons in the data recovery process.

Fig. 1 is a first flowchart illustrating a serial data recovery method according to an embodiment of the present invention. As shown in fig. 1, a serial data recovery method according to an embodiment of the present invention includes the following steps:

step 101: performing multi-phase sampling on the serial data in a clock period to obtain multi-phase sampling data;

the multiphase sample data includes M sample data, where M is an integer greater than or equal to 2.

The received serial data is sampled in M phases in one clock cycle to obtain M pieces of sampled data. Such as: and 8-phase sampling is carried out on the serial data 1 to respectively obtain the 0 th sampling data, the 1 st sampling data, the 2 nd sampling data, the 3 rd sampling data, the 4 th sampling data, the 5 th sampling data, the 6 th sampling data and the 7 th sampling data.

Step 102: synchronizing the 0 th sampling data to the (M-1)/2 th sampling data to obtain first synchronization data; synchronizing the M/2 th sampling data to the M-1 th sampling data to obtain second synchronous data;

after M sampling data are obtained, synchronizing the 0 th sampling data to the (M-1)/2 th sampling data to obtain first synchronization data; and synchronizing the M/2 th sampling data to the M-1 th sampling data to obtain second synchronous data.

In practical application, serial data is sampled in M phases in a first clock cycle to obtain M sampled data. In a second clock period, synchronizing the 0 th sampling data to the (M-1)/2 th sampling data by using a0 phase clock to obtain first synchronization data, and storing the first synchronization data into a first register, wherein the first register comprises M/2 sampling data; and synchronizing the M/2-th sampling data to the M-1-th sampling data by utilizing an M/2 phase clock to obtain second synchronous data, and storing the second synchronous data into a second register, wherein the second register comprises M/2 sampling data.

Such as: serial data is sampled 8-phase in a first clock cycle, obtaining 8 sampled data. In a second clock period, synchronizing the 0 th sampling data to the 3 rd sampling data by using a0 phase clock, and storing the data to a first register; and synchronizing the 4 th sampling data to the 7 th sampling data by using the 4-phase clock, and storing the data to the second register.

It should be noted that, when the value of M is an odd number, the first register stores one more bit of sample data than the second register.

Such as: serial data is subjected to 7-phase sampling in a first clock cycle, and 7 sampling data are obtained. In a second clock period, synchronizing the 0 th sampling data to the 3 rd sampling data by using a0 phase clock, and storing the data to a first register; and synchronizing the 4 th sampling data to the 6 th sampling data by using the 4-phase clock, and storing the data to the second register.

Step 103: synchronizing the first synchronous data and the second synchronous data to obtain M sampling data of one clock period;

after first synchronous data and second synchronous data are obtained, the first synchronous data and the second synchronous data are synchronized to obtain M sampling data of one clock period.

In practical application, in a third clock cycle, the first synchronous data and the second synchronous data are synchronously stored in a third register according to a phase sequence by using a 0-phase clock, wherein the first synchronous data stored in the first memory and the second synchronous data stored in the second memory are synchronously stored in the third register, and the third register comprises M sampling data; with the high phase leading.

Such as: in a third clock cycle, first synchronization data stored in the first memory is clocked by the 0-phase clock: the 0 th sample data to the 3 rd sample data, the second synchronization data stored in the second memory: synchronizing the 4 th sampling data to the 7 th sampling data to obtain third synchronous data stored in a third memory: 0 th sample data to 7 th sample data; wherein the 7 th sample data precedes.

Step 104: determining edge information in a clock period according to the M sampling data;

after obtaining M sampling data of one clock cycle, determining edge information within one clock cycle according to the M sampling data; wherein, the edge information may include: the number of the edges and the phase corresponding to the edge position.

As an implementation manner, determining edge information in one clock cycle according to M sampling data includes: obtaining M pieces of exclusive or data according to M pieces of sampling data of one clock period and first sampling data of an adjacent clock period; and determining edge information in one clock period according to the M pieces of exclusive-or data.

When determining edge information in one clock cycle, performing exclusive or operation on adjacent sampling data of M sampling data in one clock cycle; alternatively, the xor operation may be performed on the last sample data in one clock cycle and the first sample data in the adjacent clock cycle.

The xor data obtained by the xor operation represents whether an edge exists in one clock cycle, and it can be understood that after the same data in the serial data is acquired for M times, the xor data is obtained by performing xor operation on the data acquired for multiple times, and the xor data is 1 representing that the acquired values are inconsistent before and after the phase, and the edge exists; the XOR data is a value which is collected between the front phase and the rear phase of the 0 representation and is consistent, and no edge exists.

As an implementation manner, obtaining M pieces of xor data according to M pieces of sample data of one clock cycle and a first piece of sample data of an adjacent clock cycle includes: performing exclusive OR operation on adjacent sampling data of the M sampling data in one clock period to obtain M-1 exclusive OR data; and carrying out exclusive OR operation on the last sampling data in one clock period and the first sampling data in the adjacent clock period to obtain Mth exclusive OR data.

For the 0 th to M-1 th sampling data of one clock cycle, when performing the xor operation, the 0 th sampling data and the 1 st sampling data may be subjected to the xor operation, and the obtained xor data is stored in the 0 th phase; carrying out XOR operation on the 1 st sampling data and the 2 nd sampling data, and storing the obtained XOR data to the 1 st phase; and in the same way, performing exclusive OR operation on the M-1 th sampling data and the M-1 th sampling data, and storing the obtained exclusive OR data to the M-1 th phase, so as to obtain M-1 pieces of exclusive OR data.

For the mth sampling data of one clock cycle, when the xor operation is performed, the xor operation is performed on the mth sampling data and the 0 th sampling data of the next clock cycle, and the obtained xor data is stored in the mth phase of one clock cycle, so that the mth xor data is obtained. Such as: the mth sampling data of the clock cycle 1 and the 0 th sampling data of the clock cycle 2 are subjected to exclusive or operation, and the obtained exclusive or data is stored in the mth phase of the clock cycle 1.

As an implementation manner, determining edge information in one clock cycle according to the M pieces of xor data includes: adding the M pieces of exclusive or data to obtain an addition result; and determining the number of edges contained in the edge information in one clock period according to the addition result.

After M pieces of exclusive-or data are obtained, adding the M pieces of exclusive-or data to obtain an addition result; and determining the number of edges contained in the edge information in one clock period according to the addition result. It can be understood that, whether the values collected before and after the xor data representation and the phases are consistent or not and whether an edge exists or not, and the number of times of the edge occurrence can be judged by adding the M-bit xor data.

Such as: the 8 xor data are: 0. 1, 0 and 0, and adding the exclusive or data to determine the number of edges to be 3; for another example: the 8 xor data are: 0. 1, 0 and 0, and adding the exclusive or data to determine the number of edges as 1; for another example: the 8 xor data are: 0. 0, and the number of edges is determined to be 0 by adding the exclusive or data.

As an implementation manner, determining the number of edges included in the edge information in one clock cycle according to the addition result includes: determining the number of edges contained in one clock cycle to be 0 under the condition that the addition result is equal to 0; determining the number of edges contained in one clock cycle to be 1 under the condition that the addition result is equal to 1; in the case where the addition result is greater than or equal to 2, it is determined that the number of edges included in one clock cycle is greater than or equal to 2.

Here, the M pieces of exclusive or data are subjected to addition operation to obtain an addition result; the addition result is equal to 0, and the number of edges contained in one clock period is represented as 0; the addition result is equal to 1, and the number of edges contained in one clock period is represented as 1; the addition result is greater than or equal to 2, and the number of edges contained in one clock period is greater than or equal to 2.

Step 105: determining the access phase of the clock period according to the edge information; and obtaining the recovered serial data according to the access phase.

After the edge information in one clock cycle is obtained, determining the access phase of one clock cycle according to different conditions of the number of edges included in the edge information; and according to the access phase of one clock cycle, taking the data corresponding to the access phase as the recovered serial data.

As an implementation, determining the fetch phase for one clock cycle based on the edge information includes: and determining that the fetch phase of one clock cycle is consistent with the fetch phase of the previous clock cycle under the condition that the number of edges contained in the edge information is equal to 0.

Under the condition that the number of the edges is equal to 0, the access phase is consistent with the access phase of the previous clock cycle and is kept unchanged; after the access phase is determined, the access number can be determined according to the access phase.

Such as: the fetch phase of the previous clock cycle is 6, and in the case where the number of edges of one clock cycle is equal to 0, the fetch phase of one clock cycle is also 6, and the fetch number is 1.

As an implementation, determining the fetch phase for one clock cycle based on the edge information includes: under the condition that the number of edges contained in the edge information is equal to 1, judging whether the phase corresponding to the edge position in one clock period is in a [ K, M-K ] interval or not; k represents the maximum occupied phase proportion value of the data burr; if yes, updating the access phase of one clock period to the phase of the edge position and increasing M/2 phases; if not, the fetch phase of one clock cycle is consistent with the fetch phase of the previous clock cycle.

Under the condition that the number of edges is equal to 1, judging whether the phase corresponding to the edge position in one clock cycle is in a [ K, M-K ] interval or not, if so, updating the access phase, wherein the updated access phase is the phase of the edge position and is shifted backwards by M/2 phases, and if not, the updated access phase is consistent with the access phase in the previous clock cycle; after the access phase is determined, the access number can be determined according to the access phase.

Such as: m is 16, K is 4, and the fetch phase of the previous clock cycle is 5; if the phase corresponding to the edge position in one clock cycle is in the [4, 12] interval, the updated access phase is 13, and the access number is 1; if the phase corresponding to the edge position in one clock cycle is not in the [4, 12] interval, the access phase is kept not to be 5, and the access number is 1.

As an implementation, determining the fetch phase for one clock cycle based on the edge information includes: under the condition that the number of edges contained in the edge information is greater than or equal to 2, judging whether the edge appears in K phases before or after the corresponding position of the fetch phase of the previous clock cycle in one clock cycle; if yes, updating the access phase of one clock cycle to the access phase of the previous clock cycle, and increasing or decreasing K +1 phases; if not, the fetch phase of one clock cycle is consistent with the fetch phase of the previous clock cycle.

Under the condition that the number of the edges is more than or equal to 2, judging whether the edges appear in the first K phases of the corresponding positions of the access phases in the previous clock cycle; if yes, the access phase of one clock cycle is the access phase of the previous clock cycle, and then K +1 phases are shifted backwards, and if not, the access phase of the previous clock cycle is consistent with the access phase of the previous clock cycle; or judging whether the fetch phase in the previous clock cycle has an edge in the last K phases of the corresponding positions in one clock cycle; if yes, the access phase of one clock cycle is the access phase of the previous clock cycle, and the access phase is shifted forward by K +1 phases, and if not, the access phase is consistent with the access phase of the previous clock cycle. After the access phase is determined, the access number can be determined according to the access phase.

Such as: m is 16, K is 4, and the fetch phase of the previous clock cycle is 5; if the fetch phase 5 of the previous clock cycle has an edge in the first 4 phases of the corresponding position of the current clock cycle, the updated fetch phase is 10, and the fetch number is 1; if the fetch phase 5 of the previous clock cycle does not have an edge in the first 4 phases of the corresponding position of the current clock cycle, the fetch phase remains unchanged to 5, and the fetch number is 1.

For another example: m is 16, K is 4, and the fetch phase of the previous clock cycle is 5; if the fetch phase 5 of the previous clock cycle has an edge in the last 4 phases of the corresponding position of the current clock cycle, the updated fetch phase is 0, and the fetch number is 1; if the fetch phase 5 of the previous clock cycle does not have an edge in the last 4 phases of the corresponding position of the current clock cycle, the fetch phase is kept unchanged to 5, and the fetch number is 1.

Fig. 2 illustrates a second flowchart of a serial data recovery method according to an embodiment of the present invention. As shown in fig. 2, the serial data recovery method provided by the embodiment of the present invention includes the following steps:

step 201: carrying out data sampling on serial data;

step 202: buffering and synchronizing the obtained sampling data;

step 203: carrying out edge detection on the sampled data which is synchronously buffered;

step 204: judging whether the number of edges in one period is 1 or not;

if yes, go to step 205; if not, go to step 208.

Step 205: determining whether the edge position is within the [ K, M-K ] interval;

if yes, go to step 206; if not, go to step 207.

Step 206: updating the access phase; the new fetch phase is that the edge position moves backwards by M/2;

step 207: keeping the original digit taking phase unchanged;

step 208: judging whether the number of edges in one period is 0 or not;

if yes, go to step 209; if not, go to step 210.

Step 209: keeping the original digit taking phase unchanged;

step 210: judging whether the fetch phase of the previous clock cycle corresponds to the edge of the previous or next K phases of the current clock cycle;

if yes, go to step 211; if not, go to step 212.

Step 211: the current fetch phase is the fetch phase of the previous clock cycle and is shifted by K +1 bit in the opposite direction;

step 212: keeping the original digit taking phase unchanged;

step 213: determining the number of access numbers according to the access phases;

step 214: and selecting data to recover according to the access phase and the access number.

The serial data recovery method provided by the invention firstly carries out M-phase sampling on serial data to generate M sampling data, when the adjacent phase delay is too small when the high-speed multiphase clock acquires data and is smaller than the delay of a fastest trigger unit in a standard unit library, data synchronization can not be carried out, so that the M sampling data are not synchronized once when the sampling clock period is finished, but the M sampling data are synchronized through twice splitting to obtain first synchronization data and second synchronization data; obtaining M sampling data according to the first synchronous data and the second synchronous data; according to the M sampling data, the edge information in one clock cycle is obtained, and it can be understood that after the same data in the serial data is collected for M times, the data collected for multiple times are subjected to exclusive OR, the result of exclusive OR is that the collected values before and after the 1 representation phase are inconsistent, and problems exist.

An embodiment of the present invention further provides a serial data recovery interface, as shown in fig. 3, the serial data recovery interface includes: a data sampler 31, a buffer synchronizer 32, an edge detector 33, a determiner 34, and a data selector 35; here, an initial zero-phase clock is selected as an initial clock of each block among the M-phase clocks.

A data sampler 31 for performing multi-phase sampling on the serial data in one clock cycle to obtain multi-phase sampling data; the multiphase sampling data comprises M sampling data, wherein M is an integer greater than or equal to 2;

in practical applications, the data sampler 31 utilizes a multiphase clock with M phases, such as: clk 0., clkm-1, clkm, M-phase samples the serial DATA _ IN one clock cycle, outputs M sampled DATA 0., DATAM-1, DATAM, and outputs the initial phase clock clk0 and the M/2 phase clock clkm/2 to the buffer synchronizer 32.

A buffer synchronizer 32 for synchronizing the 0 th sample data to the (M-1)/2 nd sample data to obtain first synchronization data; synchronizing the M/2 th sampling data to the M-1 th sampling data to obtain second synchronous data; synchronizing the first synchronous data and the second synchronous data to obtain M sampling data of one clock period;

in practical application, the buffer synchronizer 32, in the second clock cycle, synchronizes the 0 th sampling data to the (M-1)/2 th sampling data by using the 0 phase clock clk0, and outputs the data to the first register of M/2 bits; synchronizing the M/2 sampling data to the Mth sampling data by using an M/2 phase clock clkm/2, and outputting to a second register of M/2 bits; if M is odd phase, the first register value is more allocated with one bit than the second register value; and in a third clock period, synchronizing the sampling DATA stored in the two registers into a third register with M bits according to the phase sequence by using a 0-phase clock to obtain M sampling DATA DATA [ M-1, 0], wherein the high bits are in front.

The operation can avoid the problem that data cannot be acquired due to small delay between adjacent phases, for example, a 0-phase clock cannot acquire data generated by an M-phase clock in the previous clock period; when the trigger with the highest response speed in the standard cell library cannot meet the time interval between the 0 phase and the M phase, the buffer synchronizer can leave a margin of a half period so as to solve the problem that data cannot be acquired due to small delay between adjacent phases.

An edge detector 33, configured to determine edge information in one clock cycle according to the M sampling data;

in practical application, the edge detector 33 buffers M pieces of acquired data obtained by the buffer synchronizer 32 for one clock cycle, and performs an exclusive or operation on two adjacent bits of the M pieces of acquired data in the one clock cycle to obtain M-1 pieces of exclusive or data; and performing exclusive-OR operation on the last DATA in the M pieces of collected DATA in one clock period and the first collected DATA in the next clock period to obtain the Mth exclusive-OR DATA, so as to obtain the M pieces of exclusive-OR DATA DATA _ XOR [ M-1, 0], with the high order preceding.

A decision device 34, configured to determine an access phase of the clock cycle according to the edge information;

in practical application, the M pieces of xor data obtained by the xor operation are all added, and the occurrence of an edge in one clock cycle is determined according to the xor result. When the exclusive or result is 0, no edge appears in one clock period; when the exclusive or result is 1, an edge appears in one clock period; when the exclusive or result is equal to or greater than 2, two or more edges occur within one clock cycle.

When an edge appears in a clock period, judging whether the edge position is in a [ K, M-K ] interval or not, if so, updating the access phase to be a phase corresponding to the edge position and then shifting back by M/2 phase; otherwise, keeping the fetch phase of the previous clock cycle unchanged; and K is the maximum occupied phase proportion of the data glitch required by the protocol.

In the case of zero edges in one clock cycle, the fetch phase remains unchanged from the fetch phase of the previous clock cycle.

And when more than or equal to two edges appear in one clock cycle, judging whether the position of the access phase of the previous clock cycle is in the front or back K phases of the current clock cycle and whether the edges appear, if so, moving the access phase of the previous clock cycle backwards or forwards by K +1 phases to be used as the access phase of the current clock cycle, otherwise, keeping the access phase of the previous clock cycle unchanged.

The number of times Data _ valid of fetching in one clock cycle and the fetch phase Data _ addr1 or Data _ addr2 are output simultaneously.

And a data selector 35, configured to obtain the recovered serial data according to the access phase.

In practical applications, the Data selector 35 outputs the M sample Data as local clock serial Data _ OUT by using a 0-phase clock through an asynchronous First-in First-OUT queue (FIFO) according to the number of times of Data _ valid and the selected access phase Data _ addr1 or Data _ addr 2.

The embodiment of the invention can achieve the following technical effects:

the serial data recovery interface solves the problem that data synchronization cannot be carried out because the adjacent phase delay is too small when the high-speed multi-phase clock acquires data and is smaller than the delay of the fastest trigger unit in the standard unit library, and a half-period allowance is reserved, so that the serial data recovery interface can be applied to a wider manufacturing process; and the [ K, M-K ] interval is utilized, data acquisition is carried out by utilizing a single edge, and the influence of burrs during phase switching is eliminated.

Furthermore, the serial data recovery problem under the condition of frequency deviation at the two ends of the transceiver is effectively solved, the range of the tolerated frequency deviation is larger, the precision of phase adjustment is higher, the problem of burrs caused by switching of a high-frequency multi-phase clock is avoided, and the transmission error rate is improved; the serial data recovery interface has simple structure and small time sequence pressure, and can simultaneously support the over-sampling recovery of odd or even number of phases.

Fig. 4 is a schematic diagram illustrating the effect of different numbers of edges included in one clock cycle, taking M as 16 as an example, as shown in fig. 4:

for the case 41 containing 0 edges in one clock cycle: the fetch phase of cycle _1 is 6, and the fetch phase of cycle _2 is 6+ 8-14; if the number of edges included in cycle _3 is 0, the sampling phase of the previous cycle is kept unchanged, and the sampling is still performed at 6+ 8-14 phases.

For the case 42 containing 2 edges in one clock cycle: because the clock period of the data is more and more in phase clock period, and the cycle _3 is normally free of jitter and glitch, the fetch phase of the cycle _2 is 7, when the cycle _3 includes 2 times of edges, the position corresponding to the fetch phase of the cycle _2 has no edge in the K phases before or after the cycle _3, and then the fetch phase 7 of the cycle _2 is kept unchanged.

For the case 43 containing more than 2 edges in one clock cycle: and (3) irregular jitter appears in the cycle _3, whether an edge appears in 3 phases before or after the access phase of the previous clock cycle is judged, if so, the phase is moved in the opposite direction by 4 phases to be the current access phase, and otherwise, the access phase of the previous clock cycle is kept unchanged.

For the case 44 where one edge occurs in one clock cycle: and judging whether the edge is in the interval of [4, 12], if so, updating the access phase.

In addition to the above, the following special cases are included:

when the phase of the Data clock is more than the phase clock period, it can be said that the speed of the Data clock is faster, and a waveform shown in a case 45 appears, where the fetch phase of the cycle _2 is 15, the phase corresponding to the edge of the cycle _3 is 8, the fetch phase determined by the cycle _3 is 8+8-16, which is 0, and the output Data _ valid is 0, which indicates that the cycle _3 does not fetch Data.

When the phase of the Data clock is more than the phase clock period, it can be said that the speed of the Data clock is slower, and a waveform shown in the case 46 appears, where the fetch phase of the cycle _2 is 8+8-16, the phase corresponding to the edge of the cycle _3 is 7, the fetch phase of the cycle _3 is 7+ 8-15, and the output Data _ valid is 2, which indicates that the cycle _3 needs to fetch Data twice.

Fig. 5 is a schematic diagram illustrating a hardware structure of an electronic device according to an embodiment of the present invention. As shown in fig. 5, the electronic device 50 includes a processor 501 and a communication interface 502.

As shown in fig. 5, the processor may be a general processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more ics for controlling the execution of programs according to the present invention. The number of the communication interfaces may be one or more. The communication interface may use any transceiver or the like for communicating with other devices or communication networks.

As shown in fig. 5, the electronic device may further include a communication line 503. The communication link may include a path for transmitting information between the aforementioned components.

Optionally, as shown in fig. 5, the electronic device may further include a memory 504. The memory is used for storing computer-executable instructions for implementing the inventive arrangements and is controlled by the processor for execution. The processor is used for executing the computer execution instructions stored in the memory, thereby realizing the method provided by the embodiment of the invention.

As shown in fig. 5, the memory may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a Random Access Memory (RAM) or other types of dynamic storage devices that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory may be separate and coupled to the processor via a communication link. The memory may also be integral to the processor.

Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in this embodiment of the present invention.

In one implementation, as shown in FIG. 5, processor 501 may include one or more CPUs, such as CPU0 and CPU1 of FIG. 5, for example.

In one implementation, as shown in FIG. 5, an electronic device may include multiple processors, such as processor 501-1 and processor 501-2 in FIG. 5, for example. Each of these processors may be a single core processor or a multi-core processor.

Fig. 6 is a schematic structural diagram of a chip according to an embodiment of the present invention. As shown in fig. 6, the chip 60 includes one or more (including two) processors 501 and a communication interface 502.

Optionally, as shown in FIG. 6, the chip also includes memory 504, which may include read-only memory and random access memory, and provides operating instructions and data to the processor. The portion of memory may also include non-volatile random access memory (NVRAM).

In some embodiments, as shown in FIG. 6, the memory stores elements, execution modules or data structures, or a subset thereof, or an expanded set thereof.

In the embodiment of the present invention, as shown in fig. 6, by calling an operation instruction stored in the memory (the operation instruction may be stored in the operating system), a corresponding operation is performed.

As shown in fig. 6, a processor, which may also be referred to as a Central Processing Unit (CPU), controls the processing operations of any of the electronic devices.

As shown in fig. 6, the memories may include both read-only memories and random access memories and provide instructions and data to the processor. The portion of memory may also include NVRAM. For example, in applications where the memory, communication interface, and memory are coupled together by a bus system that may include a power bus, a control bus, a status signal bus, etc., in addition to a data bus. For clarity of illustration, however, the various buses are labeled as bus system 505 in FIG. 6.

As shown in fig. 6, the method disclosed in the above embodiments of the present invention may be applied to a processor, or may be implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an ASIC, an FPGA (field-programmable gate array) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

In one aspect, a computer-readable storage medium is provided, in which instructions are stored, and when the instructions are executed, the functions performed by the electronic device in the above embodiments are implemented.

In one aspect, a chip is provided, where the chip is applied to an electronic device, and the chip includes at least one processor and a communication interface, where the communication interface is coupled to the at least one processor, and the processor is configured to execute instructions to implement the functions performed by the electronic device in the foregoing embodiments.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the procedures or functions described in the embodiments of the present invention are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a terminal, a user device, or other programmable apparatus. The computer program or instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program or instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable medium may be a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape; or optical media such as Digital Video Disks (DVDs); it may also be a semiconductor medium, such as a Solid State Drive (SSD).

While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A serial data recovery method, comprising:

2. The serial data recovery method of claim 1, wherein said determining edge information in one clock cycle based on said M sampled data comprises:

obtaining M pieces of exclusive or data according to M pieces of sampling data of one clock period and first sampling data of an adjacent clock period;

and determining the edge information in the clock period according to the M pieces of exclusive-or data.

3. The serial data recovery method of claim 2, wherein said obtaining M exclusive or data according to M sampled data of one clock cycle and the first sampled data of an adjacent clock cycle comprises:

performing exclusive OR operation on adjacent sampling data of the M sampling data in one clock period to obtain M-1 exclusive OR data;

and carrying out exclusive OR operation on the last sampling data in one clock period and the first sampling data in the adjacent clock period to obtain Mth exclusive OR data.

4. The serial data recovery method of claim 2, wherein said determining edge information in said one clock cycle based on said M xor data comprises:

adding the M pieces of exclusive or data to obtain an addition result;

and determining the number of edges contained in the edge information in one clock period according to the addition result.

5. The serial data recovery method of claim 4, wherein said determining the number of edges included in the edge information in the clock cycle according to the addition result comprises:

determining the number of edges included in the one clock cycle to be 0 in the case where the addition result is equal to 0;

determining the number of edges included in the one clock cycle to be 1 in the case that the addition result is equal to 1;

determining that the number of edges included in the one clock cycle is greater than or equal to 2, in a case where the addition result is greater than or equal to 2.

6. The serial data recovery method of claim 1, wherein said determining the access phase of said one clock cycle based on said edge information comprises:

and determining that the fetch phase of the clock cycle is consistent with the fetch phase of the previous clock cycle when the number of edges contained in the edge information is equal to 0.

7. The serial data recovery method of claim 1, wherein said determining the access phase of said one clock cycle based on said edge information comprises:

under the condition that the number of edges contained in the edge information is equal to 1, judging whether the phase corresponding to the edge position in one clock period is in a [ K, M-K ] interval or not; k represents the maximum occupied phase proportion value of the data burr;

if yes, updating the access phase of one clock cycle to the phase of the edge position and increasing M/2 phases; if not, the access phase of the clock cycle is consistent with the access phase of the previous clock cycle.

8. The serial data recovery method of claim 1, wherein said determining the access phase of said one clock cycle based on said edge information comprises:

under the condition that the number of edges contained in the edge information is greater than or equal to 2, judging whether the access phase of the previous clock cycle has edges in K phases before or after the corresponding position in the clock cycle;

if yes, updating the access phase of the clock period to the access phase of the previous clock period, and increasing or decreasing K +1 phases; and if not, the access phase of the clock cycle is consistent with the access phase of the previous clock cycle.

9. A serial data recovery interface, comprising: the device comprises a data sampler, a buffer synchronizer, an edge detector, a decision device and a data selector; wherein the content of the first and second substances,

10. An electronic device comprising the serial data recovery interface of claim 9.