CN113037667B - Data signal recovery method based on FPGA - Google Patents

Data signal recovery method based on FPGA Download PDF

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CN113037667B
CN113037667B CN202110209319.5A CN202110209319A CN113037667B CN 113037667 B CN113037667 B CN 113037667B CN 202110209319 A CN202110209319 A CN 202110209319A CN 113037667 B CN113037667 B CN 113037667B
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CN113037667A (en
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胡绍刚
钟利斌
肖航
李靖
宁宁
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University of Electronic Science and Technology of China
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L25/03012Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
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    • H04L25/03089Theory of blind algorithms, recursive or not

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Abstract

The invention relates to the technical field of electronic communication, in particular to a data signal recovery method based on an FPGA (field programmable gate array). Aiming at the data transmission condition in a blind sampling form, the working frequency of the system is reduced by the multiphase clock; the odd number of phases are skillfully used to determine the size of the clock period occupied by the pulse, so that the accuracy of data recovery can be greatly improved; and the phase difference between the jumping edges is used for judging the burrs and the effective data, so that the accuracy of data recovery is further improved. Finally, the invention realizes the data recovery of distortion in the transmission process, has higher recovery precision, reduces the high requirement on clock frequency under the condition of not needing frequency doubling, simultaneously optimizes the data recovery, greatly reduces the data deviation caused by burrs in the data transmission process and has low time sequence requirement.

Description

Data signal recovery method based on FPGA
Technical Field
The invention relates to the technical field of electronic communication, in particular to a data signal recovery method based on an FPGA (field programmable gate array).
Background
With the development of communication technology and electrical signal processing technology, serial data communication is increasingly applied to telecommunications, optical transceivers, data storage local area networks and wireless products, and the transmission rate is also increasing. In serial data communication, in order to save overhead and development board resources, there is a common situation that a sending end and a receiving end only allow a data signal to be transmitted between the sending end and the receiving end without transmitting a clock synchronous with the data signal due to resource limitation, that is, the receiving end receives the data signal in a blind sampling form, the blind sampling relates to data signal processing in an asynchronous clock domain, and the prior art generally adopts methods of 'two-beat', asynchronous FIFO ', handshake' protocols and the like, so that normal receiving and sending of the sending end and the receiving end are realized.
The two-beat mode refers to a mode that a data receiving end eliminates a metastable state through two-time sampling, and is generally used for transmitting a trigger signal, so that the accuracy of the width of a data signal pulse cannot be ensured. Asynchronous FIFO needs to be under the condition that a sending clock of a sending end and a receiving clock of a receiving end are known and available at the same time, data are transited through the FIFO and then read out, and the requirement on the working frequency accuracy of an FPGA system clock is high. The handshake protocol requires that a certain self-defined protocol is used between a sending end and a receiving end, the sending end packages data, so that the receiving end can distinguish valid data from invalid data, the receiving end samples the data of the data receiving end in an oversampling manner to ensure that data signals are not lost, and in the data signal transmission process, the data signals are not distorted too much to ensure that handshake is performed normally.
The above techniques are all the existing transmission modes of normal data signal streams in the form of blind sampling. For the condition that a data signal is distorted due to the influence of factors such as wiring and parasitic effect under the blind sampling condition, the current data recovery method mainly detects the rising and falling edges of a data stream by an N frequency multiplication oversampling method, thereby recovering data on the basis. However, this data recovery method has certain drawbacks: firstly, due to the existence of N-times, the clock frequency becomes very large, and when the local clock crystal oscillator is not very accurate, a large error is generated, and the effect is not particularly good; secondly, when the data distortion is serious, the influence caused by the burrs is difficult to distinguish; third, the timing requirements are high due to the large clock frequency, and can be violated inadvertently. Therefore, this method has high requirements on clock accuracy, distortion degree of data stream and timing.
Disclosure of Invention
Aiming at the defects or the improvement requirements of the prior art, the invention provides a data signal recovery method based on an FPGA (field programmable gate array), aiming at the blind sampling condition, saving global resources as much as possible under the condition of ensuring the data signal recovery precision, reducing the working frequency of a system, and eliminating the influence caused by burrs as much as possible, thereby solving the technical problems of higher requirement on the clock precision of the FPGA system, larger distortion of data signal flow, existence of burrs and the like when the data signal is recovered at present.
A data signal recovery method based on FPGA includes the following steps:
step 1, using the local clock, a receiving side system clock a having the same frequency as the known transmitting side clock is generated using FPGAPLL (phase locked loop), and sub-clocks B, C, D and E having phase differences of 72 °, 144 °, 216 °, and 288 ° from the receiving side system clock a are generated.
And 2, respectively sampling the input signals by using the five paths of clocks generated in the step 1, and respectively recording the sampling results as temp _ A, temp _ B, temp _ C, temp _ D and temp _ E.
Step 3, converting the sampling results temp _ A, temp _ B, temp _ C, temp _ D and temp _ E obtained in the step 2 into an A clock domain;
further, the specific operation of step 3 is to use two registers a _ temp _ A, Y _ a to beat temp _ a for two beats, and finally the temp _ a data signal transitions to Y _ a, and similarly, the temp _ B data signal transitions to Y _ B, the temp _ C data signal transitions to Y _ C, the temp _ D data signal transitions to Y _ D, and the temp _ E data signal transitions to Y _ E.
And 4, delaying the Y _ A, Y _ B, Y _ C, Y _ D and the Y _ E in the A clock domain obtained in the step 3 by one clock through a register, and sequentially generating X _ A, X _ B, X _ C, X _ D and X _ E respectively, so that two groups of Y-group and X-group sampling data are generated, wherein the two groups of data are in a front-back group relationship, the Y-group is the current group of data, and the X-group is the previous group of data.
And step 5, accessing the Y-group data obtained in the step 4 into a judging and data recovering module, analyzing the sampling results of the Y-group data and the previous X-group data, and counting and analyzing the attributes and the positions of the front and the back jumping edges in the clock domain A to determine a data output value and the value of a data length counter so as to recover the data signal.
The step 5 specifically comprises the following steps:
s1, judging whether jumping edges exist in Y-group data or not, and the number and attributes of the jumping edges;
s2, judging whether the X group of data has a jumping edge or not according to the jumping edge condition of the Y group of data;
when the Y group of data has no jumping edge, judging whether X group has jumping edge, including:
if the X group has no jumping edge, the output data is the data sampled by the current Y group;
the X group has a jumping edge, the output data is the data sampled by the current Y group, the position of the jumping edge is recorded, and a data width counter needs to be added by 1;
there are at least two hopping edges for group X: firstly, judging whether the jumping edges are effective or not, if the phase difference between the adjacent jumping edges is two or less, judging that the jumping edges are ineffective, outputting data as the current Y-group sampled data without recording the position of the jumping edges, and if the phase difference between the jumping edges is three or more, outputting the data as the current Y-group sampled data; and recording the position of the last jumping edge of the X groups, wherein the data width counter needs to add 1 as the recovery basis of the next group of data.
The case of one hopping edge in the Y group: judging whether the X group has a jumping edge, if not, judging data output according to the position of the Y group jumping edge and the position of the last recorded jumping edge; if the attribute and the position condition of the record exist, the concrete steps are as follows;
there is one hop edge in group X: firstly, judging whether the two jumping edges are effective jumping edges or burrs generated in the data information transmission process according to the phase difference between the two jumping edges, if the phase difference between the two jumping edges is three or more, judging the two jumping edges to be effective jumping edges, and if the two jumping edges are not effective jumping edges; if the transition edge is judged to be invalid, judging that the burr data output has no relation with burrs, so that the output data is stable data beside the invalid transition edge, if the stable data is 1, outputting 1, otherwise, outputting 0; if the current data output is judged to be the effective jumping edge, the current data output is judged according to the position of the jumping edge and the previous data output.
When one hopping edge exists in the X group, the situation that the X group is judged to be a valid hopping edge comprises the following steps:
the output of the previous data is 0, and the X groups of jumping edges are rising edges, so that the output data is 1;
the output of the previous data is 1, the X group jumping edge is a rising edge and is positioned at an AB or BC phase, if the position of the Y group jumping edge is positioned at a CD or DE, the output data is 1, and if the position of the Y group jumping edge is positioned at an AB or BC, the output data is 0;
the output of the previous data is 1, and the X groups of jumping edges are falling edges, so that the output data is 0;
the output of the previous data is 0, the X group jumping edge is a falling edge and is positioned at the AB or BC phase, if the position of the Y group jumping edge is positioned at the CD or DE, the output data is 0, and if the position of the Y group jumping edge is positioned at the AB or BC, the output data is 1.
When there are at least two hopping edges in group X: firstly, judging whether the jumping edges are effective or not, if the phase difference between two adjacent jumping edges is less than two, judging that the jumping edges are ineffective, and outputting X groups of data recovery values; if the jumping edge is valid, the output data is the opposite value of the X groups of recovery data.
When two jumping edges exist in the Y group of data: firstly, judging whether the two jumping edges are effective jumping edges or burrs generated in the data information transmission process according to the phase difference between the two jumping edges, if the phase difference between the two jumping edges is three or more, judging the two jumping edges to be effective jumping edges, and if the two jumping edges are not effective jumping edges; if the transition edge is judged to be invalid, judging that the glitch data is irrelevant to glitch output, so that the output data is stable data beside the invalid transition edge, and outputting 1 if the stable data is 1, otherwise outputting 0, if the transition edge is judged to be valid, outputting the data as a stable part between two transition edges, and if the stable part is 0, outputting 0, otherwise, outputting 1.
When the Y group data has more than two jumping edges: if the number of the jumping edges is odd, firstly judging the phase difference relation of adjacent jumping edges, if all the jumping edges are smaller than three phases, judging that only the first jumping edge is an effective jumping edge, and if the phase difference between two jumping edges is larger than three, judging that the effective jumping edge in the Y group is located at the last jumping edge; if the number of the jumping edges is even, firstly judging the phase difference relation of the adjacent jumping edges, if all the jumping edges are smaller than three phases, judging that the jumping edges in the Y group are invalid jumping edges, namely no jumping edge exists in the Y group, and if the phase difference between two jumping edges is larger than three, judging that the valid jumping edges in the Y group are located at the first jumping edge and the last jumping edge.
And if the Y group has at least two jumping edges, judging whether the data between the jumping edges is valid according to the phase difference between two adjacent jumping edges, if the phase difference between the two jumping edges is two or less, the data between the jumping edges is invalid, and if the phase difference between the jumping edges is three or more, judging the data to be valid. The invalid transition edges in group Y are removed leaving only three cases, including: no hopping edge exists in the Y group, one hopping edge exists in the Y group, and two hopping edges exist in the Y group. Specifically, the recovery of data can be determined by converting the case that multiple jumping edges exist in the Y group into the case that only 0, 1, or 2 jumping edges exist in the Y group.
The working principle of the data length counter is as follows: and when the effective jumping edge does not exist in the data of the group, adding 1 to the data length counter, and if the effective jumping edge exists in the data of the group, resetting the data length counter.
The method for judging whether the jumping edge exists and the attribute of the jumping edge exists comprises the following steps: if the sampled data of two adjacent phases are different, a jump edge exists, for example, if the sampled data of the phase A in the group Y is 0, the sampled data of the phase B is 1, a rising edge exists between the phases AB.
The method for judging whether the jump edge is effective is as follows: judging the phase difference between two adjacent jumping edges and the jumping edge, if the phase difference is more than or equal to three phase differences, the phase difference is valid, otherwise, the phase difference is invalid, for example, when three jumping edges exist in the Y group, the three jumping edges are respectively an AB rising edge, a BC falling edge and a CD rising edge, according to the judgment method, the jumping edge between the BC and the CD is an invalid jumping edge, and only one AB rising edge exists in the jumping edge of the Y group.
The step of counting and analyzing the attributes and positions of the two groups of jumping edges comprises the following steps:
acquiring X, Y two groups of sampling data, recording the sampling data as rising edges and recording positions at jumping points from 0 to 1, for example, if the sampling data of the phase B of the X group is 0 and the sampling data of the phase C is 1, recording the jumping edges as rising edges and the positions are the BC of the X group;
similarly, a falling edge is recorded at a 1 to 0 transition point, and position information is recorded, for example, if Y groups of C phase sampling data are 1 and D phase sampling data are 0, a falling edge is recorded and the position is Y groups of CDs.
In summary, for the data transmission condition in the blind sampling form, the working frequency of the system is reduced by the multiphase clock; the odd number of phases are skillfully used to determine the size of the clock period occupied by the pulse, so that the accuracy of data recovery can be greatly improved; and the burr and the effective data are judged through the phase difference between the jumping edges, the accuracy of data recovery is further improved, and the time sequence requirement is low.
Drawings
FIG. 1 is a schematic flow diagram of the present invention;
FIG. 2 is a schematic diagram of the system of the present invention;
FIG. 3 is a flow diagram of a determination, data recovery module of the present invention;
FIG. 4 is a flow chart of the present invention for determining that there is a transition edge in the Y-group data in the data recovery module;
FIG. 5 is a flow chart of the present invention for determining the existence of two transition edges in the Y-set data in the data recovery module.
Detailed Description
The present invention will be described in further detail with reference to the following drawings and specific embodiments, it should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention.
Referring to fig. 1, the present invention provides a method for recovering a data signal based on an FPGA. In the embodiment, a clone V-generation FPGA developed by altera company is mainly used as an experimental tool.
The present embodiment further explains the determination module. Referring to Table 1, in this example, it is determined whether a partial truth table is recorded for the valid transition edge positions, where Y is the set of input data, c _ out [3:0] is the transition edge position and attribute, where c _ out [3] is 1 for the rising edge and falling edge, and conversely, c _ out [2:0] for the position, 2 'b 001 for the AB, 2' b001 for the BC, 2 'b 001 for the CD, and 2' b001 for the DE.
A B C D E C_out[3] C_out[2] C_out[1] C_out[0]
0 0 0 0 1 1 1 0 0
0 0 0 1 0 1 0 1 1
0 0 1 0 0 1 0 1 0
0 1 0 0 0 1 0 0 1
1 0 0 0 0 0 0 0 1
1 1 0 0 0 0 0 1 0
1 1 1 0 0 0 0 1 1
1 1 1 1 0 0 1 0 0
TABLE 1
Referring to table 2, in this example, it is determined whether the transition edge is a partial truth table of valid transition edges, c _ in [3:0] represents the position and property of the previous group of transition edges, c _ out [3:0] represents the position and property of the transition edge of the present group, t represents valid, and t is 1, which is mainly implemented by determining whether the sum of the sums of 5(3 'b 101) -c _ in [2:0] and c _ out [2:0] is greater than 3 (i.e., 3' b 011).
Figure BDA0002950817680000061
Figure BDA0002950817680000071
TABLE 2
Referring to table 3, in this example, it is determined whether the data recovery value, the position of the current group of transition edges, the transition edges are valid, and a partial truth table of the previous group of output values, where c _ out [3:0] is the position and attribute of the transition edge, t is valid, p is the previous group of data recovery output values, and q is the recovered group of output data.
C_out[3] C_out[2] C_out[1] C_out[0] t p q
1 0 0 1 0 1 1
1 0 1 0 1 0 1
1 1 0 0 1 1 0
1 0 1 1 0 0 0
0 1 0 0 0 1 1
0 0 0 1 0 1 1
0 0 1 0 1 0 1
0 0 1 1 1 1 0
TABLE 3
To be further interpreted:
if there is no jump edge in the group Y, the input data is 5'b0000, c _ out [3:0] ═ 4' b0000, and the value of the output q is determined according to the magnitudes of c _ in, counter, and p, for example, if c _ in equals 4 'b 0011, counter equals 4' b0000, and p equals 1, it is verified that there is a falling jump edge between the groups X CD, and at this time, the jump edge in the groups X is determined to be valid, so t equals 0, q equals 0, and counter equals counter + 1.
If one transition edge exists in the Y group, the Y group is determined to be a rising edge and located between the DE, the input data is 5' b00001 ' c _ out is 4 ' b1100, and the value of the output q is determined according to the magnitudes of p, c _ in and counter, for example, if p is 1, c _ in is 4 ' b0011 and counter is 4 ' b0000, it is proved that one transition edge exists between the X group CDs, and the previous group data transition edge is a falling edge, q is 0.
Similarly, if there are two transition edges AB and DE in the Y group, the AB is determined to be a rising edge, and DE is a falling edge, then c _ out is 4 ' b0100, and the output value needs to be determined according to the sum of c _ in and counter, for example, c _ in is 4 ' b0001, and counter is 4 ' b0000, then there is one transition edge between the positive X group AB, and since the phase difference between AB and two adjacent transition edges is three or more, the determination is valid, that is, t is 1, and the value of q is a stable value between AB and DE transition edge, so the q output is 1.
The output of the Y group, i.e. the current group of data, needs to be determined according to the position of the effective jump edge, the output of the previous group of data, i.e. the current value of p, and the value of counter.
Referring to fig. 3, the specific conditions of the determining module in step 5 include:
and when the jumping edge does not exist in the Y group, judging the position and the condition of the jumping edge of the X group:
and if the X group has no jumping edge, the output data is the data sampled by the current Y group, and the data width counter needs to be added by 1.
And a jumping edge exists in the X group, the output data is the data sampled by the current Y group, the position of the jumping edge is recorded, and 1 is added to the data width counter.
The method comprises the steps that multiple jumping edges exist in an X group, whether the jumping edges are effective or not is judged firstly, if the phase difference between adjacent jumping edges is two or less, the jumping edges are judged to be invalid, output data are data sampled by a current Y group, the position of the jumping edges is not required to be recorded, if the phase difference between the jumping edges is three or more, the output data are data sampled by the current Y group, the position of the last jumping edge of the X group is recorded, and a data width counter needs to be added by 1.
Referring to fig. 4, when there is a transition edge in the group Y, where c _ in is the position and attribute of the transition edge of the previous group of data, Y is the input data of the group, X is the input data of the previous group, c _ out is the position and attribute of the transition edge of the group, counter is the data length counter, p is the recovered output of the previous group of data, and q is the recovered output data of the group. At this time, the position and situation of the jumping edge of the X group need to be judged:
if there is no jump edge in the X group, the data output and the data width need to be determined according to the position and situation of the jump edge recorded in the previous data, for example, if there is a rising edge between the BC in the Y group, and the position of the jump edge recorded in the previous time is at BC, the data output is 0.
The X group has a jump edge, whether the jump edge is an effective jump edge or a burr generated in the data information transmission process is judged according to the phase difference between two jump edges, if the phase difference between the two jump edges is three or more, the jump edge is judged to be an effective jump edge, and if the phase difference is not more than three, the jump edge is judged to be an invalid jump edge.
If the transition edge is judged to be invalid, the burr data is judged to output irrelevant burrs, so the output data is stable data beside the transition edge, 1 is output if the stable data is 1, and otherwise 0 is output.
The case of determining the effective jump edge includes:
the output of the previous data is 0, and the X groups of jumping edges are rising edges, so that the output data is 1.
And if the position of the Y group jumping edge is located at CD or DE, the output data is 1, and if the position of the Y group jumping edge is located at AB or BC, the output data is 0.
The output of the previous data is 1, and the X groups of jumping edges are falling edges, then the output data is 0.
And if the position of the Y group jumping edge is located at CD or DE, the output data is 0, and if the position of the Y group jumping edge is located at AB or BC, the output data is 1.
Referring to fig. 5, there are two jumping edges in the Y group, where c _ in is the position and attribute of the jumping edge of the previous group, Y is the input data of the group, X is the input data of the previous group, c _ out is the position and attribute of the jumping edge of the group, counter is the data length counter, p is the recovered output of the previous group, and q is the recovered output data of the group. At this time, the position and situation of the jumping edge of the X group need to be judged:
firstly, whether the X groups have jumping edges needs to be judged, and secondly, whether the X groups are effective jumping edges or burrs generated in the data information transmission process needs to be judged according to the phase difference between the two jumping edges. If the phase difference between the two jumping edges is three or more, judging the jumping edges to be effective, otherwise, judging the jumping edges to be ineffective; if the transition edge is judged to be invalid, judging that the burr data output has no relation with burrs, so that the output data is stable data beside the invalid transition edge, if the stable data is 1, outputting 1, otherwise, outputting 0; if the transition edge is judged to be valid, the data is output as a stable part between the two transition edges, if the stable part is 0, the data is output as 0, otherwise, the data is output as 1.
The case that more than two jumping edges exist in the Y group comprises the following steps:
the method comprises the steps that Y groups have a plurality of jumping edges, the number of the jumping edges is odd, the phase difference relation of adjacent jumping edges is judged firstly, if all the jumping edges are smaller than three phases, only the first jumping edge is judged to be an effective jumping edge, and if the phase difference between two jumping edges is larger than three, the effective jumping edge in the Y groups is judged to be located at the last jumping edge;
the method comprises the steps that a plurality of jumping edges exist in a Y group, the number of the jumping edges is even, the phase difference relation of adjacent jumping edges is judged firstly, if all the jumping edges are smaller than three phases, the jumping edges in the Y group are judged to be invalid jumping edges, namely, the jumping edges do not exist in the Y group, and if the phase difference between two jumping edges is larger than three, the effective jumping edges in the Y group are judged to be located at the first jumping edge and the last jumping edge.
Therefore, when more than two jumping edges exist in the Y group, the invalid jumping edges in the Y group are removed through optimization, and only three cases are left, including: no hopping edge exists in the Y group, one hopping edge exists in the Y group, and two hopping edges exist in the Y group.
Specifically, the recovery of data can be determined by converting the case that multiple jumping edges exist in the Y group into the case that only 0, 1, or 2 jumping edges exist in the Y group.
The embodiment shows that the working frequency of the system is reduced by the multi-phase clock aiming at the data transmission condition in the blind sampling form; the odd number of phases are skillfully used to determine the size of the clock period occupied by the pulse, so that the accuracy of data recovery can be greatly improved; and the phase difference between the jumping edges is used for judging the burrs and the effective data, so that the accuracy of data recovery is further improved. Finally, the invention realizes the data recovery of distortion in the transmission process, has higher recovery precision, reduces the high requirement on clock frequency under the condition of not needing frequency doubling, simultaneously optimizes the data recovery, greatly reduces the data deviation caused by burrs in the data transmission process and has low time sequence requirement.

Claims (2)

1. A data signal recovery method based on FPGA includes the following steps:
step 1, using local clock to generate a receiving end system clock A with the same frequency as the known sending end clock by utilizing FPGAPLL phase-locked loop, and generating a phase difference 72 with the receiving end system clock A
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、144
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、216
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And 288
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Phase-shifted sub-clocks B, C, D and E;
step 2, sampling the input signals by using the five paths of clocks generated in the step 1 respectively, and recording sampling results as temp _ A, temp _ B, temp _ C, temp _ D and temp _ E respectively;
step 3, converting the sampling results temp _ A, temp _ B, temp _ C, temp _ D and temp _ E obtained in the step 2 into an A clock domain;
step 4, delaying the Y _ A, Y _ B, Y _ C, Y _ D and the Y _ E in the clock domain A obtained in the step 3 by one clock through a register, and sequentially generating X _ A, X _ B, X _ C, X _ D and X _ E respectively, so that two groups of sampling data of a Y group and an X group are generated, wherein the two groups of sampling data are in a front-back group relation, the Y group is the current group of data, and the X group is the previous group of data;
step 5, the Y group data obtained in the step 4 is accessed to a judging and data restoring module, the sampling results of the Y group data and the previous group of X group data are analyzed, and the attributes and the position conditions of the front and the back jumping edges are counted and analyzed in the clock domain A to determine the data output value and the value of a data length counter and restore the data signals;
the method specifically comprises the following steps:
s1, judging whether jumping edges exist in Y-group data or not, and the number and attributes of the jumping edges;
s2, judging whether the X group of data has a jumping edge or not according to the jumping edge condition of the Y group of data;
when the Y group of data has no jumping edge, judging whether X group has jumping edge, including:
if the X group has no jumping edge, the output data is the data sampled by the current Y group;
the X group has a jumping edge, the output data is the data sampled by the current Y group, the position of the jumping edge is recorded, and a data width counter needs to be added by 1;
there are at least two hopping edges for group X: firstly, judging whether the jumping edges are effective or not, if the phase difference between the adjacent jumping edges is two or less, judging that the jumping edges are ineffective, outputting data as the current Y-group sampled data without recording the position of the jumping edges, and if the phase difference between the jumping edges is three or more, outputting the data as the current Y-group sampled data; recording the position of the last jumping edge of the X groups, wherein the data width counter needs to add 1 to be used as the recovery basis of the next group of data;
the case of one hopping edge in the Y group: judging whether the X group has a jumping edge, if not, judging data output according to the position of the Y group jumping edge and the position of the last recorded jumping edge; if the attribute and the position condition of the record exist, the concrete steps are as follows;
there is one hop edge in group X: firstly, judging whether the two jumping edges are effective jumping edges or burrs generated in the data information transmission process according to the phase difference between the two jumping edges, if the phase difference between the two jumping edges is three or more, judging the two jumping edges to be effective jumping edges, and if the two jumping edges are not effective jumping edges; if the transition edge is judged to be invalid, judging that the burr data output has no relation with burrs, so that the output data is stable data beside the invalid transition edge, if the stable data is 1, outputting 1, otherwise, outputting 0; if the current data output is judged to be the effective jumping edge, the current data output is judged according to the position of the jumping edge and the previous data output;
when one hopping edge exists in the X group, the situation that the X group is judged to be a valid hopping edge comprises the following steps:
the output of the previous data is 0, and the X groups of jumping edges are rising edges, so that the output data is 1;
the output of the previous data is 1, the X group jumping edge is a rising edge and is positioned at an AB or BC phase, if the position of the Y group jumping edge is positioned at a CD or DE, the output data is 1, and if the position of the Y group jumping edge is positioned at an AB or BC, the output data is 0;
the output of the previous data is 1, and the X groups of jumping edges are falling edges, so that the output data is 0;
the output of the previous data is 0, the X group jumping edge is a falling edge and is positioned at the AB or BC phase, if the position of the Y group jumping edge is positioned at CD or DE, the output data is 0, and if the position of the Y group jumping edge is positioned at AB or BC, the output data is 1;
when there are at least two hopping edges in group X: firstly, judging whether the jumping edges are effective or not, if the phase difference between two adjacent jumping edges is less than two, judging that the jumping edges are ineffective, and outputting X groups of data recovery values; if the jumping edge is valid, outputting the data as the opposite value of the X groups of recovery data;
when two jumping edges exist in the Y group of data: firstly, judging whether the two jumping edges are effective jumping edges or burrs generated in the data information transmission process according to the phase difference between the two jumping edges, if the phase difference between the two jumping edges is three or more, judging the two jumping edges to be effective jumping edges, and if the two jumping edges are not effective jumping edges; if the transition edge is judged to be invalid, judging that the burr data output has no relation with burrs, if the output data is stable data beside the invalid transition edge, outputting 1 if the output data is 1, otherwise outputting 0, if the output data is judged to be valid transition edge, outputting the data as a stable part between two transition edges, if the stable part is 0, outputting 0, otherwise, outputting 1;
when the Y group data has more than two jumping edges: if the number of the jumping edges is odd, firstly judging the phase difference relation of adjacent jumping edges, if all the jumping edges are smaller than three phases, judging that only the first jumping edge is an effective jumping edge, and if the phase difference between two jumping edges is larger than three, judging that the effective jumping edge in the Y group is located at the last jumping edge; if the number of the jumping edges is even, firstly judging the phase difference relation of the adjacent jumping edges, if all the jumping edges are smaller than three phases, judging that the jumping edges in the Y group are invalid jumping edges, namely no jumping edge exists in the Y group, and if the phase difference between two jumping edges is larger than three, judging that the valid jumping edges in the Y group are located at the first jumping edge and the last jumping edge.
2. The FPGA-based data signal recovery method of claim 1, wherein:
the specific operation of step 3 is to use two registers a _ temp _ A, Y _ a to beat temp _ a for two beats, and finally the temp _ a data signal transitions to Y _ a, and similarly, the temp _ B data signal transitions to Y _ B, the temp _ C data signal transitions to Y _ C, the temp _ D data signal transitions to Y _ D, and the temp _ E data signal transitions to Y _ E.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102611447A (en) * 2012-03-26 2012-07-25 东北大学 Noise adding signal synchronization clock extraction device based on FPGA (field programmable gate array)
CN103219992A (en) * 2013-01-31 2013-07-24 南京邮电大学 Blind sampling clock data recovery circuit with filter shaping circuit
CN112073058A (en) * 2020-08-24 2020-12-11 烽火通信科技股份有限公司 Clock data recovery circuit and method based on FPGA

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102611447A (en) * 2012-03-26 2012-07-25 东北大学 Noise adding signal synchronization clock extraction device based on FPGA (field programmable gate array)
CN103219992A (en) * 2013-01-31 2013-07-24 南京邮电大学 Blind sampling clock data recovery circuit with filter shaping circuit
CN112073058A (en) * 2020-08-24 2020-12-11 烽火通信科技股份有限公司 Clock data recovery circuit and method based on FPGA

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Sigma-delta based clock recovery using on-chip PLL in FPGA;Ning Ge等;《2006 IEEE International Conference on Field Programmable Technology》;20070102;全文 *
基于FPGA的时钟数据恢复电路的研究和设计;任全会等;《郑州铁路职业技术学院学报》;20110930;第23卷(第3期);全文 *
无线通信接收机位同步时钟提取电路设计;林彬彬等;《电子技术》;20170425(第04期);全文 *

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