CN116432572A - FPGA prototype verification device and test verification method thereof - Google Patents

FPGA prototype verification device and test verification method thereof Download PDF

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CN116432572A
CN116432572A CN202310305776.3A CN202310305776A CN116432572A CN 116432572 A CN116432572 A CN 116432572A CN 202310305776 A CN202310305776 A CN 202310305776A CN 116432572 A CN116432572 A CN 116432572A
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test
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李新兵
龙雨佳
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Shanghai Xinlianxin Intelligent Technology Co ltd
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Shanghai Xinlianxin Intelligent Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/61—Installation
    • G06F8/63—Image based installation; Cloning; Build to order
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/02—System on chip [SoC] design
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention provides an FPGA prototype verification device and a test verification method thereof. The FPGA prototype verification device comprises a unit to be tested, a conversion logic unit and a plurality of first pins, wherein the unit to be tested comprises a second pin, and the first pin and the second pin are connected with the conversion logic unit. Burning a test file into the FPGA prototype verification device, wherein the test file comprises one or more test programs, at least part of the test programs comprise pin configuration instructions, and the pin configuration instructions comprise the connection relation between a first pin and a second pin under the test programs; and executing each test program in the test file, wherein when executing one test program with a pin configuration instruction, the pin configuration instruction is executed firstly to configure the connection relation between a first pin and a second pin under the test program, and then the rest programs in the test program are executed to carry out test verification. In this way, the test verification efficiency can be improved.

Description

FPGA prototype verification device and test verification method thereof
[ field of technology ]
The invention relates to the field of chip design, in particular to an FPGA (Field Programmable Gate Array ) prototype verification device and a test verification method based on the FPGA prototype verification device.
[ background Art ]
With the increasing design scale of SoC (System on Chip), the functions of the SoC (System on Chip) become more complex, and the verification stage of the chip occupies most of the time of the whole chip development. Because of the advantages of the FPGA, prototype verification based on the FPGA is widely applied.
FPGA prototype verification is a mature chip verification technology, by transplanting RTL ((Register Transfer Level, register transmission stage)) to a Field Programmable Gate Array (FPGA) to verify the function of ASIC ((Application Specific Integrated Circuit)), and after the basic function verification of the chip passes, development of driving and application can be started, and development of driving and application can be performed until the chip is back-on-chip, and after the chip is back-on-chip, driving and application programs based on FPGA version can be directly used for simple adaptation, so that the method can be applied to SoC chips.
The FPGA prototype verification is to burn the contents in ROM and RAM into the FPGA for test verification, and for some complex functions, pin configuration is required.
Fig. 1 shows a schematic structural diagram of a conventional FPGA prototype verification apparatus. As shown in fig. 1, the FPGA prototype verification apparatus 100 includes a unit under test (DUT) 110, a conversion logic unit 120, and a plurality of first pins 130, where the unit under test 110 includes a plurality of second pins 111, and the first pins 130 and the second pins 111 are connected to the conversion logic unit 120. The first pin may also be a board IO (board input/output) and the second pin 111 may be a GPIO (General-purpose input/output).
Fig. 2 is a flow chart of a test verification method 200 based on the FPGA prototype verification apparatus. As shown in fig. 2, the test verification method includes: step 210, writing a test program; step 220, the tester needs to send a pin configuration instruction to the conversion logic unit 120 of the FPGA prototype verification apparatus 100 through the serial port by the test terminal 500 (upper computer), where the conversion logic unit configures pins according to the pin configuration instruction, so that the second internal pins (GPIOs) are correspondingly connected with the corresponding first pins (boards IOs) of the FPGA prototype verification apparatus; step 230, burning the test program into the FPGA prototype verification apparatus; and step 240, executing the test program to perform a test.
However, this test verification method in the related art has the following problems.
The pin configuration mode of each test program may be different, the regression test script needs to carry the configuration modes of all the test programs, if the test programs need to be changed, the configuration modes in the regression test script also need to be changed, the sequence of the test programs should correspond to the sequence of the configuration pins, and the sequence error even causes the test failure of all the test programs, and each change means that the code contents on both sides of the test programs and the test terminals need to be maintained at the same time;
the test terminal for sending the pin configuration instruction and the FPGA prototype verification device are two different environments and have different working time sequences, which means that the comprehensive test scheme is complex, multiple systems and multiple time sequences are involved, and if the test terminal needs to wait for fixed time or needs the FPGA prototype verification device to return a completion signal and detect the completion signal after the test program is executed, the next test program can be executed. This results in a system with low scalability and low configurability, and requires additional consideration of the timing issues of the part each time a function is added to the system;
the test program generated must rely on the communication of the test terminal.
Therefore, a new solution is needed to solve the above problems.
[ invention ]
One of the purposes of the present invention is to provide an FPGA prototype verification apparatus and a test verification method based on the FPGA prototype verification apparatus, which do not need to perform pin configuration for each test program on a test terminal, so as to greatly improve test verification efficiency.
In order to solve the above problems, according to one aspect of the present invention, there is provided a test verification method based on an FPGA prototype verification apparatus, the FPGA prototype verification apparatus including a unit to be tested, a conversion logic unit, and a plurality of first pins, the unit to be tested including a plurality of second pins, the first pins and the second pins being connected to the conversion logic unit, the method including: burning a test file into the FPGA prototype verification device, wherein the test file comprises one or more test programs, at least part of the test programs comprise pin configuration instructions, and the pin configuration instructions comprise the connection relation between a first pin and a second pin under the test programs; and executing each test program in the test file, wherein when executing one test program with a pin configuration instruction, the pin configuration instruction is executed firstly to configure the connection relation between a first pin and a second pin under the test program, and then the rest programs in the test program are executed to carry out test verification.
In one embodiment, the pin configuration instructions are written in the C language.
In one embodiment, the pin configuration instruction includes a first pin field, a second pin field, and a bus address field, where the bus address field is a predetermined address, the first pin field records a first pin number, the second pin field records a second pin number, and when the test program is executed, if the predetermined address is monitored on the bus, the conversion logic unit connects the first pin of the first pin number and the second pin of the second pin number.
In one embodiment, the unit to be tested includes a UART interface, the test program includes a UART interface test program, and the UART interface test program includes the pin configuration instruction; when the UART interface test program is executed, if a preset address appears on a bus is monitored, the conversion logic unit configures the connection relation between the first pin and the second pin under the UART interface test program according to the first pin field and the second pin field of the pin configuration instruction, so that the UART interface is led out of the FPGA prototype verification device through the proper first pin to communicate with external UART interface equipment, and then the rest program of the UART interface test program is executed to carry out the test verification of the UART interface.
In one embodiment, the test program includes a waveform export test program, the waveform export test program includes the pin configuration instruction, when the waveform export test program is executed, if a predetermined address appears on the bus is monitored, the conversion logic unit configures a connection relationship between a first pin and a second pin under the waveform export test program according to a first pin field and a second pin field of the pin configuration instruction, so that the unit to be tested is led out of the FPGA prototype verification device through a suitable first pin to communicate with an external oscilloscope, and then test verification of waveform export is performed by executing the rest of the waveform export test program.
In one embodiment, the test program includes a clock test program, the clock test program includes the pin configuration instruction, when the clock test program is executed, if a predetermined address appears on the bus is monitored, the conversion logic unit configures a connection relationship between a first pin and a second pin under the clock test program according to a first pin field and a second pin field of the pin configuration instruction, so that the unit under test is led out of the FPGA prototype verification apparatus through a suitable first pin, and then the rest of the clock test program is executed to perform clock test verification.
According to another aspect of the present invention, there is provided an FPGA prototype verification apparatus, including a unit under test, a conversion logic unit, and a plurality of first pins, the unit under test including a second pin, the first pin and the second pin being connected to the conversion logic unit, including: burning a test file into the FPGA prototype verification device, wherein the test file comprises one or more test programs, at least part of the test programs comprise pin configuration instructions, and the pin configuration instructions comprise the connection relation between a first pin and a second pin under the test programs; and executing each test program in the test file, wherein when executing one test program with a pin configuration instruction, the pin configuration instruction is executed firstly to configure the connection relation between a first pin and a second pin under the test program, and then the rest programs in the test program are executed to carry out test verification.
In one embodiment, the pin configuration instructions are written in the C language.
In one embodiment, the pin configuration instruction includes a first pin field, a second pin field, and a bus address field, where the bus address field is a predetermined address, the first pin field records a first pin number, the second pin field records a second pin number, and when the test program is executed, if the predetermined address is monitored on the bus, the conversion logic unit connects the first pin of the first pin number and the second pin of the second pin number.
In one embodiment, the unit to be tested includes a UART interface, the test program includes a UART interface test program, and the UART interface test program includes the pin configuration instruction; when executing the UART interface test program, if a predetermined address appears on the bus, the conversion logic unit configures the connection relation between the first pin and the second pin under the UART interface test program according to the first pin field and the second pin field of the pin configuration instruction, so that the UART interface is led out of the FPGA prototype verification device through the appropriate first pin to communicate with external UART interface equipment, then the remaining program of the UART interface test program is executed to perform the test verification of the UART interface, the test program comprises a waveform export test program, the waveform export test program comprises the pin configuration instruction, when executing the waveform export test program, if the predetermined address appears on the bus, the conversion logic unit configures a connection relationship between a first pin and a second pin under a test program according to the first pin field and the second pin field of the pin configuration instruction, so that the unit to be tested is led out of the FPGA prototype verification device through a proper first pin to communicate with an external oscilloscope, then the rest program of the waveform-derived test program is executed to perform waveform-derived test verification, the test program comprises a clock test program, the clock test program comprises the pin configuration instruction, when the clock test program is executed, if a predetermined address appears on a bus is monitored, the conversion logic unit configures the connection relationship between the first pin and the second pin under the clock test program according to the first pin field and the second pin field of the pin configuration instruction, so that the unit to be tested is led out of the FPGA prototype verification device through a proper first pin, and then executing the rest program of the clock test program to perform clock test verification.
Compared with the prior art, the invention can integrate the test programs of all projects into a whole test file, is convenient for regression test work, and in addition, the tester does not need to perform pin configuration on the test terminal any more, and the configuration can be automatically performed by setting corresponding pin configuration instructions in the test program.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 shows a schematic diagram of a prior art FPGA prototype verification apparatus;
FIG. 2 is a flow chart of a test verification method based on the FPGA prototype verification apparatus;
FIG. 3 is a schematic diagram of the structure of an FPGA prototype verification apparatus of the present invention in one embodiment;
FIG. 4 is a flow chart of a test verification method based on the FPGA prototype verification apparatus shown in FIG. 3;
fig. 5 is an example of a correspondence table of bus addresses and their roles.
[ detailed description ] of the invention
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Unless specifically stated otherwise, the terms connected, or connected herein denote an electrical connection, either directly or indirectly.
In the present invention, unless specifically stated and limited otherwise, the terms "connected," "coupled," and the like should be construed broadly; for example, they may be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Fig. 3 shows a schematic structure of an FPGA prototype verification apparatus of the present invention in one embodiment. As shown in fig. 3, the FPGA prototype verification apparatus 300 includes a unit under test (DUT) 310, a conversion logic unit 320, and a plurality of first pins 330, where the unit under test 310 includes a plurality of second pins 311, and the first pins 330 and the second pins 311 are connected to the conversion logic unit 320. The conversion logic 320 may also be connected to the test terminal 600 through a serial port. The first pin may also be a board IO (board input/output) and the second pin 111 may be a GPIO (General-purpose input/output).
Fig. 4 is a flow chart of a test verification method 400 based on the FPGA prototype verification apparatus. As shown in fig. 4, the test verification method 400 includes the following steps.
In step 410, a test file is written, wherein the test file includes one or more test programs, and at least part of the test programs include pin configuration instructions, and the pin configuration instructions include a connection relationship between a first pin and a second pin under the test program. In another embodiment, this step 410 may be performed before the test verification method 400, i.e., the test verification method 400 may begin at step 420.
The pin configuration instruction is written in a C language, does not affect hardware, does not cause interruption, and is only executed as a configuration instruction in the prototype verification of the FPGA.
The pin configuration instruction comprises a first pin field, a second pin field and a bus address field, wherein the bus address field is a preset address, the first pin field is recorded with a first pin number, the second pin field is recorded with a second pin number, and when the test program is executed, if the preset address appears on the bus, the conversion logic unit connects the first pin of the first pin number with the second pin of the second pin number. For example, int=0xbfc07 FE 0=0xf103 is an example of one pin configuration instruction, where "0xBFC07FE0" is a predetermined address in the bus address field, "f1" is a first pin number recorded in the first pin field, "103" is a second pin number recorded in the second pin field, and "f1103" means that the first pin with the number "f1" and the second pin with the number "103" are connected together.
The bus address field for the pin configuration instruction may be custom, but certain conditions need to be met. Each operation on the bus has a respective address, and the CPU of the FPGA prototype verification device reads an operation execution command corresponding to the respective address. Functional operations corresponding to different address intervals on the bus are specified in the design process, refer to fig. 5 specifically. For example, it can be seen from FIG. 5 that the address "0xD4FFFFFF-0xD0000000" is QSPI (Queued Serial Peripheral Interface) External Memory for QSPI. For Reserved areas, the Reserved areas are not defined, and the preset address of the bus address field in the pin configuration command can be set in the address interval of Reserved, so that other functions cannot be interfered, and when the situation that the address corresponding to the configuration pin appears on the bus is monitored, the CPU of the FPGA prototype verification device can execute the pin configuration command.
The pin configuration instruction may have a plurality of first pin fields and a plurality of second pin fields corresponding to the plurality of first pin fields, so that the plurality of first pins and the corresponding plurality of second pins may be respectively connected through one pin configuration instruction.
The invention can integrate the test programs of all projects into a whole test file, thereby facilitating regression test work. Each test program may include pin configuration instructions, although for test programs that do not require pin configuration, pin configuration instructions need not be included.
And step 420, burning the test file into the FPGA prototype verification device.
And 430, executing each test program in the test file, wherein when executing one test program with a pin configuration instruction, the pin configuration instruction is executed first to configure the connection relation between the first pin and the second pin under the test program, and then the rest programs in the test program are executed for test verification.
By adopting the test verification method to carry out verification test, all the test programs can be integrated into one test file, so that the management and maintenance are easier, the configuration pins are not circularly executed as in the prior art, the test programs are burnt, and the test efficiency is improved. In addition, the tester does not need to perform pin configuration on the test terminal any more, and the configuration can be automatically performed by setting corresponding pin configuration instructions in the test program.
The centralized test procedure is listed below.
The unit under test 310 includes a UART interface, the test program includes a UART interface test program, and the UART interface test program includes the pin configuration instruction; when executing the UART interface test program, if it is detected that a predetermined address appears on the bus, the conversion logic unit 320 configures a connection relationship between the first pin and the second pin under the UART interface test program according to the first pin field and the second pin field of the pin configuration instruction, so that the UART interface is led out of the FPGA prototype verification device through the appropriate first pin to communicate with an external UART interface device, and then the remaining program of the UART interface test program is executed to perform test verification of the UART interface.
The test program comprises a waveform export test program, the waveform export test program comprises the pin configuration instruction, when the waveform export test program is executed, if a preset address appears on a bus is monitored, the conversion logic unit configures the connection relation between a first pin and a second pin under the waveform export test program according to a first pin field and a second pin field of the pin configuration instruction, so that the unit to be tested is led out of the FPGA prototype verification device through a proper first pin to communicate with an external oscilloscope, and then the rest program of the waveform export test program is executed to carry out test verification of waveform export.
The test program comprises a clock test program, the clock test program comprises the pin configuration instruction, when the clock test program is executed, if a preset address appears on a bus is monitored, the conversion logic unit configures the connection relation between a first pin and a second pin under the clock test program according to a first pin field and a second pin field of the pin configuration instruction, so that the unit to be tested is led out of the FPGA prototype verification device through a proper first pin, and then the rest program of the clock test program is executed to perform clock test verification.
According to another aspect of the present invention, the present invention provides an FPGA prototype verification apparatus, which includes the FPGA prototype verification apparatus 300 including a unit under test (DUT) 310, a conversion logic unit 320, and a plurality of first pins 330, where the unit under test 310 includes a plurality of second pins 311, and the first pins 330 and the second pins 311 are connected to the conversion logic unit 320. The FPGA prototype verification device comprises: burning a test file into the FPGA prototype verification device, wherein the test file comprises one or more test programs, at least part of the test programs comprise pin configuration instructions, and the pin configuration instructions comprise the connection relation between a first pin and a second pin under the test programs; and executing each test program in the test file, wherein when executing one test program with a pin configuration instruction, the pin configuration instruction is executed firstly to configure the connection relation between a first pin and a second pin under the test program, and then the rest programs in the test program are executed to carry out test verification.
In one embodiment, the pin configuration instruction includes a first pin field, a second pin field, and a bus address field, where the bus address field is a predetermined address, the first pin field records a first pin number, the second pin field records a second pin number, and when the test program is executed, if the predetermined address is monitored on the bus, the conversion logic unit connects the first pin of the first pin number and the second pin of the second pin number.
For further details of the FPGA prototype verification apparatus, please refer to the description of the test verification method of the FPGA prototype verification apparatus above.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art may combine and combine the different embodiments or examples described in this specification.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications and alternatives to the above embodiments may be made by those skilled in the art within the scope of the invention.

Claims (10)

1. The test verification method based on the FPGA prototype verification device comprises a unit to be tested, a conversion logic unit and a plurality of first pins, wherein the unit to be tested comprises a plurality of second pins, and the first pins and the second pins are connected with the conversion logic unit, and the test verification method is characterized by comprising the following steps:
burning a test file into the FPGA prototype verification device, wherein the test file comprises one or more test programs, at least part of the test programs comprise pin configuration instructions, and the pin configuration instructions comprise the connection relation between a first pin and a second pin under the test programs;
and executing each test program in the test file, wherein when executing one test program with a pin configuration instruction, the pin configuration instruction is executed firstly to configure the connection relation between a first pin and a second pin under the test program, and then the rest programs in the test program are executed to carry out test verification.
2. The test verification method of claim 1, wherein,
the pin configuration instructions are written in the C language.
3. The test verification method of claim 1, wherein the pin configuration instruction includes a first pin field, a second pin field, and a bus address field, the bus address field being a predetermined address, the first pin field having a first pin number recorded therein, the second pin field having a second pin number recorded therein,
when the test program is executed, if the occurrence of a preset address on the bus is monitored, the conversion logic unit connects the first pin of the first pin number with the second pin of the second pin number.
4. The test verification method of claim 3, wherein,
the unit to be tested comprises a UART interface, the test program comprises a UART interface test program, and the UART interface test program comprises the pin configuration instruction; when the UART interface test program is executed, if a preset address appears on a bus is monitored, the conversion logic unit configures the connection relation between the first pin and the second pin under the UART interface test program according to the first pin field and the second pin field of the pin configuration instruction, so that the UART interface is led out of the FPGA prototype verification device through the proper first pin to communicate with external UART interface equipment, and then the rest program of the UART interface test program is executed to carry out the test verification of the UART interface.
5. The test verification method of claim 3, wherein,
the test program comprises a waveform export test program, the waveform export test program comprises the pin configuration instruction, when the waveform export test program is executed, if a preset address appears on a bus is monitored, the conversion logic unit configures the connection relation between a first pin and a second pin under the waveform export test program according to a first pin field and a second pin field of the pin configuration instruction, so that the unit to be tested is led out of the FPGA prototype verification device through a proper first pin to communicate with an external oscilloscope, and then the rest program of the waveform export test program is executed to carry out test verification of waveform export.
6. The test verification method of claim 3, wherein,
the test program comprises a clock test program, the clock test program comprises the pin configuration instruction, when the clock test program is executed, if a preset address appears on a bus is monitored, the conversion logic unit configures the connection relation between a first pin and a second pin under the clock test program according to a first pin field and a second pin field of the pin configuration instruction, so that the unit to be tested is led out of the FPGA prototype verification device through a proper first pin, and then the rest program of the clock test program is executed to perform clock test verification.
7. The utility model provides a FPGA prototype verification device, its includes unit to be tested, conversion logic unit and a plurality of first pin, the unit to be tested is including the second pin, first pin and second pin with conversion logic unit links to each other, its characterized in that includes:
burning a test file into the FPGA prototype verification device, wherein the test file comprises one or more test programs, at least part of the test programs comprise pin configuration instructions, and the pin configuration instructions comprise the connection relation between a first pin and a second pin under the test programs;
and executing each test program in the test file, wherein when executing one test program with a pin configuration instruction, the pin configuration instruction is executed firstly to configure the connection relation between a first pin and a second pin under the test program, and then the rest programs in the test program are executed to carry out test verification.
8. The FPGA prototype verification apparatus of claim 7,
the pin configuration instructions are written in the C language.
9. The test verification method of claim 7, wherein the pin configuration instruction includes a first pin field, a second pin field, and a bus address field, the bus address field being a predetermined address, the first pin field having a first pin number recorded therein, the second pin field having a second pin number recorded therein,
when the test program is executed, if the occurrence of a preset address on the bus is monitored, the conversion logic unit connects the first pin of the first pin number with the second pin of the second pin number.
10. The test verification method of claim 9, wherein,
the unit to be tested comprises a UART interface, the test program comprises a UART interface test program, and the UART interface test program comprises the pin configuration instruction; when executing the UART interface test program, if the predetermined address appears on the bus, the conversion logic unit configures the connection relation between the first pin and the second pin under the UART interface test program according to the first pin field and the second pin field of the pin configuration instruction, so that the UART interface is led out of the FPGA prototype verification device through the appropriate first pin to communicate with external UART interface equipment, then the rest program of the UART interface test program is executed to perform the test verification of the UART interface,
the test program comprises a waveform export test program, the waveform export test program comprises the pin configuration instruction, when the waveform export test program is executed, if a preset address appears on a bus is monitored, the conversion logic unit configures the connection relation between a first pin and a second pin under the waveform export test program according to a first pin field and a second pin field of the pin configuration instruction, so that the unit to be tested is exported to the FPGA prototype verification device through a proper first pin to communicate with an external oscilloscope, then the rest program of the waveform export test program is executed to carry out test verification of waveform export,
the test program comprises a clock test program, the clock test program comprises the pin configuration instruction, when the clock test program is executed, if a preset address appears on a bus is monitored, the conversion logic unit configures the connection relation between a first pin and a second pin under the clock test program according to a first pin field and a second pin field of the pin configuration instruction, so that the unit to be tested is led out of the FPGA prototype verification device through a proper first pin, and then the rest program of the clock test program is executed to perform clock test verification.
CN202310305776.3A 2022-12-30 2023-03-24 FPGA prototype verification device and test verification method thereof Pending CN116432572A (en)

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