CN116243147B

CN116243147B - PAD function matrix-based integrated control chip peripheral self-test method and device

Info

Publication number: CN116243147B
Application number: CN202310515108.3A
Authority: CN
Inventors: 蒋晓伟
Original assignee: Wuhan Xinbida Microelectronics Co ltd
Current assignee: Wuhan Xinbida Microelectronics Co ltd
Priority date: 2023-05-09
Filing date: 2023-05-09
Publication date: 2023-08-18
Anticipated expiration: 2043-05-09
Also published as: CN116243147A

Abstract

The invention discloses a PAD function matrix-based integrated control chip peripheral self-test method and device, wherein the method comprises the following steps: interconnecting the input and output of at least two peripheral devices to be tested with the PAD function matrix respectively to form a PAD loop; configuring a PAD data direction in the PAD loop; and executing the function test program and reading the test result. According to the invention, data distribution of the peripheral to be tested is completed through the PAD function matrix, different peripheral to be tested are interconnected through PAD, and the function test program is controlled through the internal host computer, so that self-test of the whole chip is completed. According to the invention, the self-test of the peripheral is realized through the PAD function matrix, so that the pattern of the PAD test is reduced, and the test cost and the test complexity are reduced. The invention tests based on functions, can test the whole chip from the angle of the chip function, visually see whether the whole function of the chip can normally run, and can be used as supplement to DFT test to cover the part which cannot be covered by the DFT test.

Description

PAD function matrix-based integrated control chip peripheral self-test method and device

Technical Field

The invention belongs to the field of semiconductor design and test, and particularly relates to a PAD function matrix-based integrated control chip peripheral self-test method and device.

Background

The large-scale integrated control chip is often provided with a plurality of peripherals and a plurality of pins, and a large number of pins and related functional tests are very tedious and time-consuming work. With the development of modern science and technology, the number of pins of chips is increased, and even more pins reach hundreds of pins, which brings great challenges to peripheral testing and pin testing.

The vehicle-mounted chip is more rigorous in testing than the ordinary chip. The existing vehicle-mounted chip testing method mainly uses a Design for Test (DFT) testing technology, and most of testing logic can be covered by DFT testing, but because of the method and the tool, the coverage rate cannot reach 100%, and some logic which cannot be covered by DFT (such as complex logic and function selection logic) needs to be covered by other modes, so as to meet the testing requirement of the vehicle-mounted chip. And, the DFT test is not based on the function to test, and whether the whole function of the chip can normally run cannot be intuitively seen.

Aiming at the current situation, most manufacturers adopt running programs or other modes at present, and the points which cannot be tested in DFT tests are covered through circuit function tests, and the method mainly comprises two modes of machine test and PCB test.

The machine test is mainly divided into two parts, wherein one part is the data interaction of the machine and is used for inputting and controlling excitation; one part is a data observation part, mainly a PAD (chip pin) outputs different level changes for testing whether the Test is normal, and the method is effective in a CP (Circuit Probing) stage and a FT (Final Test) stage, but the more the PAD is tested, the lower the Test efficiency is. For example, the CP test stage is now a probe test, and if one machine has 64 probes and one chip test requires 4 probes, one machine can only test 16 chips at a time. If the peripheral communication is required to be simulated in the peripheral test to observe the peripheral state so as to realize whether the test function is normal, the peripheral test also requires to increase a test port, for example, after the peripheral is increased, the number of test IOs is programmed 8, and then only 8 chips can be tested at a time by one machine, so that the test efficiency is seriously reduced.

Further, in the CP and FT testing stages, a developer is required to develop test incentives, and when the number of test PADs is too large, the test incentives become complex, the difficulty of developing test vectors increases, the risk of human errors increases, and the cost of test labor increases.

In addition, if the number of large integrated control chips PAD is large and all the devices are used to cover stimulus test, a large number of test patterns (time sequences) are required.

The PCB board test mainly uses a third party standard chip to communicate with a chip to be tested on the PCB, and uses a communication observation mode to judge whether the chip works normally as the machine test.

For large integrated control chips, PAD resources are very abundant, and a large number of peripheral circuits are required for testing the large integrated control chips, for example, one chip has 5 groups of I2 cs, so that each group of I2 cs needs additional wiring and pull-up resistors, and the design and testing complexity of the PCB are increased.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention provides a self-testing method and a self-testing device for an integrated control chip peripheral based on a PAD function matrix, which are used for solving at least one technical problem.

According to an aspect of the present disclosure, there is provided a PAD function matrix-based integrated control chip peripheral self-test method, the method including:

interconnecting the input and output of at least two peripheral devices to be tested with the PAD function matrix respectively to form a PAD loop;

configuring a PAD data direction in the PAD loop;

and executing the function test program and reading the test result.

According to the technical scheme, data distribution of the peripheral to be tested is completed through the PAD function matrix, different peripheral to be tested are interconnected through the PAD, and the function test program is controlled through the internal host computer, so that self-test of the whole chip is completed. According to the technical scheme, the self-test of the peripheral is realized through the PAD function matrix, so that the pattern of the PAD test is reduced, and the test cost and the test complexity are reduced.

The technical scheme is based on the function for testing, the whole chip can be tested from the angle of the chip function, whether the whole function of the chip can normally run or not can be visually seen, and the chip can be used as a supplement to the DFT test to cover the part which cannot be covered by the DFT test.

Furthermore, the technical scheme can complete the peripheral test of the integrated control chip by directly using the machine communication interface, is convenient to use in machine test and PCB test, and greatly saves the test difficulty of each link.

As a further technical scheme, the PAD functional matrix comprises a communication interconnection matrix, a PAD direction controller and a plurality of PADs, wherein the communication interconnection matrix is used for respectively interconnecting the input and output of different peripherals to be tested with the plurality of PADs, and the PAD direction controller is used for selecting a control mode of the input and output directions of PAD data and controlling the input and output directions of the PAD data under a manual control mode.

According to the technical scheme, the characteristics of the PAD are utilized, under the condition that PAD input enabling (IE signal) is enabled all the time, the output of the PAD can be looped back to the input of the PAD, the input and the output of the PAD are connected with two different peripheral modules, and the two modules connected with the PAD generate data interaction, so that the test of two peripheral devices is realized.

Further, the PAD direction controller mainly controls PAD pull-up, pull-down, output enabling and input enabling, and in a manual control mode, the PAD data input and output direction is controlled by controlling the PAD pull-up, pull-down, output enabling and input enabling.

Further, the PAD direction controller selects a control mode of the PAD data input/output direction, and different control modes can be freely combined according to different application scenes to meet the test requirements of different test scenes.

Alternatively, the control mode of the PAD data input-output direction is selected by reading the register configuration data.

As a further technical solution, configuring a PAD data direction in the PAD loop, further includes: the PAD data direction is configured to be an automatic control mode or a manual control mode. The automatic control mode and the manual control mode can be freely combined according to different application scenes, so that the test requirements of different test scenes are met.

As a further technical solution, the configuration of the automatic control mode includes: enabling a master peripheral function and a slave peripheral function to be tested for forming a PAD loop, setting a data direction corresponding to the master peripheral function as output, and setting a data direction corresponding to the slave peripheral function as input.

Optionally, for two to-be-tested peripherals, the function enabling of one to-be-tested peripheral is master, the function enabling of the other to-be-tested peripheral is slave, the to-be-tested peripheral data direction with the function of master is set as output, and the to-be-tested peripheral data direction with the function of slave is set as input.

As a further technical solution, the configuration of the manual control mode includes: the PAD direction controller manually controls the input and output directions of the PAD data. The input/output direction of the PAD data is controlled by controlling the PAD pull-up, pull-down, output enable and input enable.

As a further technical scheme, when the function test program is executed, the internal state register of the chip is read to judge whether the chip can normally operate.

As a further technical solution, the peripheral to be tested includes: SPI, I2C, UART, GPIO or PWM. When testing is carried out, different peripherals to be tested can complete PAD loop-back through different combinations, and the purpose of self-testing of the peripherals is achieved.

According to an aspect of the present disclosure, there is provided an integrated control chip peripheral self-test device based on PAD function matrix, including: the PAD functional matrix and at least two peripherals to be tested, wherein the input and the output of the at least two peripherals to be tested are respectively interconnected with the PAD functional matrix to form a PAD loop; the PAD function matrix comprises a communication interconnection matrix and a plurality of PADs, wherein the communication interconnection matrix is used for respectively interconnecting the input and the output of different peripherals to be tested with the plurality of PADs.

The device provided by the technical scheme can be applied to machine test and PCB test, realizes data interconnection between the peripherals to be tested through the PAD function matrix, can complete integrated control chip peripheral test by directly using the machine communication interface, and achieves the purposes of reducing machine test and PCB test cost and test complexity by reducing test PAD.

As a further technical scheme, the PAD functional matrix further includes a PAD direction controller, configured to select a control mode of a PAD data input/output direction, and control the PAD data input/output direction in a manual control mode. The PAD direction controller selects the control mode of the PAD data input and output directions, and different control modes can be freely combined according to different application scenes, so that the test requirements of different test scenes are met.

Compared with the prior art, the invention has the beneficial effects that:

(1) The invention reduces the cost and complexity of the machine test and the PCB test in the peripheral test by reducing the test PAD, and can complete the peripheral test of the integrated control chip by directly using the machine communication interface, thereby greatly saving the test time.

(2) The invention reduces the testing circuit and the PCB wiring in the PCB board, thereby achieving the purpose of saving the cost.

(3) When the chip is started, the self-test scheme can be used as a chip self-test method to detect the integrity of the peripheral functions of the chip.

Drawings

Fig. 1 is a schematic diagram of the PAD principle according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a PAD function matrix according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a self-test system according to an embodiment of the invention.

Fig. 4 is a schematic diagram of SPI self-test according to an embodiment of the invention.

Detailed Description

The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.

In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

The invention provides a method for realizing self-test of the peripheral of a vehicle-gauge integrated control chip by using a PAD function matrix, which is based on the function test, can test the part which cannot be covered by a logic test in DFT, can be used as a supplement outside the DFT test, and can test the whole chip from the aspect of the chip function due to the use of a self-test mode.

The invention starts from reducing the complexity and the test cost of machine test and PCB test in peripheral test by reducing test PAD. The invention can complete the peripheral test of the integrated control chip by directly using the machine communication interface, has certain convenience in the machine test and the PCB test, and greatly saves the test difficulty of each link.

Because the PAD is an important part of the input and output of the chip, the input and output of the PAD can be controlled by controlling the signals on the PAD, so that the invention utilizes the characteristic of the PAD, under the condition that the input enable (IE signal) of the PAD is always enabled, the output of the PAD can be looped back to the input of the PAD, the input and the output of the PAD are connected with two different peripheral modules, and the two modules connected with the PAD generate data interaction.

The PAD principle is shown in fig. 1, where the signal descriptions are shown in table 1. Input Driver in fig. 1 represents an Input buffer unit, output Driver represents an Output buffer unit, and Pull logic represents a Pull-up and Pull-down logic unit.

Table 1 PAD signal specification table

Nouns (noun)	Direction	Description of the invention
			DOUT	Input device	Output data from chip cores
OE	Input device	Output enable
			PU	Input device	Pull-up resistor enable
PD	Input device	Pull-down resistor enable
			DIN	Output of	Data from PAD to inside of chip
IE	Input device	Input enabling
			PAD	Input/output	PAD connects external chip

Based on the PAD principle, the invention constructs a PAD functional matrix which comprises at least two peripheral devices to be tested to form a PAD loop, thereby meeting the self-test condition.

As shown in fig. 2, the PAD function matrix includes a communication interconnect matrix, PAD, and PAD directional controller (PAD-ctrl). The communication interconnection matrix is connected with the input and output of the peripheral equipment.

Specifically, pad_ctrl logic mainly controls Pad pull-up, pull-down, output enable, and input enable. The pad_ctrl can control whether the PAD output is controlled by the peripheral equipment automatically or manually, and different control modes can be freely combined according to different application scenes so as to meet different test scenes. By way of example only, in the case of two I2C communication tests, the two I2C directions may be selected to be controlled automatically by the I2C or the PAD via a register.

Further, in the manual control mode, the PAD direction controller controls the PAD input/output direction. In the automatic control mode, the related peripheral equipment is mutually complemented with the automatic mode and the manual mode through a protocol and the input and output directions of the PAD to be controlled.

Taking the automatic control mode of the SPI as an example, as shown in fig. 4, the SPI may be configured as slave or master, and when configured as slave, for example, SPI1, its spi_cs, spi_clk, and spi_si signals are required as inputs in the protocol, the spi_so protocol is required as an output, and the PAD direction is switched according to the mode set by the SPI. Similarly, when the SPI is set to the master, such as SPI0, the SPI signal line is opposite to the input/output direction of the slave signal line. It should be noted that, the master may be understood as a peripheral configured as a master in the enabling relationship, and the slave may be understood as a peripheral configured as a slave in the enabling relationship.

The peripheral devices in fig. 2 include PADs to be tested, such as GPIO (General Purpose Input/Output, universal input/Output module), PWM (Pulse Width Modulation ), SPI (Serial Peripheral Interface, serial peripheral interface), UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter), I2C (Inter-Integrated Circuit, integrated circuit bus), and the like.

The peripheral can complete PAD loop through different combinations, for example, internal signal loop such as I2C0, I2C1, I2C0, GPIO, PWM and the like can be formed, and the purpose of self-testing of the peripheral is achieved. It should be noted that, at least two sets of peripherals to be tested are needed in the present invention so as to complete signal connection.

The communication interconnection matrix is mainly connected with the input and the output of two peripheral modules, and signals of one peripheral module are output to the other peripheral module to serve as input.

As shown in fig. 3, the self-test system constructed by using the PAD function matrix includes: PAD function matrix, to-be-tested peripheral equipment, (Bus martix) and host Master. It should be noted that, the PAD function matrix here includes a plurality of PADs, and other structures are the same as the PAD function matrix including a single PAD.

The host Master is a host for controlling the whole peripheral, and may use a CPU, but not limited thereto. When testing, the CPU or other host master controls different peripheral devices such as I2C, SPI, PWM, UART, GPIO and the like, controls the input and output of the peripheral devices through different programs, and the PAD function matrix controls the input and output directions of PAD data.

The bus matrix in fig. 3 is a matrix structure controlling the entire peripheral device for communication between the chip peripheral device and the host.

The self-test system utilizes the PAD function matrix to connect all the functions of the peripheral equipment together, and a plurality of PADs form the functions required by the whole PAD test. By way of illustration only, SPI requires 4 PADs to make up two sets of SPI self-tests, I2C requires two PADs to complete GPIO module simulation I2C protocol and GPIO module communication, etc.

As an implementation manner, two SPI peripheral devices to be tested are taken as an example, and the self-testing method of the integrated control chip peripheral device based on the PAD function matrix is described, as shown in fig. 4, specifically:

step 1, the input and output of each peripheral are all connected to a PAD function matrix, and the PAD function matrix can control the input and output directions of PAD data in a program control mode or in a peripheral control mode.

Take SPI in automatic control mode as an example: the SPI can be configured into a slave and a master, when the SPI is configured into the slave, SPI_CS, SPI_CLK and SPI_SI signals are required to be input in a protocol, SPI_SO protocol is required to be output, the PAD direction can be switched according to the mode set by the SPI, when the SPI is set into the master, the SPI signal line is opposite to the input and output directions of the slave signal line, the SDA signal line in the IIC protocol is also used as input and output, and the PAD direction can be controlled by the peripheral according to the peripheral data format and the protocol requirement.

And 2, enabling different peripheral functions, wherein one is used as a master, the other is used as a slave, the peripheral function is used as a master data direction and is set as output, and the slave data direction is set as input.

In the figure: the solid line is SPI0 is master, SPI is slave output, the dotted line is SPI0 is master, and SPI is slave input.

And 3, after the data path and the direction are configured, the SPI function test can be completed through the program. SPI0 may also be replaced with GPIO, so that GPIO analog SPI protocol may be used to communicate with SPI 1.

Specifically, GPIO is generally available in the integrated control chip and is a relatively flexible peripheral, the function of testing the peripheral of the chip can be achieved through the GPIO analog I2C, SPI, UART protocol, and the PAD state can be obtained through the GPIO and square waves with different frequencies can be generated for PWM capturing.

And step 4, reading a state register in the chip to judge whether the chip can normally operate.

It should be noted that the foregoing steps are merely illustrative of the flow and principles of the testing method of the present invention, and are not limited to specific steps. The method can also be used for completing the self-test function of peripheral equipment such as I2C, PWM, UART, SPI, GPIO.

Further, the method of the present invention is not limited to the listed peripherals. All peripheral devices in the peripheral test theory can be tested by the method.

The invention also provides an integrated control chip peripheral self-test device based on the PAD function matrix, which comprises: the PAD functional matrix and at least two peripherals to be tested, wherein the input and the output of the at least two peripherals to be tested are respectively interconnected with the PAD functional matrix to form a PAD loop; the PAD function matrix comprises a communication interconnection matrix and a plurality of PADs, wherein the communication interconnection matrix is used for respectively interconnecting the input and the output of different peripherals to be tested with the plurality of PADs.

The test device utilizes the characteristics of the PAD, and under the condition that the PAD input enable (IE signal) is enabled all the time, the output of the PAD can be looped back to the input of the PAD, the input and the output of the PAD are connected with two different peripheral modules, and the two modules connected with the PAD generate data interaction.

The PAD functional matrix constructed based on the PAD principle comprises at least two peripheral devices to be tested so as to form a PAD loop and meet the self-test condition.

The PAD function matrix also comprises a PAD direction controller, which is used for selecting a control mode of the input and output directions of the PAD data and controlling the input and output directions of the PAD data in a manual control mode. The PAD direction controller selects the control mode of the PAD data input and output directions, and different control modes can be freely combined according to different application scenes, so that the test requirements of different test scenes are met.

It should be noted that the device of the present invention can be used to implement the foregoing test method. The embodiments covered by the above test method are equally applicable to the test device.

As a further aspect, in the description herein, reference to the terms "one embodiment," "certain embodiments," "an exemplary embodiment," "an example," "a particular example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced with equivalents; these modifications or substitutions do not depart from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.

Claims

1. The method is characterized in that the method utilizes the characteristics of PAD, connects the input and output of the PAD with two different peripheral modules inside the chip, and enables the two peripheral modules connected with the PAD to generate data interaction so as to realize the self-test of the two peripheral modules inside the chip;

the method comprises the following steps:

interconnecting the input and output of at least two peripheral devices to be tested with the PAD function matrix respectively to form a PAD loop; the PAD function matrix comprises a communication interconnection matrix, a PAD direction controller and a plurality of PADs, wherein the communication interconnection matrix is used for respectively interconnecting the input and output of different peripherals to be tested with the plurality of PADs, and the PAD direction controller is used for selecting a control mode of the input and output directions of PAD data and controlling the input and output directions of the PAD data;

configuring a PAD data direction in the PAD loop;

and executing the function test program and reading the test result.

2. The PAD function matrix-based integrated control chip peripheral self-test method of claim 1, wherein configuring PAD data direction within the PAD loop further comprises: the PAD data direction is configured to be an automatic control mode or a manual control mode.

3. The PAD function matrix-based integrated control chip peripheral self-test method according to claim 2, wherein the configuration of the automatic control mode comprises: enabling a master peripheral function and a slave peripheral function to be tested for forming a PAD loop, setting a data direction corresponding to the master peripheral function as output, and setting a data direction corresponding to the slave peripheral function as input.

4. The PAD function matrix based integrated control chip peripheral self-test method of claim 1, wherein the internal state register of the chip is read to determine whether the chip can operate normally when the function test program is executed.

5. The PAD function matrix-based integrated control chip peripheral self-test method as claimed in claim 1, wherein the peripheral to be tested comprises: SPI, I2C, UART, GPIO or PWM.

6. The integrated control chip peripheral self-test device based on the PAD function matrix is characterized in that the device utilizes the characteristics of the PAD to connect the input and output of the PAD with two different peripheral modules inside the chip, and the two peripheral modules connected with the PAD generate data interaction to realize the self-test of the two peripheral modules inside the chip; the device comprises: the PAD functional matrix and at least two peripherals to be tested, wherein the input and the output of the at least two peripherals to be tested are respectively interconnected with the PAD functional matrix to form a PAD loop; the PAD function matrix comprises a communication interconnection matrix, a PAD direction controller and a plurality of PADs, wherein the communication interconnection matrix is used for respectively interconnecting the input and output of different peripherals to be tested with the plurality of PADs, and the PAD direction controller is used for selecting a control mode of the input and output directions of PAD data and controlling the input and output directions of the PAD data.