CN116431518A - Multi-level and multi-mode software fault injection method based on simulation platform - Google Patents
Multi-level and multi-mode software fault injection method based on simulation platform Download PDFInfo
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Abstract
The invention relates to a multi-level and multi-mode software fault injection method based on a simulation platform, belonging to the field of embedded software testing. The invention achieves the effect of fault injection by modifying the simulation platform, and the simulation platform has the characteristics of strong controllability, flexible fault injection and high precision. Firstly, realizing the construction of a simulation platform by adopting a virtualization technology, wherein the simulation platform comprises a processor, a peripheral, a bus and other models; secondly, constructing a fault injection case library, wherein the fault injection case library comprises a processor platform level, an interface equipment level, a communication protocol level and other levels, and uniformly designing and managing fault cases; then, configuring fault injection parameters, and executing fault injection, wherein the fault injection comprises injection modes based on time, PC, address and the like; and finally, collecting the execution information after fault case injection, and generating a code coverage rate report. The invention improves the test sufficiency of the embedded software and ensures the quality and reliability of the software.
Description
Technical Field
The invention belongs to the field of embedded software testing, and particularly relates to a multi-level and multi-mode software fault injection method based on a simulation platform.
Background
Along with the wide application of the embedded system in the key fields of aviation, aerospace and the like, the embedded software is increasingly large in scale, the requirements on reliability and stability are increasingly increased, and the problem of software quality becomes a non-negligible problem. Compared with general software, the embedded software has the characteristics of difficulty in acquiring and positioning hardware errors, difficulty in fault reproduction and incomplete coverage of abnormal boundaries due to the fact that the running environment of the embedded software has the specificity and the specialization, and an effective quality assessment means is lacked. In practical engineering application, because of worry about hardware damage, it is difficult to perform fault injection on a real target system, in order to ensure the sufficiency of test verification of embedded software, a dynamic test environment is usually built by adopting a semi-physical object and a physical object, and fault simulation of external data of an interface is realized by means of plug-in mounting and the like, but faults of a bottom hardware system processor and a device layer are difficult to simulate, and the test sufficiency needs to be further improved.
With the continuous improvement of the structural complexity of the target system, the limitation of the fault injection method based on hardware implementation is gradually exposed, the problems of high cost, long period, irreversible faults and the like exist in the dynamic test environment constructed based on the real target machine, the fault simulation is difficult, the abnormal boundary cannot be covered, and the quality and the reliability of software cannot be effectively ensured.
The invention provides a multi-level and multi-mode software fault injection method based on a simulation platform for reducing the development and test cost of embedded software and improving the test sufficiency. The method is characterized in that a simulation platform is built by performing functional simulation on modules such as a processor and a peripheral device based on a virtualization technology, multi-level fault injection of an equipment interface level, a processor platform level and a communication protocol level is realized, abnormal boundary condition coverage is realized, fault information is acquired by monitoring the running state of software, and the quality and reliability of embedded software are ensured.
Disclosure of Invention
First, the technical problem to be solved
The invention aims to solve the technical problem of how to provide a multi-level and multi-mode software fault injection method based on a simulation platform so as to solve the problems that the quality of key software cannot be effectively ensured due to insufficient fault injection means, difficult fault information acquisition and insufficient test verification in the current embedded software test process.
(II) technical scheme
In order to solve the technical problems, the invention provides a multi-level and multi-mode software fault injection method based on a simulation platform, which comprises the following steps:
first step, constructing an embedded software simulation platform
Constructing a simulation platform by adopting a virtualization technology, realizing a processor platform simulation model, an interface device simulation model and a communication protocol simulation model, describing the association between the simulation models according to the composition relation of a hardware operation environment, and operating the tested embedded software;
second step, creating a typical fault case base
Establishing a fault model according to fault attributes and fault distribution, and uniformly managing the fault model to form a fault case library; wherein the fault attributes include: fault type, injection location, fault distribution identifies conditions under which the fault model occurs, depending on fault attributes;
third step of editing fault execution script
Retrieving fault cases from a fault case library according to requirements, editing fault model information, configuring fault script parameters, and generating a fault execution script;
fourth step of performing multi-level, multi-mode fault injection
Executing fault injection according to the generated fault execution script, and executing fault injection of different levels according to the fault case injection position, wherein the fault injection comprises processor fault injection, interface equipment fault injection and communication protocol fault injection; performing fault injection of different modes according to different triggering modes, wherein the fault injection comprises time-based fault injection, PC-based fault injection and address-based fault injection;
fifth step, collecting fault data information
Monitoring the running process of the target program based on the simulation platform, marking fault execution conditions, and collecting the running state data of the target program, wherein the method comprises the following steps: processor context information, register information, memory information, program trace, exception record, and fault parameters;
sixth step result analysis and display
Analyzing and displaying the collected fault information, including: and triggering, executing and ending the information analysis of each stage of faults, judging the effectiveness of fault cases, analyzing the fault-tolerant mechanism and the program coverage rate of the tested software, and generating a report result through a custom template.
(III) beneficial effects
The invention provides a multi-level and multi-mode software fault injection method based on a simulation platform, which has the following characteristics:
1. the fault injection system is realized based on the simulation platform, so that the problems of difficult control, poor flexibility, easy damage of the system and the like of the hardware platform fault injection are solved, and the controllability and the flexibility are greatly improved.
2. The multi-level fault injection is supported, the multi-level fault injection of a processor platform, interface equipment, a communication protocol and the like is realized, the coverage range of the fault injection is improved, and the reliability of target software is greatly ensured.
3. The multi-mode fault injection is supported, the configurable fault injection mode is provided, the modes of time-based, PC-based, address-based and the like are supported, and the fault injection flexibility and efficiency are improved;
4. the design of the fault case library is supported, the fault model and the fault case description are provided, the standard fault case library management is supported, the dynamic update of the case library is supported, a rich model is provided for fault injection, and the fault injection work is strongly supported.
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FIG. 1 is a block diagram of a multi-level and multi-mode software fault injection method based on a simulation platform;
fig. 2 is a software fault injection flow chart.
Detailed Description
To make the objects, contents and advantages of the present invention more apparent, the following detailed description of the present invention will be given with reference to the accompanying drawings and examples.
The invention provides a multi-level and multi-mode software fault injection method based on a simulation platform, which mainly achieves the effect of fault injection by modifying the simulation platform. Firstly, realizing the construction of a simulation platform by adopting a virtualization technology, wherein the simulation platform comprises a processor, a peripheral, a bus and other models; secondly, constructing a fault injection case library, wherein the fault injection case library comprises a processor platform level, an interface equipment level, a communication protocol level and other levels, and uniformly designing and managing fault cases; then, configuring fault injection parameters, and executing fault injection, wherein the fault injection comprises injection modes based on time, PC, address and the like; and finally, collecting the execution information after fault case injection, and generating a code coverage rate report. The multi-level and multi-mode software fault injection method based on the simulation platform is simple and flexible in fault injection mode, comprehensive in fault injection level, rich in fault case types, capable of covering abnormal boundary conditions comprehensively, improving the testing sufficiency of embedded software and guaranteeing the quality and reliability of the software.
The invention aims to provide a multi-level and multi-mode software fault injection method based on a simulation platform, which solves the problems that the quality of key software cannot be effectively ensured due to insufficient fault injection means, difficult fault information acquisition and insufficient test verification in the current embedded software test process.
First step, constructing an embedded software simulation platform
And constructing a simulation platform by adopting a virtualization technology, realizing a processor platform simulation model, an interface device simulation model and a communication protocol simulation model, describing the association between the simulation models according to the composition relation of the hardware operation environment, and operating the tested embedded software.
Second step, creating a typical fault case base
And establishing a fault model according to the fault attribute and the fault distribution, and uniformly managing the fault model to form a fault case library. Wherein the fault attributes include fault type, injection location, fault distribution identifies conditions under which the fault model occurs, depending on the fault attributes.
Third step of editing fault execution script
Retrieving fault cases from a fault case library according to requirements, editing fault model information, configuring fault script parameters, and generating a fault execution script;
the fault model information includes: fault type attribute, fault location attribute, duration attribute, trigger mode attribute, and simulation platform attribute;
the fault type attribute comprises software faults, hardware faults and communication faults; fault location attributes include software, operating environment, processor, interface device, communication protocol; duration attributes include permanent, transient, intermittent; the triggering mode attribute comprises time-based, PC-based and address-based; the simulation platform attributes comprise processor parameters, peripheral parameters and protocol parameters.
Fourth step of performing multi-level, multi-mode fault injection
Using a fault injector, such as a generated fault execution script, executing fault injection, and executing fault injection of different levels according to fault case injection positions, wherein the fault injection comprises processor fault injection, interface equipment fault injection and communication protocol fault injection; different modes of fault injection are performed in different triggering modes, including time-based fault injection, PC-based fault injection, address-based fault injection.
Fifth step, collecting fault data information
Based on the simulation platform monitoring the running process of the target program, marking fault execution conditions, and collecting the running state data of the target program, wherein the running state data mainly comprise processor context information, register information, memory information, program tracks, abnormal records, fault parameters and the like.
Sixth step result analysis and display
Analyzing and displaying the collected fault information, including fault triggering, executing and ending each stage of information analysis, judging the effectiveness of a fault case, analyzing the fault tolerance mechanism and the program coverage rate of the tested software, and generating a report result through a custom template.
Example 1:
an embodiment of a multi-level, multi-mode software fault injection method based on a simulation platform comprises two parts of the simulation platform and a software fault injection system, as shown in fig. 1.
Firstly, modeling simulation of a processor platform, interface equipment and a communication protocol is realized by adopting a virtualization technology, a simulation platform is established, and software operation is supported; secondly, constructing a fault case library, designing a multi-level fault case, describing abnormal boundary conditions and constructing fault data; then, performing multi-level, multi-mode fault injection using the fault injector; finally, collecting fault data for analysis and displaying the result.
The specific implementation steps are as follows:
first step, constructing an embedded software simulation platform
The embedded software simulation platform simulates the functions of the hardware running environment, adopts a virtualization technology to realize the functions of the processor platform, the interface equipment and the communication protocol, and supports the simulation running of the embedded software.
(1) And simulating the processor platform, namely finishing the processor architecture simulation according to a processor instruction manual, designing and realizing the instruction set function simulation architecture according to instruction fetching, decoding and executing stages, and performing on-chip equipment, register and memory space simulation to generate a processor platform simulation model.
(2) The simulation interface device is used for completing the function simulation of the interface device according to the manual, and mainly comprises an input interface, an output interface and a register function of the interface device to generate an interface device simulation model.
(3) And simulating the communication protocol, modeling the application layer communication protocol, generating a communication protocol simulation model which comprises a data frame, a command frame and the like, simulating byte types, integer types, semi-integer types, long integer types, data bits and the like, and assembling according to the communication protocol to form a frame head, frame data and a frame tail.
Step two, generating a fault case library
And creating a fault case library, building a fault model according to fault attributes and fault distribution, storing fault information by using a structured file, extracting fault model keyword information, and uniformly managing the fault case library.
S21, describing a fault model. And carrying out fault model description according to the test requirements, wherein the fault model description comprises fault attributes and fault distribution. The fault attribute comprises information such as fault type, fault occurrence position and the like; the fault distribution identifies conditions under which the fault model occurs, such as uniform distribution, exponential distribution, normal distribution, etc.
S22, storing a fault model. And (3) carrying out structural storage on fault model information by adopting a JSON data format, wherein a fault library= { fault model 1, fault model 2 and fault model 3}, fault model= { fault attribute, fault distribution }, fault attribute= { fault type, fault occurrence position }, fault distribution = { uniform distribution/exponential distribution/normal distribution }, fault type = { transient fault, intermittent fault, permanent fault }, fault occurrence position = { processor, interface equipment and communication protocol }.
S23, fault model management. And managing the fault models in the fault library, extracting keywords of the fault models, such as fault types, fault occurrence positions and fault distribution, searching the fault models through the keywords, acquiring the appointed fault models, and carrying out classified display on the fault models.
Third step of editing fault execution script
And retrieving fault cases from the fault case library according to requirements, editing fault model information, configuring fault script parameters, and generating a fault execution script.
S31, searching a fault case library according to the keywords, matching the fault cases and reading basic information of the fault model.
S32, editing fault model key information, including fault injection time T, fault injection position P and fault injection mode M.
S33, configuring a fault execution script, wherein the execution script is = { the number of faults N, fault case IDs { ID1, ID2, … }, fault injection time T { T1, T2, … }, fault injection positions P { P1, P2, … }, and fault injection modes M { M1, M2, … }.
Fourth step of performing multi-level, multi-mode fault injection
And executing fault injection according to the generated fault execution script, wherein the fault injection steps are as follows.
S41, initializing the simulation platform, and initializing the processor, the interface device and the communication protocol of the simulation platform to be in a normal state.
S42, analyzing the fault execution script, matching the fault case library, and retrieving the fault case according to the ID.
S43, acquiring an injection position P of a fault case, and matching a fault injection level, wherein the fault injection level comprises a processor, a register, a protocol and the like.
S44, acquiring an injection mode M of a fault case, and matching the fault injection mode, wherein the fault injection mode comprises time-based, address-based, PC-based and the like.
S45, running a script, and executing multi-mode and multi-level fault injection.
S46, judging whether fault injection is completed, executing step S47, and not executing step S42.
And S47, finishing fault injection.
Fifth step, collecting fault state data information
And after fault injection is executed, operating a simulation platform monitoring service, and collecting fault data information.
S51, searching a fault case according to the ID, and starting a simulation platform monitoring service.
S52, acquiring a fault injection mode M, and matching corresponding monitoring algorithms according to modes based on time, PC, address and the like.
S53, monitoring the fault position P of the simulation platform, judging whether the triggering condition of the fault injection mode is met, and collecting fault state information at the position P after triggering.
S54, monitoring the process of the target program, and collecting process state information.
And S55, outputting the state information in a log file mode.
Sixth step of fault result analysis
S61, checking the running state of the program after fault injection and recording fault results, wherein the common running results are as follows.
1) The program is normally executed, and fault injection has no influence on the program result.
2) And (5) ending the program operation, and making the program result incorrect.
3) The program runs out and falls into a dead loop.
4) And (3) running illegal instructions to cause the processor simulation kernel to stop working.
5) Accessing the illegal address space causes the emulation platform to crash.
S62, analyzing the influence of the fault case on the system according to the operation result, and guiding fault-tolerant design.
The key of the invention is as follows:
1. designing a fault case library:
the fault case library comprises the types of hardware running environment faults, software running environment faults, communication faults, software faults and the like. The hardware running environment faults comprise a processor, a memory, an interface, an interrupt/time sequence class and the like; the software running environment faults comprise operating system classes, supporting software classes and the like; the communication failure includes a bus class, an application protocol class, etc. Examples of fault models are shown in table 1.
TABLE 1 exemplary fault model tables
2. Multi-level, multi-mode fault injection
The fault injector supporting multi-level and multi-mode fault injection is realized, and fault level matching, fault mode matching, fault triggering, fault marking and other operations are performed after fault cases are received, wherein the fault injection modes are as follows.
(1) Time-based fault injection: the method can be divided into an immediate trigger and an application program operation after a designated time, and in this way, a user can inject various faults into any unprotected place of a target system.
(2) PC-based fault injection: the fault injection process is triggered when the target system executes some special instructions or branches, in this way, the user can change the running path of the target system, thereby checking the effectiveness of the fault tolerance mechanism of the target system.
(3) Address-based fault injection: when performing read-write operation to a certain memory cell and when performing data operation to certain specific address cells, faults are triggered.
And after the simulation platform is started, monitoring whether the target system program is running, if the target program is not running, exiting the system, and if the target program is running, recording the instruction step number of the current target program and the state information of the simulation system. Then, polling whether the target system has injected a fault currently, if so, continuing to execute the target program, acquiring the state information of the target system through a monitoring and information acquisition module, and finally, carrying out fault analysis and system evaluation through an analysis module; if no fault is injected, the target program runs in a single step, then different fault modes are selected according to user configuration, and when the triggering condition is met, fault injection operation is performed on the corresponding fault model and the injected fault is marked. For different fault modes, there are different fault injection methods, and the general fault injection flow is shown in fig. 2.
The multi-level and multi-mode software fault injection method based on the simulation platform has the following characteristics:
1. the fault injection system is realized based on the simulation platform, so that the problems of difficult control, poor flexibility, easy damage of the system and the like of the hardware platform fault injection are solved, and the controllability and the flexibility are greatly improved.
2. The multi-level fault injection is supported, the multi-level fault injection of a processor platform, interface equipment, a communication protocol and the like is realized, the coverage range of the fault injection is improved, and the reliability of target software is greatly ensured.
3. The multi-mode fault injection is supported, the configurable fault injection mode is provided, the modes of time-based, PC-based, address-based and the like are supported, and the fault injection flexibility and efficiency are improved;
4. the design of the fault case library is supported, the fault model and the fault case description are provided, the standard fault case library management is supported, the dynamic update of the case library is supported, a rich model is provided for fault injection, and the fault injection work is strongly supported.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (10)
1. The multi-level and multi-mode software fault injection method based on the simulation platform is characterized by comprising the following steps of:
first step, constructing an embedded software simulation platform
Constructing a simulation platform by adopting a virtualization technology, realizing a processor platform simulation model, an interface device simulation model and a communication protocol simulation model, describing the association between the simulation models according to the composition relation of a hardware operation environment, and operating the tested embedded software;
second step, creating a typical fault case base
Establishing a fault model according to fault attributes and fault distribution, and uniformly managing the fault model to form a fault case library; wherein the fault attributes include: fault type, injection location, fault distribution identifies conditions under which the fault model occurs, depending on fault attributes;
third step of editing fault execution script
Retrieving fault cases from a fault case library according to requirements, editing fault model information, configuring fault script parameters, and generating a fault execution script;
fourth step of performing multi-level, multi-mode fault injection
Executing fault injection according to the generated fault execution script, and executing fault injection of different levels according to the fault case injection position, wherein the fault injection comprises processor fault injection, interface equipment fault injection and communication protocol fault injection; performing fault injection of different modes according to different triggering modes, wherein the fault injection comprises time-based fault injection, PC-based fault injection and address-based fault injection;
fifth step, collecting fault data information
Monitoring the running process of the target program based on the simulation platform, marking fault execution conditions, and collecting the running state data of the target program, wherein the method comprises the following steps: processor context information, register information, memory information, program trace, exception record, and fault parameters;
sixth step result analysis and display
Analyzing and displaying the collected fault information, including: and triggering, executing and ending the information analysis of each stage of faults, judging the effectiveness of fault cases, analyzing the fault-tolerant mechanism and the program coverage rate of the tested software, and generating a report result through a custom template.
2. The simulation platform-based multi-level, multi-mode software fault injection method of claim 1, wherein the implementing the processor platform simulation model, the interface device simulation model, and the communication protocol simulation model in the first step specifically comprises:
the simulation processor platform is used for completing processor architecture simulation according to a processor instruction manual, realizing instruction set function simulation architecture according to instruction fetching, decoding and executing stage design, performing on-chip equipment, register and memory space simulation, and generating a processor platform simulation model;
the simulation interface device is used for completing the function simulation of the interface device according to the manual used by the device, and comprises an input interface, an output interface and a register function of the interface device, so as to generate an interface device simulation model;
modeling the application layer communication protocol to generate a communication protocol simulation model, comprising: data frame, command frame, analog byte, integer, semi-integer, long integer, data bit type, and frame header, frame data, frame tail are assembled according to communication protocol.
3. The simulation platform-based multi-level, multi-mode software fault injection method of claim 2, wherein the second step specifically comprises:
s21, describing a fault model: carrying out fault model description according to test requirements, wherein the fault model description comprises fault attributes and fault distribution; the fault attribute comprises fault type and fault occurrence position information; the fault distribution identifies conditions under which the fault model occurs;
s22, storing a fault model: the method comprises the steps of adopting a JSON data format to store fault model information in a structured mode, wherein a fault library= { fault model 1, fault model 2 and fault model 3}, fault model= { fault attribute, fault distribution }, fault attribute= { fault type, fault occurrence position }, fault distribution = { uniform distribution, exponential distribution, normal distribution }, fault type = { transient fault, intermittent fault, permanent fault }, fault occurrence position = { processor, interface equipment and communication protocol };
s23, fault model management: and managing the fault models in the fault library, extracting keywords of the fault models, searching the fault models through the keywords, acquiring the designated fault models, and carrying out classified display of the fault models.
4. The simulation platform-based multi-level, multi-mode software fault injection method of claim 3, wherein in the third step, fault model information comprises: fault type attribute, fault location attribute, duration attribute, trigger mode attribute, and simulation platform attribute; the fault type attribute comprises software faults, hardware faults and communication faults; fault location attributes include software, operating environment, processor, interface device, communication protocol; duration attributes include permanent, transient, intermittent; the triggering mode attribute comprises time-based, PC-based and address-based; the simulation platform attributes comprise processor parameters, peripheral parameters and protocol parameters.
5. The simulation platform-based multi-level, multi-mode software fault injection method of claim 3, wherein the third step specifically comprises:
s31, searching a fault case library according to the keywords, matching the fault cases and reading basic information of the fault model;
s32, editing fault model key information, including: fault injection time T, fault injection location P, fault injection mode M;
s33, configuring a fault execution script, wherein the execution script is = { the number of faults N, fault case IDs { ID1, ID2, … }, fault injection time T { T1, T2, … }, fault injection positions P { P1, P2, … }, and fault injection modes M { M1, M2, … }.
6. The simulation platform-based multi-level, multi-mode software fault injection method of claim 5, wherein the fourth step specifically comprises:
s41, initializing a simulation platform, and initializing the states of a processor, interface equipment and a communication protocol of the simulation platform into a normal state;
s42, analyzing a fault execution script, matching a fault case library, and retrieving fault cases according to the ID;
s43, acquiring an injection position P of a fault case, and matching a fault injection level, wherein the fault injection level comprises a processor, a register and a protocol;
s44, acquiring an injection mode M of a fault case, and matching the fault injection mode, wherein the method comprises the following steps: time-based, address-based, and PC-based;
s45, running a script, and executing multi-mode and multi-level fault injection;
s46, judging whether fault injection is completed, and executing step S47 and step S42 are not completed;
and S47, finishing fault injection.
7. The simulation platform-based multi-level, multi-mode software fault injection method of claim 6, wherein the fifth step specifically comprises:
s51, searching a fault case according to the ID, and starting a simulation platform monitoring service;
s52, acquiring a fault injection mode M, and matching corresponding monitoring algorithms according to time-based, PC-based and address-based modes;
s53, monitoring a fault position P of the simulation platform, judging whether a triggering condition of a fault injection mode is met, and collecting fault state information at the position P after triggering;
s54, monitoring a target program process and collecting process state information;
and S55, outputting the state information in a log file mode.
8. The simulation platform-based multi-level, multi-mode software fault injection method of claim 7, wherein the fault injection mode comprises:
time-based fault injection: the method is divided into an immediate triggering mode and an application program triggering mode after the operation of the application program is carried out for a designated time, and in this way, a user injects various faults into any unprotected place of a target system;
PC-based fault injection: triggering a fault injection process when the target system executes certain special instructions or branches, and in this way, a user changes the running path of the target system, so as to check the effectiveness of a fault tolerance mechanism of the target system;
address-based fault injection: triggering faults when performing read-write operation on a certain storage unit and performing data operation on certain specific address units;
after the simulation platform is started, monitoring whether the target system program is running, if the target program is not running, exiting the system, and if the target program is running, recording the instruction step number of the current target program and the state information of the simulation system; then, polling whether the target system has injected a fault currently, if so, continuing to execute the target program, acquiring the state information of the target system through a monitoring and information acquisition module, and finally, carrying out fault analysis and system evaluation through an analysis module; if no fault is injected, the target program runs in a single step, then different fault modes are selected according to user configuration, and when the triggering condition is met, fault injection operation is performed on the corresponding fault model and the injected fault is marked.
9. The simulation platform-based multi-level, multi-mode software fault injection method of claim 7, wherein the sixth step specifically comprises:
s61, checking the running state of the program after fault injection and recording a fault result;
s62, analyzing the influence of the fault case on the system according to the operation result, and guiding fault-tolerant design.
10. The simulation platform-based multi-level, multi-mode software fault injection method of claim 9, wherein the result in S61 is as follows:
the program is normally executed, and fault injection has no influence on the program result;
ending the program operation, and making the program result incorrect;
the program runs and falls into a dead loop;
operating illegal instructions to cause the processor simulation kernel to stop working;
accessing the illegal address space causes the emulation platform to crash.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7096322B1 (en) * | 2003-10-10 | 2006-08-22 | Unisys Corporation | Instruction processor write buffer emulation using embedded emulation control instructions |
| US20100218058A1 (en) * | 2009-02-25 | 2010-08-26 | Cisco Technology, Inc. | Fault injection |
| CN102354298A (en) * | 2011-07-27 | 2012-02-15 | 哈尔滨工业大学 | Software testing automation framework (STAF)-based fault injection automation testing platform and method for high-end fault-tolerant computer |
| CN102760098A (en) * | 2012-06-13 | 2012-10-31 | 北京航空航天大学 | Processor fault injection method oriented to BIT software test and simulator thereof |
| CN105446887A (en) * | 2016-01-11 | 2016-03-30 | 中国科学院光电研究院 | Satellite-borne embedded data communication fault dynamic injection system and method based on digital virtual technology |
| US20160334467A1 (en) * | 2015-05-14 | 2016-11-17 | Electronics And Telecommunications Research Institute | Method and apparatus for injecting fault and analyzing fault tolerance |
| CN107368408A (en) * | 2017-05-31 | 2017-11-21 | 中国船舶工业综合技术经济研究院 | A kind of software fault towards interface injects automated testing method |
| CN111813672A (en) * | 2020-07-03 | 2020-10-23 | 北京计算机技术及应用研究所 | Non-invasive coverage rate statistical method for various processor architectures |
| CN114676059A (en) * | 2022-03-30 | 2022-06-28 | 湖北航天技术研究院总体设计所 | Embedded software fault injection method and device |
-
2023
- 2023-04-26 CN CN202310461957.5A patent/CN116431518B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7096322B1 (en) * | 2003-10-10 | 2006-08-22 | Unisys Corporation | Instruction processor write buffer emulation using embedded emulation control instructions |
| US20100218058A1 (en) * | 2009-02-25 | 2010-08-26 | Cisco Technology, Inc. | Fault injection |
| CN102354298A (en) * | 2011-07-27 | 2012-02-15 | 哈尔滨工业大学 | Software testing automation framework (STAF)-based fault injection automation testing platform and method for high-end fault-tolerant computer |
| CN102760098A (en) * | 2012-06-13 | 2012-10-31 | 北京航空航天大学 | Processor fault injection method oriented to BIT software test and simulator thereof |
| US20160334467A1 (en) * | 2015-05-14 | 2016-11-17 | Electronics And Telecommunications Research Institute | Method and apparatus for injecting fault and analyzing fault tolerance |
| CN105446887A (en) * | 2016-01-11 | 2016-03-30 | 中国科学院光电研究院 | Satellite-borne embedded data communication fault dynamic injection system and method based on digital virtual technology |
| CN107368408A (en) * | 2017-05-31 | 2017-11-21 | 中国船舶工业综合技术经济研究院 | A kind of software fault towards interface injects automated testing method |
| CN111813672A (en) * | 2020-07-03 | 2020-10-23 | 北京计算机技术及应用研究所 | Non-invasive coverage rate statistical method for various processor architectures |
| CN114676059A (en) * | 2022-03-30 | 2022-06-28 | 湖北航天技术研究院总体设计所 | Embedded software fault injection method and device |
Non-Patent Citations (5)
| Title |
|---|
| 张建伟等: "嵌入式系统测试的发展", 单片机与嵌入式系统应用, no. 2011, pages 5 - 7 * |
| 徐应诗;刘斌;阮镰;: "基于故障注入的仿真测试方法过程框架", 测控技术, no. 10 * |
| 王华等: "基于故障注入的嵌入式测绘导航软件测试技术研究", 测绘技术学报, no. 2018, pages 31 - 35 * |
| 王金波;张涛;: "基于故障注入的嵌入式软件安全性测试框架及实现", 计算机应用研究, no. 08 * |
| 肖永健;刘永恒;徐军;: "一种嵌入式软件逻辑覆盖测试方法研究", 计算机测量与控制, no. 04 * |
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