CN116302379A - Microkernel architecture, scheduling method, microkernel system and storage medium - Google Patents

Microkernel architecture, scheduling method, microkernel system and storage medium Download PDF

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CN116302379A
CN116302379A CN202211093730.1A CN202211093730A CN116302379A CN 116302379 A CN116302379 A CN 116302379A CN 202211093730 A CN202211093730 A CN 202211093730A CN 116302379 A CN116302379 A CN 116302379A
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厉雷刚
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4831—Task transfer initiation or dispatching by interrupt, e.g. masked with variable priority
    • G06F9/4837—Task transfer initiation or dispatching by interrupt, e.g. masked with variable priority time dependent
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a microkernel architecture, a scheduling method, a microkernel system and a computer readable storage medium. The micro-kernel architecture includes: the scheduling module is used for calling the threads according to a preset ready priority queue, the ready state of the threads and the priority of the threads; the memory management module comprises a plurality of memory idle blocks with different sizes and is used for distributing and releasing the memory according to the call of the thread; the IPC module is used for setting endpoints for the threads and realizing communication among different threads according to the endpoints; the time tree module is used for setting timeout time nodes for different threads; and the interrupt mechanism module is used for processing a preset process, wherein the process comprises a plurality of threads. The invention reduces the coupling degree of the application and the system, reduces the system call interface and ensures that the microkernel can realize better maintenance.

Description

Microkernel architecture, scheduling method, microkernel system and storage medium
Technical Field
The present invention relates to the technical field of microkernel operating systems, and in particular, to a microkernel architecture, a scheduling method, a microkernel system, and a storage medium.
Background
Modern operating systems (OS Operating System) typically contain multiple processes or threads, between which there may be a need to contend for a shared resource, where in order to synchronize data consistency among the multiple processes or threads, there is often a need to lock access, or close interrupts before access. On the other hand, for a system supporting interrupts, the interrupt response function may compete with a Kernel (Kernel) or a common process or thread for sharing resources, and in this time, it is common practice to directly close interrupts to ensure exclusive access of the shared resources, so as to maintain data consistency.
Although the interrupt may achieve the purpose of exclusively accessing the shared resource, if a new interrupt with high priority is generated after the interrupt is closed, the system cannot respond to the new interrupt, and the interrupt must be opened by the software to respond to the interrupt, which increases the interrupt response time of the system, and the interrupt closing time may be uncertain, because it is determined by the application code, and for a real-time system, the increased response time and time length uncertainty are unacceptable. In addition, the OS typically maintains a plurality of queues, such as a ready queue, and a waiting queue of various kernel resources, where operations of the plurality of queues are complex, and the waiting queue is typically O (n) or O (log n) for guaranteeing priority, which also brings a certain uncertainty to the execution time.
The OS is typically based on a Tick interrupt as the beat of the system, pushing the flow of events as a basis for timing. Tick requires a relatively high frequency (e.g., 100/1000 HZ) to meet timing and scheduling requirements, but excessive Tick interrupts can degrade system performance and increase power consumption. FreeRTOS also provides a mode of tick but requires pre-computation of the time in low power mode, by the time the system is again awakened to continue execution, which is not well calculated or accuracy is difficult to guarantee.
The operation interfaces of most of the prior kernels are based on a series of system calls, which causes the application and the kernels to be coupled too tightly and even coupled with a specific version, and the system call interfaces are too many and difficult to maintain.
Disclosure of Invention
The invention mainly aims to provide a micro-kernel architecture, a scheduling method, a micro-kernel system and a storage medium, and aims to solve the problems that an operating system is too tightly coupled with a kernel, even coupled with a specific version, too many system call interfaces and difficult maintenance.
To achieve the above object, the present invention provides a microkernel architecture, including:
the scheduling module is used for calling the threads according to a preset ready priority queue, the ready state of the threads and the priority of the threads;
the memory management module comprises a plurality of memory idle blocks with different sizes and is used for distributing and releasing the memory according to the call of the thread;
the IPC module is used for setting endpoints for the threads and realizing communication among different threads according to the endpoints;
the time tree module is used for setting timeout time nodes for different threads;
and the interrupt mechanism module is used for processing a preset process, wherein the process comprises a plurality of threads.
Optionally, the scheduling module includes a first API interface and a second API interface, where the first API interface is configured to switch a state of the thread to a ready state, and the second API interface is configured to switch the state of the thread to a waiting state.
Optionally, the scheduling module further comprises a scheduling unit and an executing unit;
the scheduling unit is used for calling the first API interface and the second API interface to switch the ready state of the thread according to preset calling information of the thread;
the execution unit is used for executing the thread according to the ready state, the preset ready priority queue and the priority of the thread.
Optionally, the IPC module stores an IPC message passing mechanism, which is used for creating communication endpoints between threads with communication links in all threads, so as to realize point-to-point communication between the threads.
Optionally, an ordered linked list is arranged in the time tree module, and the ordered linked list is sequentially connected from small to large according to the timeout time of the thread.
Optionally, the size of the memory idle block is 2 n To 2 n+1 Wherein n > 0.
In order to achieve the above object, the present invention further provides a scheduling method, where the scheduling method is applied to the micro-kernel architecture, and the scheduling method includes the steps of:
acquiring a thread to be switched corresponding to a current thread in execution, and switching the state of the thread to be switched into a ready state;
adding the thread to be switched into a ready queue, and judging whether the thread to be switched is a thread to be scheduled or not according to a preset ready priority queue;
if yes, executing the thread to be scheduled;
if not, according to the thread with the highest next priority corresponding to the current thread in the preset ready priority queue.
Optionally, the step of acquiring the thread to be switched corresponding to the current thread in execution and switching the state of the thread to be switched to the ready state includes:
acquiring a thread to be switched corresponding to a current thread in execution, and acquiring the state of the thread to be switched;
and if the state is a sleep state, calling an API interface to modify the state of the thread to be switched into a ready state.
In addition, in order to achieve the above object, the present invention also provides a microkernel system, where the microkernel system includes a microkernel architecture, a memory, a processor, and a scheduler stored on the memory and capable of running on the processor, where the scheduler, when executed by the processor, implements the steps of the scheduling method as described above.
In addition, to achieve the above object, the present invention also provides a computer-readable storage medium having stored thereon a scheduler, which when executed by a processor, implements the steps of the scheduling method as described above.
The invention provides a microkernel architecture, a scheduling method, a microkernel system and a computer readable storage medium, wherein the microkernel architecture comprises: the scheduling module is used for calling the threads according to a preset ready priority queue, the ready state of the threads and the priority of the threads; the memory management module comprises a plurality of memory idle blocks with different sizes and is used for distributing and releasing the memory according to the call of the thread; an IPC (Inter-Process Communication ) module, configured to set endpoints for the threads, and implement communication between different threads according to the endpoints; the time tree module is used for setting timeout time nodes for different threads; and the interrupt mechanism module is used for processing a preset process, wherein the process comprises a plurality of threads. The scheduling method comprises the following steps: acquiring a thread to be switched corresponding to a current thread in execution, and switching the state of the thread to be switched into a ready state; adding the thread to be switched into a ready queue, and judging whether the thread to be switched is a thread to be scheduled or not according to a preset ready priority queue; if yes, executing the thread to be scheduled; if not, according to the thread with the highest next priority corresponding to the current thread in the preset ready priority queue. The invention can realize 0 forbidden interrupt in microkernel through the architecture and the method, can completely eliminate terminal operation and improve the instantaneity of thread switching; through the IPC module, the communication mechanism among the IPC processes is based on a message mechanism, and the time waiting for each other can be triggered by the message IPC between the processes to realize the scheduling. By the scheduling module, redundant waiting queues in the prior art are removed, and ready queues are reserved, so that the waiting queues do not need to be maintained, and the operation is simplified. Through the memory management module, the size of the queue of each idle block is not strictly the same size, but the memory blocks with different sizes, so that multiple memory block division operations can be avoided when a thread is called. By the method and the device, the coupling degree of the application and the system is reduced, and the system call interface is reduced, so that the microkernel can realize better maintenance.
Drawings
FIG. 1 is a schematic diagram of a micro-kernel system architecture of a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a framework of the microkernel architecture of the present invention;
FIG. 3 is a messaging diagram of an IPC module in the micro-kernel architecture of the present invention;
FIG. 4 is a schematic diagram of a time tree module in a micro-kernel architecture according to the present invention;
FIG. 5 is a flow chart of an embodiment of a scheduling method according to the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1, fig. 1 is a schematic hardware structure of a microkernel system according to various embodiments of the present invention. The microkernel system comprises a communication module 01, a memory 02, a processor 03 and other components. Those skilled in the art will appreciate that the microkernel system illustrated in fig. 1 may also include more or less components than illustrated, or may combine certain components, or may be a different arrangement of components. The processor 03 is connected to the memory 02 and the communication module 01, respectively, and a computer program is stored in the memory 02 and executed by the processor 03 at the same time.
The communication module 01 is connectable to an external device via a network. The communication module 01 can receive data sent by external equipment, and can also send data, instructions and information to the external equipment, wherein the external equipment can be electronic equipment such as a mobile phone, a tablet personal computer, a notebook computer, a desktop computer and the like.
The memory 02 is used for storing software programs and various data. The memory 02 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function, and the like; the storage data area may store data or information, etc. created according to the use of the microkernel system. In addition, memory 02 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device.
The processor 03, which is a control center of the microkernel system, connects various parts of the entire microkernel system using various interfaces and lines, performs various functions of the microkernel system and processes data by running or executing software programs and/or modules stored in the memory 02 and calling data stored in the memory 02, thereby performing overall monitoring of the microkernel system. The processor 03 may include one or more processing units; preferably, the processor 03 may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, an application program, etc., and the modem processor mainly processes wireless communication. It will be appreciated that the modem processor described above may not be integrated into the processor 03.
Although not shown in fig. 1, the microkernel system may further include a circuit control module, where the circuit control module is used to connect with a mains supply to implement power control and ensure normal operation of other components.
Those skilled in the art will appreciate that the microkernel system architecture illustrated in fig. 1 is not limiting of microkernel systems and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
Modern operating systems (OS Operating System) typically contain multiple processes or threads, between which there may be a need to contend for a shared resource, where in order to synchronize data consistency among the multiple processes or threads, there is often a need to lock access, or close interrupts before access. On the other hand, for a system supporting interrupts, the interrupt response function may compete with a Kernel (Kernel) or a common process or thread for sharing resources, and in this time, it is common practice to directly close interrupts to ensure exclusive access of the shared resources, so as to maintain data consistency.
Although the interrupt may achieve the purpose of exclusively accessing the shared resource, if a new interrupt with high priority is generated after the interrupt is closed, the system cannot respond to the new interrupt, and the interrupt must be opened by the software to respond to the interrupt, which increases the interrupt response time of the system, and the interrupt closing time may be uncertain, because it is determined by the application code, and for a real-time system, the increased response time and time length uncertainty are unacceptable. In addition, the OS typically maintains a plurality of queues, such as a ready queue, and a waiting queue of various kernel resources, where operations of the plurality of queues are complex, and the waiting queue is typically O (n) or O (log n) for guaranteeing priority, which also brings a certain uncertainty to the execution time.
The OS is typically based on a Tick interrupt as the beat of the system, pushing the flow of events as a basis for timing. Tick requires a relatively high frequency (e.g., 100/1000 HZ) to meet timing and scheduling requirements, but excessive Tick interrupts can degrade system performance and increase power consumption. FreeRTOS also provides a mode of tick but requires pre-computation of the time in low power mode, by the time the system is again awakened to continue execution, which is not well calculated or accuracy is difficult to guarantee.
The operation interfaces of most of the prior kernels are based on a series of system calls, which causes the application and the kernels to be coupled too tightly and even coupled with a specific version, and the system call interfaces are too many and difficult to maintain.
Referring to fig. 2, fig. 2 is a schematic diagram of a frame structure of a microkernel architecture according to the present invention, where the microkernel architecture includes a scheduling module, configured to call a thread according to a preset ready priority queue, a ready state of the thread, and a priority of the thread; the memory management module comprises a plurality of memory idle blocks with different sizes and is used for distributing and releasing the memory according to the call of the thread; the IPC module is used for setting endpoints for the threads and realizing communication among different threads according to the endpoints; the time tree module is used for setting timeout time nodes for different threads; and the interrupt mechanism module is used for processing a preset process, wherein the process comprises a plurality of threads.
Further, the IPC module stores an IPC message passing mechanism, which is used for creating communication endpoints between threads with communication links in all threads, so as to realize point-to-point communication between the threads.
Further, an ordered linked list is arranged in the time tree module, and the ordered linked list is sequentially connected from small to large according to the overtime of the thread.
Further, the size of the memory free block is 2 n To 2 n+1 Wherein n > 0.
In this embodiment, the preset ready priority queue includes a preset assigned priority for each thread, and when executing the threads, the preset ready priority queue is used to execute the threads sequentially according to the priority. The ready state is a state when each thread can execute, that is, the thread can be executed only when the thread is in the ready state, and the priority of the thread is the order of the threads in a preset ready priority queue. Specifically, when scheduling the thread, the thread needing to be currently executed wakes up the thread needing to be next executed, and judges whether the thread needing to be next executed is at the next priority of the thread needing to be currently executed in the ready priority queue, if not, the thread with the next priority is executed according to the ready priority queue; and if the thread needing to be executed next is in the next priority of the priority needing to be executed in the ready priority queue, directly executing the thread needing to be executed next. For example, when the thread a is executing and the thread to be executed next to the thread a is the thread B, sending a message to wake up the thread B by the thread a, further judging whether the next priority of the thread a in the ready priority queue is the thread B, if not, executing the thread of the next priority of the thread a in the ready priority queue, and adding the thread B into a preset ready priority queue; if the next priority is just thread B, then thread B is executed. By the scheduling module, the whole system has only one queue, namely the ready priority queue and no other waiting queues. The thread ready state is placed in the ready queue and the wait state is removed from the ready queue without placing any queues. And 0 interrupt in the microkernel architecture is realized, the operation complexity is reduced, and the real-time performance of the inter-thread switching is improved.
The size of the free memory block in the memory management module is 2 n To 2 n+1 In the two-way circulation list, n is greater than 0, and is specifically divided into a plurality of idle blocks of the n power of 2 memory, however, the memory blocks in each list are not necessarily of the same size, but are all idle blocks with the size between the n power of 2 and the n+1 power of 2, so that the dividing and merging operations of the idle blocks can be reduced when the memory is allocated and released.
Referring to fig. 3, fig. 3 is a message passing diagram in an IPC module, where an IPC message passing mechanism is stored in the IPC module, and is used to create communication endpoints between threads having communication links in all threads, so as to implement point-to-point communication between the threads. Specifically, IPC message communication does not exist among all threads, because of different business logic, different design modes and different communication models, it can be determined which threads have communication links according to the actual communication model, an endpoint of communication is created among the threads with communication links, the threads send messages through the endpoint, the state of the triggering thread changes, the scheduling execution sequence is affected, and the business field customized scheduling algorithm is realized. Before communication, two threads need to be connected first, an endpoint pair is generated, which is equivalent to point-to-point communication among multiple threads, each endpoint pair is a message queue pair formed by two ring-buf (circular buffer queue), and two threads can be disconnected after communication is finished, but for a hard real-time system, a communication model is not generally recommended to be changed, and when the system is initialized, the communication model is built, and the communication model is not changed halfway.
The time tree module is configured to set timeout time nodes for different threads, referring to fig. 4, fig. 4 is a schematic structural diagram of the time tree module, in which an ordered linked list is set, and the ordered linked list is sequentially connected from small to large according to the timeout time of the threads. And the overtime node is used for switching the thread into a waiting state according to the overtime if the thread has the corresponding overtime when the thread calls the yields. By means of the time tree module, the complexity of the thread entering the ready queue can be simplified.
The interrupt mechanism module is configured to process a preset process, where the process includes a plurality of threads, the preset process may be an urgent process, and other processes may wake up corresponding threads through an IPC communication mechanism. In addition, since the key operations of all the kernels are independently placed in one thread to be processed, no competition state can occur, the operations of all the kernels do not need to shut down the interrupt, the interrupt handler does not need to prohibit the interrupt, the threads are awakened through IPC communication, no interaction exists between the interrupts, and all the threads are communicated with one independent communication endpoint and mutually complementary conflicts, so that the interrupt is not required to be shut down, and the interrupt shutdown of 0 is realized.
Further, the scheduling module includes a first API interface for switching the state of the thread to a ready state, and a second API interface for switching the state of the thread to a waiting state.
Further, the scheduling module further comprises a scheduling unit and an executing unit;
the scheduling unit is used for calling the first API interface and the second API interface to switch the ready state of the thread according to preset calling information of the thread;
the execution unit is used for executing the thread according to the ready state, the preset ready priority queue and the priority of the thread.
In this embodiment, the preset call information is a call relationship between threads, for example, a call relationship exists between thread a and thread B, and thread B may be called by thread a.
Specifically, the first API interface is wakeup, the second API interface is yield, and the wakeup is used for processing that a thread enters a ready state, and when one thread is executed or after execution ends, the next thread can be awakened by an IPC communication mechanism to execute the above operation. And the yield is used for processing the waiting state of the thread, and if the thread does not receive wakeup information of wakeup in the process of waiting for wakeup of the next thread, the yield is called to enter the waiting state until wakeup information is received. For example, the thread a sends wakeup information to wake up the thread B, but when no wakeup information is received by the thread B, the thread B may call yield to make the thread B enter a waiting state, and not switch to a ready state until wakeup information is received.
The invention provides a microkernel architecture, a scheduling method, a microkernel system and a computer readable storage medium, wherein the microkernel architecture comprises: the scheduling module is used for calling the threads according to a preset ready priority queue, the ready state of the threads and the priority of the threads; the memory management module comprises a plurality of memory idle blocks with different sizes and is used for distributing and releasing the memory according to the call of the thread; an IPC (Inter-Process Communication ) module, configured to set endpoints for the threads, and implement communication between different threads according to the endpoints; the time tree module is used for setting timeout time nodes for different threads; and the interrupt mechanism module is used for processing a preset process, wherein the process comprises a plurality of threads. The scheduling method comprises the following steps: acquiring a thread to be switched corresponding to a current thread in execution, and switching the state of the thread to be switched into a ready state; adding the thread to be switched into a ready queue, and judging whether the thread to be switched is a thread to be scheduled or not according to a preset ready priority queue; if yes, executing the thread to be scheduled; if not, according to the thread with the highest next priority corresponding to the current thread in the preset ready priority queue. The invention can realize 0 forbidden interrupt in microkernel through the architecture and the method, can completely eliminate terminal operation and improve the instantaneity of thread switching; through the IPC module, the communication mechanism among the IPC processes is based on a message mechanism, and the time waiting for each other can be triggered by the message IPC between the processes to realize the scheduling. By the scheduling module, redundant waiting queues in the prior art are removed, and ready queues are reserved, so that the waiting queues do not need to be maintained, and the operation is simplified. Through the memory management module, the size of the queue of each idle block is not strictly the same size, but the memory blocks with different sizes, so that multiple memory block division operations can be avoided when a thread is called. By the method and the device, the coupling degree of the application and the system is reduced, and the system call interface is reduced, so that the microkernel can realize better maintenance.
According to the above hardware structure, various embodiments of the method of the present invention are presented.
Referring to fig. 5, in a first embodiment of the scheduling method of the present invention, the scheduling method includes the steps of:
step S10, acquiring a thread to be switched corresponding to a current thread in execution, and switching the state of the thread to be switched into a ready state;
step S20, adding the thread to be switched into a ready queue, and judging whether the thread to be switched is a thread to be scheduled according to a preset ready priority queue;
in an embodiment, the step S20 further includes:
step A21, acquiring a thread to be switched corresponding to a current thread in execution, and acquiring the state of the thread to be switched;
and step A22, if the state is a sleep state, calling an API interface to modify the state of the thread to be switched into a ready state.
Step S30, if yes, executing the thread to be scheduled;
step S40, if not, according to the thread with the highest next priority corresponding to the current thread in the preset ready priority queue.
In this embodiment, the thread to be switched is the thread corresponding to the current thread and to be called next; the current thread is the executing thread; and the thread to be scheduled is the thread with the highest next priority corresponding to the current process in a preset ready queue. For example, when the thread a is executing and the thread to be executed next to the thread a is the thread B, sending a message to wake up the thread B by the thread a, further judging whether the next priority of the thread a in the ready priority queue is the thread B, if not, executing the thread of the next priority of the thread a in the ready priority queue, and adding the thread B into a preset ready priority queue, so that the thread B can be called according to the priority subsequently; if the next priority is just thread B, thread B is directly executed.
By the method, the whole system has only one queue, namely the ready priority queue and no other waiting queues. The thread ready state is placed in the ready queue and the wait state is removed from the ready queue without placing any queues. And 0 interrupt in the microkernel architecture is realized, the operation complexity is reduced, and the real-time performance of the inter-thread switching is improved.
In addition, an embodiment of the present invention also proposes a computer-readable storage medium, on which a scheduler is stored, which when executed by a processor, implements the following operations:
acquiring a thread to be switched corresponding to a current thread in execution, and switching the state of the thread to be switched into a ready state;
adding the thread to be switched into a ready queue, and judging whether the thread to be switched is a thread to be scheduled or not according to a preset ready priority queue;
if yes, executing the thread to be scheduled;
if not, according to the thread with the highest next priority corresponding to the current thread in the preset ready priority queue.
Further, the blockchain-based scheduler, when executed by the processor, also performs the following operations:
acquiring a thread to be switched corresponding to a current thread in execution, and acquiring the state of the thread to be switched;
and if the state is a sleep state, calling an API interface to modify the state of the thread to be switched into a ready state.
Embodiments of the computer readable storage medium of the present invention are substantially the same as the above-described embodiments of the blockchain-based scheduler, and are not described herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) as described above, comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims (10)

1. A micro-kernel architecture, wherein the micro-kernel architecture comprises:
the scheduling module is used for calling the threads according to a preset ready priority queue, the ready state of the threads and the priority of the threads;
the memory management module comprises a plurality of memory idle blocks with different sizes, wherein the memory idle blocks are used for distributing and releasing the memory according to the call of the thread;
the IPC module is used for setting endpoints for the threads and carrying out communication among different threads according to the endpoints;
the time tree module is used for setting timeout time nodes for different threads;
and the interrupt mechanism module is used for processing a preset process, wherein the process comprises a plurality of threads.
2. The micro-kernel architecture of claim 1, wherein the scheduling module comprises a first API interface for switching the state of the thread to a ready state and a second API interface for switching the state of the thread to a wait state.
3. The micro-kernel architecture of claim 2, wherein the scheduling module further comprises a scheduling unit and an execution unit;
the scheduling unit is used for calling the first API interface and the second API interface to switch the state of the thread according to preset calling information of the thread;
the execution unit is used for executing the thread according to the ready state of the thread, the preset ready priority queue and the priority of the thread.
4. The micro-kernel architecture of claim 3, wherein the IPC module has stored therein an IPC messaging mechanism for creating communication endpoints between threads having communication links among all threads to enable point-to-point communication between the threads.
5. The micro-kernel architecture of claim 4, wherein an ordered linked list is provided in the time tree module, and the ordered linked list is sequentially connected from small to large according to a timeout time of the thread.
6. The micro-kernel architecture of claim 5, wherein the size of the memory free block is at 2 n To 2 n+1 Wherein n > 0.
7. A scheduling method, characterized in that the scheduling method is applied to the micro-kernel architecture of any one of claims 1 to 6, the scheduling method comprising the steps of:
acquiring a thread to be switched corresponding to a current thread in execution, and switching the state of the thread to be switched into a ready state;
adding the thread to be switched into a ready queue, and judging whether the thread to be switched is a thread to be scheduled or not according to a preset ready priority queue;
if yes, executing the thread to be scheduled;
if not, according to the thread with the highest next priority corresponding to the current thread in the preset ready priority queue.
8. The scheduling method of claim 7, wherein the step of acquiring the thread to be switched corresponding to the current thread in execution and switching the state of the thread to be switched to the ready state comprises:
acquiring a thread to be switched corresponding to a current thread in execution, and acquiring the state of the thread to be switched;
and if the state is a sleep state, calling a first API interface to modify the state of the thread to be switched into a ready state.
9. A microkernel system comprising a microkernel architecture and a memory, a processor and a scheduler stored on the memory and executable on the processor, which when executed by the processor implements the steps of the scheduling method of any of claims 7 to 8.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a scheduler, which when executed by a processor, implements the steps of the scheduling method according to any of claims 7 to 8.
CN202211093730.1A 2022-09-07 2022-09-07 Microkernel architecture, scheduling method, microkernel system and storage medium Pending CN116302379A (en)

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