CN116033539A - Base station GNSS clock synchronization method and system based on EPLD - Google Patents

Base station GNSS clock synchronization method and system based on EPLD Download PDF

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CN116033539A
CN116033539A CN202211130831.1A CN202211130831A CN116033539A CN 116033539 A CN116033539 A CN 116033539A CN 202211130831 A CN202211130831 A CN 202211130831A CN 116033539 A CN116033539 A CN 116033539A
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epld
module
pp1s
ocxo
clock
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赵前程
赵鑫鑫
姜凯
胡雷钧
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Shandong Inspur Science Research Institute Co Ltd
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Shandong Inspur Science Research Institute Co Ltd
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Priority to CN202211130831.1A priority Critical patent/CN116033539A/en
Priority to PCT/CN2023/082115 priority patent/WO2024055547A1/en
Publication of CN116033539A publication Critical patent/CN116033539A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention discloses a base station GNSS clock synchronization method and system based on an EPLD, and relates to the technical field of signal synchronization; aiming at the defects of GPS deviation, phase difference oscillation and the like of a GNSS clock on a base station, the GNSS clock synchronization system is improved, an EPLD with lower cost is adopted as a phase discriminator and a frequency divider, a CPU, a DAC and an OCXO chip form a large phase-locked loop, a small phase-locked loop is not nested in the large phase-locked loop, the phase-locked loop oscillation cannot be caused, the PP1S of the EPLD phase discriminator is a single pulse signal of the OCXO PP1S, the single pulse signal is introduced into an SSC synchronous code stream module, the clock deviation caused by external interference is eliminated regularly, the GPS deviation problem is solved, and the GNSS clock synchronization of the base station also combines the long stability characteristic of GNSS and the short stability characteristic of OCXO, so that a stable and reliable clock source is provided for the whole base station equipment.

Description

Base station GNSS clock synchronization method and system based on EPLD
Technical Field
The invention discloses a method and a system, relates to the technical field of signal synchronization, and in particular relates to a base station GNSS clock synchronization method and a system based on an EPLD.
Background
In the TDD system, different time slots are used for realizing the uplink and downlink common frequency of the air interface signal, so the TDD system is a strong self-interference system, and if clocks of different base stations are not synchronous, the deviation is larger than 1.5us, and the base stations have the problem of mutual interference. The way to guarantee air interface synchronization is to use a GNSS synchronization scheme. However, the existing GNSS clock synchronization system may have the defects of GPS deviation, phase difference oscillation and the like. The defects of GPS deviation, phase difference concussion and the like form nightmares of the outfield base station, and operation and maintenance teams in various places face great pressure.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides the base station GNSS clock synchronization method and system based on the EPLD, which have the characteristics of strong universality, simple and convenient implementation and the like, and have wide application prospect.
The specific scheme provided by the invention is as follows:
the invention provides a base station GNSS clock synchronization method based on EPLD, which utilizes a base station GNSS clock synchronization system to carry out clock synchronization, wherein the base station GNSS clock synchronization system comprises a GNSS clock processing module and a synchronous code stream timing module,
the GNSS clock processing module comprises a GNSS receiving module, an EPLD phase demodulation module, a CPU, dac, OCXO clock source and an EPLD frequency division module,
the synchronous code stream timing module comprises a PLL, an EPLD frequency division module and an SCC module,
receiving GPS satellite signals through a GNSS receiving module, outputting GPS PP1S signals to an EPLD phase discrimination module, outputting two paths of 10MHz signals through an OCXO clock source, dividing one path of 10MHz signals into OCXO PP1S signals through an EPLD frequency division module in the GNSS clock processing module, transmitting the OCXO PP1S signals to the EPLD phase discrimination module, carrying out phase discrimination processing on the OCXO PP1S signals and the GPS PP1S signals through the EPLD phase discrimination module, generating a phase lead or lag mark, calculating the difference value between the OCXO PP1S and the GPS PP1S, sending the difference value to a CPU through the EPLD phase discrimination module, controlling a DAC to output corresponding voltage values after the difference value is processed through the CPU, adjusting the frequency output of the OCXO clock source,
the other path of 10MHz signal output by the OCXO clock source enters the PLL, after frequency multiplication by the PLL, a plurality of paths of clock signals are output, one path of clock signal is connected to the EPLD phase discrimination module and used as a phase discrimination clock of the EPLD phase discrimination module, the other path of clock signal is divided by the EPLD frequency division module in the synchronous code stream timing module to obtain a 40ms signal and is transmitted to the SSC module for synchronous code stream timing output, the EPLD phase discrimination module is used for transmitting a PP1S signal to the EPLD frequency division module in the synchronous code stream timing module, the PP1S signal is a single pulse signal of the OCXO PP1S, and the PP1S signal is used as a synchronous reset signal of 40ms timing output of the synchronous code stream for clearing 40ms clock offset caused by external interference.
Further, in the EPLD-based base station GNSS clock synchronization method, the phase discrimination processing is performed on the OCXO PP1S signal and the GPS PP1S signal by the EPLD phase discrimination module, and a phase lead or lag flag is generated, including:
if the phase lead flag is generated, the OCXO PP1S signal leads the GPS PP1S signal, indicating that the OCXO clock source is operating at a frequency higher than 10MHz,
if the phase lag flag is generated, the OCXO PP1S signal lags the GPS PP1S signal, indicating that the OCXO clock source operating frequency is below 10MHz.
Preferably, in the method for synchronizing GNSS clocks of a base station based on EPLD, the step of processing the difference by a CPU and then controlling a DAC to output a corresponding voltage value, and adjusting the frequency output of an OCXO clock source includes:
and filtering the difference value by a CPU, controlling a DAC to output a corresponding voltage value by an SPI write register according to the processed difference value, and adjusting the frequency output of the OCXO clock source.
Preferably, in the method for synchronizing the GNSS clock of the base station based on EPLD, the GNSS receiving module receives the GPS satellite signal by using the SMA antenna, outputs the GPS PP1S signal, and performs initialization configuration on the GNSS receiving module by using the UART interface by using the CPU, so as to read the relevant signals.
Preferably, in the EPLD-based base station GNSS clock synchronization method, the PLL is an AD9523, and a 2-stage phase-locked loop is disposed inside the PLL, and outputs a 61.44MHz clock signal for synchronizing a code stream and phase discrimination.
The invention also provides a base station GNSS clock synchronization system based on the EPLD, which comprises a GNSS clock processing module and a synchronous code stream timing module,
the GNSS clock processing module comprises a GNSS receiving module, an EPLD phase demodulation module, a CPU, dac, OCXO clock source and an EPLD frequency division module,
the synchronous code stream timing module comprises a PLL, an EPLD frequency division module and an SCC module,
the GNSS receiving module receives GPS satellite signals, outputs GPS PP1S signals to the EPLD phase discrimination module, the OCXO clock source outputs two paths of 10MHz signals, one path of 10MHz signals is divided into OCXO PP1S signals by the EPLD frequency division module in the GNSS clock processing module and is transmitted to the EPLD phase discrimination module, the EPLD phase discrimination module carries out phase discrimination processing on the OCXO PP1S signals and the GPS PP1S signals to generate a phase lead or lag mark, calculates the difference value between the OCXO PP1S and the GPS PP1S, the EPLD phase discrimination module sends the difference value to a CPU, the CPU processes the difference value and then controls the DAC to output corresponding voltage value, the frequency output of the OCXO clock source is adjusted,
the other path of 10MHz signal output by the OCXO clock source enters the PLL, after the PLL frequency multiplication, a plurality of paths of clock signals are output, one path of clock signal is connected to the EPLD phase discrimination module and used as a phase discrimination clock of the EPLD phase discrimination module, the other path of clock signal is divided by the EPLD frequency division module in the synchronous code stream timing module to obtain a 40ms signal and is transmitted to the SSC module for synchronous code stream timing output, the EPLD phase discrimination module transmits a PP1S signal to the EPLD frequency division module in the synchronous code stream timing module, the PP1S signal is a single pulse signal of the OCXO PP1S, and the PP1S signal is used as a synchronous reset signal of 40ms timing output of the synchronous code stream and is used for eliminating 40ms clock offset caused by external interference.
Further, in the EPLD-based base station GNSS clock synchronization system, the EPLD phase demodulation module performs phase demodulation processing on the OCXO PP1S signal and the GPS PP1S signal, and generates a phase lead or lag flag, including:
if the phase lead flag is generated, the OCXO PP1S signal leads the GPS PP1S signal, indicating that the OCXO clock source is operating at a frequency higher than 10MHz,
if the phase lag flag is generated, the OCXO PP1S signal lags the GPS PP1S signal, indicating that the OCXO clock source operating frequency is below 10MHz.
Preferably, the method for controlling the DAC to output a corresponding voltage value after the CPU processes the difference value in the EPLD-based base station GNSS clock synchronization system, adjusting the frequency output of the OCXO clock source includes:
and filtering the difference value by a CPU, controlling a DAC to output a corresponding voltage value by an SPI write register according to the processed difference value, and adjusting the frequency output of the OCXO clock source.
Preferably, in the base station GNSS clock synchronization system based on EPLD, the GNSS receiving module receives the GPS satellite signal by using the SMA antenna, outputs the GPS PP1S signal, and the CPU performs initialization configuration on the GNSS receiving module by using the UART interface, and reads the relevant signals.
Preferably, in the EPLD-based base station GNSS clock synchronization system, the PLL is an AD9523, and a 2-stage phase-locked loop is disposed inside the PLL, and outputs a 61.44MHz clock signal for synchronizing a code stream and phase discrimination.
The invention has the advantages that:
the invention provides a base station GNSS clock synchronization method based on an EPLD, aiming at the defects of GPS deviation, phase difference oscillation and the like of a GNSS clock on a base station, the invention improves a GNSS clock synchronization system, adopts the EPLD with lower cost as a phase discriminator, a frequency divider, a CPU, a DAC and an OCXO chip to form a large phase-locked loop, the large phase-locked loop is not nested with a small phase-locked loop, the oscillation of the phase-locked loop is not caused, the PP1S of the EPLD phase discriminator is a single pulse signal of the OCXO PP1S, the EPLD phase discriminator is introduced into an SSC synchronous code stream module, and can be synchronized with the PP1S of a GNSS clock processing module every second, so that clock deviation caused by external interference is eliminated at fixed time, the GPS deviation problem is solved, and the GNSS clock synchronization of the base station also combines the long stability characteristic of GNSS and the short stability characteristic of OCXO, thereby providing a stable and reliable clock source for the whole base station equipment.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of the system module structure and interaction of the present invention.
Fig. 2 is a block diagram of the detection of a processed signal in the EPLD phase discrimination module.
Fig. 3 is a schematic diagram of a state switching of a clock synchronization system in a base station board card.
Detailed Description
The GNSS clock synchronization system may have the defects of GPS deviation, phase difference oscillation and the like. The GPS deviation fault is shown in that the clock system is in a LOCK state when seen from the BBU side, but the information obtained from RRU equipment of the base station is that the IOT is too high, and specific interference sites can be positioned by closing sites at the central position of an interference area one by one. The phase difference oscillation is represented by a sudden jump in the DIF value of the phase detector, such as a jump from "0" to "3" or "4", when the clock is in the LOCK state, and then the oscillation starts, and the clock enters the "abnormal" state from the LOCK state.
Aiming at the problems of GPS deviation, phase difference oscillation and the like in a base station, the invention provides an EPLD-based base station GNSS clock synchronization method which can solve the problems.
The present invention will be further described with reference to the accompanying drawings and specific examples, which are not intended to be limiting, so that those skilled in the art will better understand the invention and practice it.
The invention provides a base station GNSS clock synchronization method based on EPLD, which utilizes a base station GNSS clock synchronization system to carry out clock synchronization, wherein the base station GNSS clock synchronization system comprises a GNSS clock processing module and a synchronous code stream timing module,
the GNSS clock processing module comprises a GNSS receiving module, an EPLD phase demodulation module, a CPU, dac, OCXO clock source and an EPLD frequency division module,
the synchronous code stream timing module comprises a PLL, an EPLD frequency division module and an SCC module,
receiving GPS satellite signals through a GNSS receiving module, outputting GPS PP1S signals to an EPLD phase discrimination module, outputting two paths of 10MHz signals through an OCXO clock source, dividing one path of 10MHz signals into OCXO PP1S signals through an EPLD frequency division module in the GNSS clock processing module, transmitting the OCXO PP1S signals to the EPLD phase discrimination module, carrying out phase discrimination processing on the OCXO PP1S signals and the GPS PP1S signals through the EPLD phase discrimination module, generating a phase lead or lag mark, calculating the difference value between the OCXO PP1S and the GPS PP1S, sending the difference value to a CPU through the EPLD phase discrimination module, controlling a DAC to output corresponding voltage values after the difference value is processed through the CPU, adjusting the frequency output of the OCXO clock source,
the other path of 10MHz signal output by the OCXO clock source enters the PLL, after frequency multiplication by the PLL, a plurality of paths of clock signals are output, one path of clock signal is connected to the EPLD phase discrimination module and used as a phase discrimination clock of the EPLD phase discrimination module, the other path of clock signal is divided by the EPLD frequency division module in the synchronous code stream timing module to obtain a 40ms signal and is transmitted to the SSC module for synchronous code stream timing output, the EPLD phase discrimination module is used for transmitting a PP1S signal to the EPLD frequency division module in the synchronous code stream timing module, the PP1S signal is a single pulse signal of the OCXO PP1S, and the PP1S signal is used as a synchronous reset signal of 40ms timing output of the synchronous code stream for clearing 40ms clock offset caused by external interference.
In a further preferred embodiment, reference may be made to some embodiments of the inventive method, such as an improved base station GNSS clock synchronization system of the inventive method comprising a GNSS clock processing module and a synchronization code stream timing module,
the GNSS clock processing module comprises a GNSS receiving module, an EPLD phase demodulation module, a CPU, dac, OCXO clock source and an EPLD frequency division module,
the synchronous code stream timing module includes a PLL, an EPLD frequency division module, and an SCC module, and referring to fig. 1,
the GNSS receiving module receives GPS satellite signals through the SMA antenna, outputs GPS PP1S signals, communicates with the CPU through the UART interface, and the CPU carries out initialization configuration on the GNSS receiving module through the interface to read related signals.
The OCXO clock source outputs a high-precision 10MHz signal, and outputs one path of 10MHz signal to the PLL through a quarter clock Buffer for synchronizing the code stream timing module, and outputs the other path of 10MHz signal to an EPLD frequency dividing module in the GNSS clock processing module, wherein the internal frequency division of the EPLD frequency dividing module is 1Hz, namely OCXO PP1S, as shown in figure 1.
The OCXO PP1S signal and the GPS PP1S signal complete phase discrimination processing in the EPLD phase discrimination module to generate phase lead and lag marks, and if the OCXO PP1S leads to the GPS PP1S, the OCXO running frequency is higher than 10MHz; if the OCXO PP1S lags the GPS PP1S, this indicates that the OCXO operating frequency is below 10MHz. The advance and retard status flags may be reset using the OCXO PP1S Middle signal, as shown with reference to fig. 2.
After the phase discrimination processing of the OCXO PP1S and the GPS PP1S is completed in the EPLD phase discrimination module, the calculated difference DIF signal enters a CPU, the CPU firstly carries out filtering processing, then controls a DAC to output corresponding voltage values through an SPI write register, and the frequency output of the OCXO is adjusted in time according to the condition of advance or delay.
One path of 10MHz signal output by the clock buffer enters the PLL, the PLL multiplies the frequency of the 10MHz signal and outputs a plurality of paths of 61.44MHz clock signals, wherein one path of 61.44MHz signal is connected to the EPLD phase detection module and is used as a phase detection clock for the operation of the EPLD phase detector;
the other path of 61.44MHz is used for setting a synchronous code stream, 40ms signals are obtained through an EPLD frequency division module in a synchronous code stream timing module, the PP1S of an EPLD phase discrimination module is a single pulse signal of the OCXO PP1S, the single pulse signal is introduced into the EPLD frequency division module of 40ms and used as a synchronous reset signal of a 40ms counter, and thus, the 40ms timing signal used for generating the synchronous code stream is synchronous with the PP1S of the OCXO every second, and 40ms clock offset caused by external interference is eliminated in a timing way. By using the improved synchronous system, GPS deviation problem faults can be processed.
Preferably, in the embodiment of the method of the present invention, the PLL may be an AD9523, and a 2-stage phase-locked loop is provided therein, and a 61.44MHz clock signal is output for synchronizing the code stream and phase discrimination.
The GNSS receiving module can use an LEA-M8T-0GNSS time service module of ublox, and the outputtable time pulse frequency is 0.25Hz to 10MHz. The time pulse precision is less than 20ns in the Clear sky mode and less than or equal to 500ns in the loop mode.
EPLD may use LCMXO2280, a series of Mach XOs available from LatTlce. With up to 271 IOs, sysMEM embedded block RAM, distributed RAM up to 7.7KB, supporting boundary scan of IEEE Standard 1149.1, operating voltages supporting 3.3V, 1.8V.
The OXCO clock source can be OC22L5D39-10MHz, the voltage control range is 0-5V, the initial frequency precision is 0.1ppm, the frequency temperature stability is less than 3ppb, the power supply voltage frequency stability is less than 1ppb, and the load frequency stability is less than 1ppb.
The CPU can select X86, the CPU carries out initialization configuration to the GNSS module through the UART, the CPU receives signals from the EPLD after phase discrimination, the signals are subjected to filtering processing, the output of the DAC chip is controlled through the SPI interface, and the DAC outputs variable voltage to control the output frequency of the OCXO. The DAC may be DAC8550 and the CPU adjusts its output through the SPI interface.
In the application of the improved base station GNSS clock synchronization system in the method of the invention, the GNSS receiving module state can be divided into STARTUP, WARMUP, FAST, LOCK, HOLDOVER, HOLDOVERTIMEOUT and ABNORMAL. The GNSS receiving module continuously outputs PP1S, the CPU judges that 5 continuous clocks are available, and the GNSS receiving module enters a FAST state from a STARTUP state. In the FAST state, if the LOCK condition (plus or minus 10 units) is satisfied 30 times in succession, the GNSS receiving module enters the LOCK state; otherwise, the clock is not available, the state stays in FAST, and the EPLD phase difference is reset when the phase difference is too large. In the LOCK state, if the clock is not available, directly entering the HOLDOVER state; if the LOCK condition (plus or minus 30 units) is not satisfied 30 times in the continuous clock, the ABNORMAL ABNORMAL state is entered from the LOCK state. After entering the HOLDOVER state, if the clock starts to judge the phase difference after 5 continuous clocks are available, the LOCK condition (plus or minus 10 units) is satisfied 300 continuous times and the clock is available, the LOCK state can be re-entered. If the clock is not available for more than 8 hours, then the HOLDOVERTIMEOUT state is entered from the HOLDOVER state; HOLDOVER factory reset enters the initial STARTUP state. The current HOLDOVERTIMEOT state is judged for 1 time after 10 seconds each; if the clock is available for 6 consecutive determinations, the GNSS receiving module enters the WARMUP state. If the current ABNORMAL ABNORMAL state is ABNORMAL for more than 10s, the WARMUP state is entered.
The state of the GNSS receiving module can be known at any time by the CPU through the UART interface, and when the GNSS receiving module is locked, the GNSS receiving module outputs stable PP1S and TOD information. The outputted GPS PP1S and the OCXO PP1S outputted by the PLLAD9523 both enter the EPLD, phase discrimination processing is carried out in the EPLD, the processed result enters the CPU to carry out filtering processing, the CPU adjusts the output of the DAC through the SPI interface after processing, and finally the DAC adjusts the frequency output of the OCXO through the voltage-controlled pin. Namely, EPLD PD, CPU, DAC and OCXO form a large PLL, but digital PLLAD9523 is not involved in the large PLL, 61.44MHz output by digital PLLAD9523 is used for synchronous code stream timing output, and multiplexing SSC and SCK are output to each baseband board of BBU, so that clock synchronization of the whole base station system is ensured.
The method of the invention is designed aiming at the GPS deviation and phase difference oscillation problem of the GNSS clock in the base station, combines the long stability characteristic of the GNSS with the short stability characteristic of the OCXO through the EPLD and the CPU software phase discrimination filtering, and provides a stable and reliable clock source for the whole base station equipment.
The invention also provides a base station GNSS clock synchronization system based on the EPLD, which comprises a GNSS clock processing module and a synchronous code stream timing module,
the GNSS clock processing module comprises a GNSS receiving module, an EPLD phase demodulation module, a CPU, dac, OCXO clock source and an EPLD frequency division module,
the synchronous code stream timing module comprises a PLL, an EPLD frequency division module and an SCC module,
the GNSS receiving module receives GPS satellite signals, outputs GPS PP1S signals to the EPLD phase discrimination module, the OCXO clock source outputs two paths of 10MHz signals, one path of 10MHz signals is divided into OCXO PP1S signals by the EPLD frequency division module in the GNSS clock processing module and is transmitted to the EPLD phase discrimination module, the EPLD phase discrimination module carries out phase discrimination processing on the OCXO PP1S signals and the GPS PP1S signals to generate a phase lead or lag mark, calculates the difference value between the OCXO PP1S and the GPS PP1S, the EPLD phase discrimination module sends the difference value to a CPU, the CPU processes the difference value and then controls the DAC to output corresponding voltage value, the frequency output of the OCXO clock source is adjusted,
the other path of 10MHz signal output by the OCXO clock source enters the PLL, after the PLL frequency multiplication, a plurality of paths of clock signals are output, one path of clock signal is connected to the EPLD phase discrimination module and used as a phase discrimination clock of the EPLD phase discrimination module, the other path of clock signal is divided by the EPLD frequency division module in the synchronous code stream timing module to obtain a 40ms signal and is transmitted to the SSC module for synchronous code stream timing output, the EPLD phase discrimination module transmits a PP1S signal to the EPLD frequency division module in the synchronous code stream timing module, the PP1S signal is a single pulse signal of the OCXO PP1S, and the PP1S signal is used as a synchronous reset signal of 40ms timing output of the synchronous code stream and is used for eliminating 40ms clock offset caused by external interference.
The content of information interaction and execution process between the modules in the system is based on the same concept as the method embodiment of the present invention, and specific content can be referred to the description in the method embodiment of the present invention, which is not repeated here.
In the same way, the system of the invention improves the GNSS clock synchronization system aiming at the defects of GPS deviation, phase difference oscillation and the like of the GNSS clock on the base station, adopts the EPLD with lower cost as a phase discriminator and a frequency divider, and forms a large phase-locked loop together with a CPU, a DAC and an OCXO chip, the small phase-locked loop is not nested in the large phase-locked loop, the oscillation of the phase-locked loop is not caused, the PP1S of the EPLD phase discriminator is a single pulse signal of the OCXO PP1S, the single pulse signal is introduced into the SSC synchronous code stream module, the clock deviation caused by external interference is eliminated at regular time every second, the GPS deviation problem is solved, and the GNSS clock synchronization of the base station also combines the long stability characteristic of GNSS and the short stability characteristic of OCXO, thereby providing a stable and reliable clock source for the whole base station equipment.
It should be noted that not all the steps and modules in the above processes and the system structures are necessary, and some steps or modules may be omitted according to actual needs. The execution sequence of the steps is not fixed and can be adjusted as required. The system structure described in the above embodiments may be a physical structure or a logical structure, that is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities, or may be implemented jointly by some components in multiple independent devices.
The above-described embodiments are merely preferred embodiments for fully explaining the present invention, and the scope of the present invention is not limited thereto. Equivalent substitutions and modifications will occur to those skilled in the art based on the present invention, and are intended to be within the scope of the present invention. The protection scope of the invention is subject to the claims.

Claims (10)

1. An EPLD-based base station GNSS clock synchronization method is characterized in that a base station GNSS clock synchronization system is utilized for clock synchronization, the base station GNSS clock synchronization system comprises a GNSS clock processing module and a synchronous code stream timing module,
the GNSS clock processing module comprises a GNSS receiving module, an EPLD phase demodulation module, a CPU, dac, OCXO clock source and an EPLD frequency division module,
the synchronous code stream timing module comprises a PLL, an EPLD frequency division module and an SCC module,
receiving GPS satellite signals through a GNSS receiving module, outputting GPS PP1S signals to an EPLD phase discrimination module, outputting two paths of 10MHz signals through an OCXO clock source, dividing one path of 10MHz signals into OCXO PP1S signals through an EPLD frequency division module in the GNSS clock processing module, transmitting the OCXO PP1S signals to the EPLD phase discrimination module, carrying out phase discrimination processing on the OCXO PP1S signals and the GPS PP1S signals through the EPLD phase discrimination module, generating a phase lead or lag mark, calculating the difference value between the OCXO PP1S and the GPS PP1S, sending the difference value to a CPU through the EPLD phase discrimination module, controlling a DAC to output corresponding voltage values after the difference value is processed through the CPU, adjusting the frequency output of the OCXO clock source,
the other path of 10MHz signal output by the OCXO clock source enters the PLL, after frequency multiplication by the PLL, a plurality of paths of clock signals are output, one path of clock signal is connected to the EPLD phase discrimination module and used as a phase discrimination clock of the EPLD phase discrimination module, the other path of clock signal is divided by the EPLD frequency division module in the synchronous code stream timing module to obtain a 40ms signal and is transmitted to the SSC module for synchronous code stream timing output, the EPLD phase discrimination module is used for transmitting a PP1S signal to the EPLD frequency division module in the synchronous code stream timing module, the PP1S signal is a single pulse signal of the OCXO PP1S, and the PP1S signal is used as a synchronous reset signal of 40ms timing output of the synchronous code stream for clearing 40ms clock offset caused by external interference.
2. The EPLD-based base station GNSS clock synchronization method of claim 1, wherein the phase discrimination processing is performed on the OCXO PP1S signal and the GPS PP1S signal by the EPLD phase discrimination module to generate the phase lead or lag flag, comprising:
if the phase lead flag is generated, the OCXO PP1S signal leads the GPS PP1S signal, indicating that the OCXO clock source is operating at a frequency higher than 10MHz,
if the phase lag flag is generated, the OCXO PP1S signal lags the GPS PP1S signal, indicating that the OCXO clock source operating frequency is below 10MHz.
3. The EPLD-based base station GNSS clock synchronization method of claim 1 or 2, wherein the controlling the DAC to output the corresponding voltage value after the CPU processes the difference value, adjusting the frequency output of the OCXO clock source includes:
and filtering the difference value by a CPU, controlling a DAC to output a corresponding voltage value by an SPI write register according to the processed difference value, and adjusting the frequency output of the OCXO clock source.
4. The method for synchronizing GNSS clock of base station based on EPLD as claimed in claim 1, wherein the GNSS receiving module receives GPS satellite signals by using SMA antenna, outputs GPS PP1S signals, and uses UART interface to initialize the GNSS receiving module by CPU to read related signals.
5. The EPLD-based base station GNSS clock synchronization method of claim 1 wherein the PLL is an AD9523 with a 2-stage phase locked loop therein, outputting a 61.44MHz clock signal for synchronization of code streams and phase discrimination.
6. An EPLD-based base station GNSS clock synchronization system is characterized in that the base station GNSS clock synchronization system comprises a GNSS clock processing module and a synchronous code stream timing module,
the GNSS clock processing module comprises a GNSS receiving module, an EPLD phase demodulation module, a CPU, dac, OCXO clock source and an EPLD frequency division module,
the synchronous code stream timing module comprises a PLL, an EPLD frequency division module and an SCC module,
the GNSS receiving module receives GPS satellite signals, outputs GPS PP1S signals to the EPLD phase discrimination module, the OCXO clock source outputs two paths of 10MHz signals, one path of 10MHz signals is divided into OCXO PP1S signals by the EPLD frequency division module in the GNSS clock processing module and is transmitted to the EPLD phase discrimination module, the EPLD phase discrimination module carries out phase discrimination processing on the OCXO PP1S signals and the GPS PP1S signals to generate a phase lead or lag mark, calculates the difference value between the OCXO PP1S and the GPS PP1S, the EPLD phase discrimination module sends the difference value to a CPU, the CPU processes the difference value and then controls the DAC to output corresponding voltage value, the frequency output of the OCXO clock source is adjusted,
the other path of 10MHz signal output by the OCXO clock source enters the PLL, after the PLL frequency multiplication, a plurality of paths of clock signals are output, one path of clock signal is connected to the EPLD phase discrimination module and used as a phase discrimination clock of the EPLD phase discrimination module, the other path of clock signal is divided by the EPLD frequency division module in the synchronous code stream timing module to obtain a 40ms signal and is transmitted to the SSC module for synchronous code stream timing output, the EPLD phase discrimination module transmits a PP1S signal to the EPLD frequency division module in the synchronous code stream timing module, the PP1S signal is a single pulse signal of the OCXO PP1S, and the PP1S signal is used as a synchronous reset signal of 40ms timing output of the synchronous code stream and is used for eliminating 40ms clock offset caused by external interference.
7. The EPLD-based base station GNSS clock synchronization system of claim 6, wherein said EPLD phase discrimination module performs phase discrimination processing on OCXO PP1S signals and GPS PP1S signals to generate phase lead or lag flags, comprising:
if the phase lead flag is generated, the OCXO PP1S signal leads the GPS PP1S signal, indicating that the OCXO clock source is operating at a frequency higher than 10MHz,
if the phase lag flag is generated, the OCXO PP1S signal lags the GPS PP1S signal, indicating that the OCXO clock source operating frequency is below 10MHz.
8. The EPLD-based base station GNSS clock synchronization system of claim 6 or 7, wherein the CPU processes the difference value and then controls the DAC to output a corresponding voltage value, adjusts the frequency output of the OCXO clock source, and includes:
and filtering the difference value by a CPU, controlling a DAC to output a corresponding voltage value by an SPI write register according to the processed difference value, and adjusting the frequency output of the OCXO clock source.
9. The EPLD-based base station GNSS clock synchronization system of claim 6, wherein the GNSS receiving module receives GPS satellite signals using SMA antenna, outputs GPS PP1S signals, and the CPU uses UART interface to perform an initialization configuration of the GNSS receiving module, and reads the relevant signals.
10. The EPLD-based base station GNSS clock synchronization system of claim 6, wherein the PLL is an AD9523 with a 2-stage phase locked loop therein, outputting a 61.44MHz clock signal for synchronization of code streams and phase discrimination.
CN202211130831.1A 2022-09-16 2022-09-16 Base station GNSS clock synchronization method and system based on EPLD Pending CN116033539A (en)

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